View source for PIC instruction listings

The [[PIC microcontroller|PIC]] [[instruction set]] refers to the set of instructions that [[Microchip Technology]] PIC or dsPIC [[microcontroller]] supports. The instructions are usually programmed into the [[Flash memory]] of the processor, and automatically executed by the microcontroller on startup.

PICmicro chips have a [[Harvard architecture]] and instruction words have unusual sizes. Originally, 12-bit instructions included 5 address bits to specify the memory operand, and 9-bit branch destinations.  Later revisions added opcode bits, allowing additional address bits.

They are [[accumulator machine]]s, with a common accumulator "W" being one operand in all 2-operand instructions.

In the instruction set tables that follow, register numbers are referred to as "f", while constants are referred to as "k".  Bit numbers (0–7) are selected by "b".  Arithmetic instructions write their result to one of the inputs selected by the "d" bit: 0 indicates W, while 1 indicates that the result is written back to source register f.  The C and Z status flags may be set based on the result; otherwise they are unmodified.  Add and subtract (but not rotate) instructions that set C also set the DC (digit carry) flag, the carry from bit 3 to bit 4, which is useful for [[binary-coded decimal|BCD]] arithmetic.

==Architecture==

Memory operands are also referred to as "registers".  Most are simply general-purpose storage (RAM), while some locations are reserved for ''special function registers''.  Except for a single accumulator (called <code>W</code>), almost all other registers are memory-mapped, even registers like the [[program counter]] and ALU [[status register]].  (The other exceptions, which are not memory-mapped, are the return address stack, and the [[Three-state logic|tri-state]] registers used to configure the [[GPIO]] pins.)

Some arithmetic instructions only use one of their inputs, but still use a <code>d</code>bit.  For example, <code>MOVW</code> copies the value of <code>W</code> to the destination.  When used with <code>d</code> = 1, this stores <code>W</code> to <code>f</code>.  When used with <code>d</code> = 0, this performs [[NOP (code)|no operation]].  There is a matching <code>MOVF</code> instruction which outputs the value of <code>f</code>.  When used with <code>d</code> = 0, this loads <code>f</code> into <code>W</code>.  When used with <code>d</code> = 1, the only visible effect is to set the [[zero flag]] depending on the value of <code>f</code>.

The instruction set does not contain conditional branch instructions.  Instead, it contains conditional skip instructions which cause the following instruction to be ignored.  A conditional skip followed by an unconditional branch performs a conditional branch.  The skip instructions test any bit of any register.  The ALU status register is one possibility.

Memory operands are specified by [[Addressing mode#Absolute or direct|absolute address]]; the location is fixed at [[compile time]].  To provide indirect addressing, a pair of special function registers are provided:
* The ''file select register'' (<code>FSR</code>) is written with the address of the desired memory operand, after which
* The ''indirect file'' register (<code>INDF</code>) becomes an [[Aliasing (computing)|alias]] for the operand [[pointer (computer programming)|pointed to]] by the FSR.

This mechanism also allows up to 256 bytes of memory to be addressed, even when the instruction set only allows 5- or 7-bit absolute addresses.  Models with more registers (special function registers plus RAM) than fit into the instruction provide multiple banks of memory, and use one of two mechanisms for accessing them:
# Most baseline core devices, and some mid-range core devices, use the high-order bits of the file select register to select the current register bank.
# More recent models have a separate ''bank select register'', and a <code>MOVLB</code> instruction to set it.

PIC processors with more than 256 words of program use paged memory.  The internal program counter and return stack are as wide as necessary to address all memory, but only the low 8 bits are visible to software in the <code>PCL</code> ("PC low") register.  There is an additional <code>PCLATH</code> ("PC latch high") register which is only modified by software.  Any operation which does not specify the full destination address (such as a 9-bit <code>GOTO</code> or an 8-bit write to the PCL register) fills in the additional high bits from the corresponding part of PCLATH.  (Some PIC18 processors extend this beyond 16 bits with a PCLATU register to supply bits 16–23.)

==Baseline core devices (12 bit)==

{|class="wikitable" style="text-align:center"
|+ 12-bit PIC instruction set
! 1<br/>1 || 1<br/>0 || <br/>9 || <br/>8 || <br/>7 ||<br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || C<br/>? || Z<br/>? || Description
|-
|colspan=16|
|-
! 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=5| ''opcode'' ||colspan=4| Miscellaneous instructions
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||align=left| NOP || || ||align=left| No operation (MOVW 0,W)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 ||align=left| OPTION || || ||align=left| Copy W to OPTION register
|- 
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 ||align=left| SLEEP || || ||align=left| Go into standby mode
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 ||align=left| CLRWDT || || ||align=left| Restart watchdog timer
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=2| ''f'' ||align=left| TRIS ''f'' || || ||align=left| Copy W to tri-state register (''f'' = 1, 2 or 3)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 ||colspan=3| ''k'' ||align=left| MOVLB ''k''<sup>*</sup> || || ||align=left| Set bank select register to ''k''
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || 1 || 0 ||align=left| RETURN<sup>†</sup> || || ||align=left| Return from subroutine, W unmodified
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || 1 || 1 ||align=left| RETFIE<sup>†</sup> || || ||align=left| Return from interrupt; return & enable interrupts
|-
|colspan=16|
|-
! 0 || 0 ||colspan=4| ''opcode'' || ''d'' || colspan=5| ''register'' ||colspan=4| ALU operations: dest ← OP(f,W)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=5| ''f'' ||align=left| MOVWF ''f'' || || ||align=left| f ← W
|-
| 0 || 0 || 0 || 0 || 0 || 1 || ''d'' ||colspan=5| ''f'' ||align=left| CLR ''f'',''d'' || || Z ||align=left| dest ← 0, usually written CLRW or CLRF ''f''
|-
| 0 || 0 || 0 || 0 || 1 || 0 || ''d'' ||colspan=5| ''f'' ||align=left| SUBWF ''f'',''d'' || C || Z ||align=left| dest ← f−W (dest ← f+~W+1)
|-
| 0 || 0 || 0 || 0 || 1 || 1 || ''d'' ||colspan=5| ''f'' ||align=left| DECF ''f'',''d'' || || Z ||align=left| dest ← f−1
|-
| 0 || 0 || 0 || 1 || 0 || 0 || ''d'' ||colspan=5| ''f'' ||align=left| IORWF ''f'',''d'' || || Z ||align=left| dest ← f {{pipe}} W, logical inclusive or
|-
| 0 || 0 || 0 || 1 || 0 || 1 || ''d'' ||colspan=5| ''f'' ||align=left| ANDWF ''f'',''d'' || || Z ||align=left| dest ← f & W, logical and
|-
| 0 || 0 || 0 || 1 || 1 || 0 || ''d'' ||colspan=5| ''f'' ||align=left| XORWF ''f'',''d'' || || Z ||align=left| dest ← f ^ W, logical exclusive or
|-
| 0 || 0 || 0 || 1 || 1 || 1 || ''d'' ||colspan=5| ''f'' ||align=left| ADDWF ''f'',''d'' || C || Z ||align=left| dest ← f+W
|-
| 0 || 0 || 1 || 0 || 0 || 0 || ''d'' ||colspan=5| ''f'' ||align=left| MOVF ''f'',''d'' || || Z ||align=left| dest ← f
|-
| 0 || 0 || 1 || 0 || 0 || 1 || ''d'' ||colspan=5| ''f'' ||align=left| COMF ''f'',''d'' || || Z ||align=left| dest ← ~f, bitwise complement
|-
| 0 || 0 || 1 || 0 || 1 || 0 || ''d'' ||colspan=5| ''f'' ||align=left| INCF ''f'',''d'' || || Z ||align=left| dest ← f+1
|-
| 0 || 0 || 1 || 0 || 1 || 1 || ''d'' ||colspan=5| ''f'' ||align=left| DECFSZ ''f'',''d'' || || ||align=left| dest ← f−1, then skip if zero
|-
| 0 || 0 || 1 || 1 || 0 || 0 || ''d'' ||colspan=5| ''f'' ||align=left| RRF ''f'',''d'' || C || ||align=left| dest ← CARRY<<7 {{pipe}} f>>1, rotate right through carry
|-
| 0 || 0 || 1 || 1 || 0 || 1 || ''d'' ||colspan=5| ''f'' ||align=left| RLF ''f'',''d'' || C || ||align=left| dest ← F<<1 {{pipe}} CARRY, rotate left through carry
|-
| 0 || 0 || 1 || 1 || 1 || 0 || ''d'' ||colspan=5| ''f'' ||align=left| SWAPF ''f'',''d'' || || ||align=left| dest ← f<<4 {{pipe}} f>>4, swap nibbles
|-
| 0 || 0 || 1 || 1 || 1 || 1 || ''d'' ||colspan=5| ''f'' ||align=left| INCFSZ ''f'',''d'' || || ||align=left| dest ← f+1, then skip if zero
|-
|colspan=16|
|-
! 0 || 1 ||colspan=2| ''opc'' ||colspan=3| ''bit'' ||colspan=5| ''register'' ||colspan=4| Bit operations
|-
| 0 || 1 || 0 || 0 ||colspan=3| ''bit'' ||colspan=5| ''f'' ||align=left| BCF ''f'',''b'' || || ||align=left| Clear bit b of f
|-
| 0 || 1 || 0 || 1 ||colspan=3| ''bit'' ||colspan=5| ''f'' ||align=left| BSF ''f'',''b'' || || ||align=left| Set bit b of f
|-
| 0 || 1 || 1 || 0 ||colspan=3| ''bit'' ||colspan=5| ''f'' ||align=left| BTFSC ''f'',''b'' || || ||align=left| Skip if bit b of f is clear
|-
| 0 || 1 || 1 || 1 ||colspan=3| ''bit'' ||colspan=5| ''f'' ||align=left| BTFSS ''f'',''b'' || || ||align=left| Skip if bit b of f is set
|-
|colspan=16|
|-
! 1 || 0 ||colspan=2| ''opc'' ||colspan=8| ''k'' ||colspan=4| Control transfers
|-
| 1 || 0 || 0 || 0 ||colspan=8| ''k'' ||align=left| RETLW ''k'' || || ||align=left| Set W ← k, then return from subroutine
|-
| 1 || 0 || 0 || 1 ||colspan=8| ''k'' ||align=left| CALL ''k'' || || ||align=left| Call subroutine, 8-bit address k
|-
| 1 || 0 || 1 ||colspan=9| ''k'' ||align=left| GOTO ''k'' || || ||align=left| Jump to 9-bit address k<ref>{{Cite book 
  |publisher=Microchip Technology 
  |year=2007 
  |url=http://ww1.microchip.com/downloads/en/DeviceDoc/41239D.pdf 
  |title=PIC10F200/202/204/206 Data Sheet 
  |page=52 
  |access-date=2015-01-15 
  |archive-url=https://web.archive.org/web/20150811030147/http://ww1.microchip.com/downloads/en/DeviceDoc/41239D.pdf 
  |archive-date=2015-08-11 
  |url-status=dead 
  }}</ref>
|-
|colspan=16|
|-
! 1 || 1 ||colspan=2| ''opc'' ||colspan=8| ''8-bit immediate'' ||colspan=4| Operations with W and 8-bit literal: W ← OP(k,W)
|-
| 1 || 1 || 0 || 0 ||colspan=8| ''k'' ||align=left| MOVLW ''k'' || || ||align=left| W ← k
|-
| 1 || 1 || 0 || 1 ||colspan=8| ''k'' ||align=left| IORLW ''k'' || || Z ||align=left| W ← k {{pipe}} W, bitwise logical or
|-
| 1 || 1 || 1 || 0 ||colspan=8| ''k'' ||align=left| ANDLW ''k'' || || Z ||align=left| W ← k & W, bitwise and
|-
| 1 || 1 || 1 || 1 ||colspan=8| ''k'' ||align=left| XORLW ''k'' || || Z ||align=left| W ← k ^ W, bitwise exclusive or
|-
|colspan=16|
|-
! 1<br/>1 || 1<br/>0 || <br/>9 || <br/>8 || <br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || C<br/>? || Z<br/>? || Description
|}
<nowiki/>*: Extended instruction, not available on most 12-bit PICs.  Of the models with extended RAM, most (e.g. 16C5x, 16F5x) extend the register address space using the high-order bits of the FSR.  A few (e.g. PIC12F529T39A) have a separate bank select register which can be set with this instruction.<br/>
†: Extended instruction, only available on "enhanced baseline" PICs.  Only the very few models (16F527, 16F570, MCV20A) with interrupt support (and a 4-level stack) include these instructions. All such models also include MOVLB.

==ELAN Microelectronics clones (13 bit)==
[[List of common microcontrollers#ELAN Microelectronics Corp.|ELAN Microelectronics Corp.]] make a series of PICmicro-like microcontrollers with a 13-bit instruction word.<ref>{{Cite web|url=http://www.emc.com.tw/eng/products.asp|title = 義隆電子股份有限公司義隆電子，再創未來！}}</ref>  The instructions are mostly compatible with the mid-range 14-bit instruction set, but limited to a 6-bit register address (16 special-purpose registers and 48 bytes of RAM) and a 10-bit (1024 word) program space.

The 10-bit program counter is accessible as R2.  Reads access only the low bits, and writes clear the high bits.  An exception is the TBL instruction, which modifies the low byte while preserving bits 8 and 9.

The 7 accumulator-immediate instructions are renumbered relative to the 14-bit PICmicro, to fit into 3 opcode bits rather than 4, but they are all there, as well as an additional software interrupt instruction.

There are a few additional miscellaneous instructions, and there are some changes to the terminology (the PICmicro OPTION register is called the CONTrol register; the PICmicro TRIS registers 1–3 are called I/O control registers 5–7), but the equivalents are obvious.

{|class="wikitable" style="text-align:center"
|+ 13-bit EM78 instruction set<ref>{{Citation |url=http://www.emc.com.tw/upload/2019_01_15(0_0)b2/EM78P157N.pdf#page=36 |title=EM78P157N 8-bit microcontroller with OTP ROM Product Specification |version=version 1.3 |date=26 April 2016 |author=ELAN Microelectronics Corp. |access-date=2020-06-06 |archive-url=https://web.archive.org/web/20160304054645/http://www.emc.com.tw/eng/database/Data_Sheet/8BIT/EM78P157N.pdf#page=36 |archive-date=2016-03-04 |url-status=live}}</ref><ref name=EM78P143>{{Citation |url=http://www.emc.com.tw/upload/2019_01_15(0_0)b2/EM78P143.pdf#page=83 |title=EM78P143 8-bit microprocessor with OTP ROM Product Specification |version=version 1.7 |date=25 April 2016 |author=ELAN Microelectronics Corp. |access-date=2020-06-06 |page=77}}</ref>
! 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 || <br/>8 || <br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || C<br/>? || Z<br/>? || Description
|-
|colspan=17|
|-
! 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=6| ''opcode'' ||colspan=4| Miscellaneous instructions
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||align=left| NOP<sup>*</sup> || || ||align=left| No operation (MOVW 0,W)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||align=left| DAA<sup>†</sup> || C || ||align=left| [[Intel BCD opcodes#Adding|Decimal Adjust after Addition]]
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 ||align=left| CONTW<sup>*</sup> || || ||align=left| Write CONT register (CONT ← W)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 ||align=left| SLEP<sup>*</sup> || || ||align=left| Go into standby mode (WDT ← 0, stop clock)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 ||align=left| WDTC<sup>*</sup> || || ||align=left| Restart watchdog timer (WDT ← 0)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=4| ''f'' ||align=left| IOW ''f''{{prime||f|c=<sup>†</sup>}} || || ||align=left| Copy W to I/O control register (''f'' = 5–7, 11–15)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 || 0 ||align=left| ENI<sup>†</sup> || || ||align=left| Enable interrupts
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 || 1 ||align=left| DISI<sup>†</sup> || || ||align=left| Disable interrupts
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 1 || 0 ||align=left| RET || || ||align=left| Return from subroutine, W unmodified
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 1 || 1 ||align=left| RETI || || ||align=left| Return from interrupt; return & enable interrupts
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 || 0 || 0 ||align=left| CONTR<sup>†</sup> || || ||align=left| Read CONT register (W ← CONT)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=4| ''f'' ||align=left| IOR ''f''{{prime||f|c=<sup>†</sup>}} || || ||align=left| Copy I/O control register to W  (''f'' = 5–7, 11–15)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 || 0 || 0 ||align=left| TBL<sup>†</sup> || C || Z ||align=left| PCL += W, preserve PC bits 8 & 9
|-
|colspan=17|
|-
! 0 || 0 ||colspan=4| ''opcode'' || ''d'' ||colspan=6| ''register'' ||colspan=4| ALU operations same as 12- and 14-bit PIC
|-
! 0 || 1 ||colspan=2| ''opc'' ||colspan=3| ''bit'' ||colspan=6| ''register'' ||colspan=4| Bit operations same as 12- and 14-bit PIC
|-
! 1 || 0 || ''c'' ||colspan=10| ''k'' ||colspan=4| Control transfers same as 14-bit PIC
|-
|colspan=17|
|-
! 1 || 1 ||colspan=3| ''opcode'' ||colspan=8| ''8-bit immediate'' ||colspan=4| Operations with W and 8-bit literal: W ← OP(k,W)
|-
| 1 || 1 || 0 ||colspan=2| ''op'' ||colspan=8| ''k'' ||colspan=4| MOV/IOR/AND/XOR, same as 12-bit PIC
|-
| 1 || 1 || 1 || 0 || 0 ||colspan=8| ''k'' ||align=left| RETLW ''k'' || || ||align=left| W ← k, then return from subroutine
|-
| 1 || 1 || 1 || 0 || 1 ||colspan=8| ''k'' ||align=left| SUBLW ''k'' || C || Z ||align=left| W ← k−W (W ← k+~W+1)
|-
| 1 || 1 || 1 || 1 || 0 || 0 ||colspan=7| ''k'' ||align=left| INT ''k''<sup>†</sup> || || ||align=left| Push PC, PC ← k (software interrupt, usually k=1)
|-
| 1 || 1 || 1 || 1 || 1 ||colspan=8| ''k'' ||align=left| ADDLW ''k'' || C || Z ||align=left| W ← k+W
|-
|colspan=17|
|-
! 1 || 1 || 1 || 1 || 0 || 1 ||colspan=3| ''opcode'' ||colspan=4| ''k'' ||colspan=4| Extensions (replacing INT ''k'' for ''k''≥128 on later models){{r|EM78P143}}<ref>{{Citation |url=http://www.emc.com.tw/Twn/database/Data_Sheet/8BIT/EM78P346N.pdf#page=85 |title=EM78P346N 8-bit microprocessor with OTP ROM Product Specification |version=version 1.5 |date=April 2016 |author=ELAN Microelectronics Corp. |access-date=2019-07-11 |page=77}}</ref><ref>{{Citation |url=http://www.emc.com.tw/twn/database/Data_Sheet/COM/EM78860.pdf#page=17 |title=EM78860 8-bit Micro-controller |date=17 April 2000 |author=ELAN Microelectronics Corp. |access-date=2019-07-11 |page=17}}</ref>
|-
| 1 || 1 || 1 || 1 || 0 || 1 || 0 || 0 || 0 ||colspan=4| ''k'' ||align=left| PAGE ''k'' || || ||align=left| Select ROM page ''k'' (like MOVLP ''k'')
|-
| 1 || 1 || 1 || 1 || 0 || 1 || 0 || 0 || 1 ||colspan=4| ''k'' ||align=left| BANK ''k''<sup>†</sup> || || ||align=left| Select RAM bank ''k''
|-
| 1 || 1 || 1 || 1 || 0 || 1 || 0 || 1 || 0 ||colspan=4| ''k'' ||align=left| LCALL ''k''<sup>†</sup> || || ||align=left| Long call with 17-bit address (2-word instruction)
|-
| 1 || 1 || 1 || 1 || 0 || 1 || 0 || 1 || 1 ||colspan=4| ''k'' ||align=left| LJMP ''k''<sup>†</sup> || || ||align=left| Long jump with 17-bit address (2-word instruction)
|-
| 1 || 1 || 1 || 1 || 0 || 1 || 1 ||colspan=6| ''f'' ||align=left| TBRD ''f''{{prime||f|c=<sup>†</sup>}} || || ||align=left| Read ROM at TBHP:TBLP into specified register
|-
|colspan=17|
|-
! 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 || <br/>8 || <br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || C<br/>? || Z<br/>? || Description
|}
<nowiki/>*: Same opcode as 12-bit PIC<br>
†: Instruction unique to EM78 instruction set with no PIC equivalent

Some models support multiple ROM or RAM banks, in a manner similar to other PIC microcontrollers.

There is also a 15-bit variant of the instruction set, which is almost identical except that the register numbers are enlarged to 8 bits and the call and jump addresses are enlarged to 12 bits.  Other differences:<ref>{{Citation |url=http://www.emc.com.tw/twn/database/Data_Sheet/8BIT/EM78F641N.pdf#page=174 |title=EM78F648/644/642/641N/548/544/542/541N Flash Series 8-Bit Microcontroller Product Specification |version=version 1.2 |date=15 March 2013 |author=ELAN Microelectronics Corp. |access-date=2019-07-11 |pages=162–165}}</ref>
* The CONTW, IOW, CONTR, IOR and INT instructions are deleted,
* Operations with an 8-bit literal have two 0 bits added as bits 8 and 9,
* Extensions with a 4-bit literal have two 0 bits added as bits 4 and 5, and
* The PAGE and BANK instructions are renamed SBANK and GBANK and perform bank switching on special function registers and general-purpose RAM, respectively.

A second generation 15-bit instruction set includes several additional instructions:
{|class="wikitable" style="text-align:center"
|+ 15-bit EM78/EM88 instruction set extensions<ref>Derived from instruction encoding tables in Elan [http://www.emc.com.tw/eng/database/Sa2/Gp/Dt/eUIDEII_v2.19.60.14.rar eUIDE II v2.19.60.14], released 2019-05-01, accessed 2019-07-13.  Specifically the <code>Bin/*.cfg</code> files.</ref><ref>{{Citation |url=http://www.emc.com.tw/eng/database/Sa2/Gp/PG/EM78xxx15-bit%20Instruction%20Set%20_20140114_.pdf |title=EM78XXX 15-Bit Instruction Set |date=2014-01-14 |author=ELAN Microelectronics Corp. |access-date=2019-07-13}}</ref>
! 1<br/>4 || 1<br/>3 || 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 || <br/>8 || <br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || C<br/>? || Z<br/>? || Description
|-
|colspan=19|
|-
! 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=7| ''opcode'' ||colspan=4| Miscellaneous instructions
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||align=left| NOP<sup>*</sup> || || ||align=left| No operation (MOVW 0,W)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||align=left| DAA<sup>*</sup> || C || ||align=left| [[Intel BCD opcodes#Adding|Decimal Adjust after Addition]]
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 ||align=left| SLEP<sup>*</sup> || || ||align=left| Go into standby mode (WDT ← 0, stop clock)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 ||align=left| WDTC<sup>*</sup> || || ||align=left| Restart watchdog timer (WDT ← 0)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 ||align=left| MULW<sup>†</sup> || || ||align=left| 8×8 → 16-bit multiply
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 ||align=left| DIVW<sup>†</sup> || || ||align=left| 8÷8 → 8,8-bit divide
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 || 0 ||align=left| ENI<sup>*</sup> || || ||align=left| Enable interrupts
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 || 1 ||align=left| DISI<sup>*</sup> || || ||align=left| Disable interrupts
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 1 || 0 ||align=left| RET<sup>*</sup> || || ||align=left| Return from subroutine, W unmodified
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 1 || 1 ||align=left| RETI<sup>*</sup> || || ||align=left| Return from interrupt; return & enable interrupts
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 || 1 || 0 ||align=left| RESET || || ||align=left| Software reset
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 || 1 || 1 ||align=left| TBWR || || ||align=left| Flash ROM write
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=6| ''k'' ||align=left| INT ''k'' || || ||align=left| Software interrupt at address 2×k
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=3| ''bit'' ||colspan=4| ''f'' ||align=left| BTG ''f'',''b'' || || ||align=left| Invert (toggle) bit b of f (limited address range)
|-
|colspan=19|
|-
! 0 || 0 ||colspan=4| ''opcode'' || ''d'' ||colspan=8| ''register'' ||colspan=4| ALU operations same as EM78 and PIC
|-
! 0 || 1 ||colspan=2| ''opc'' ||colspan=3| ''bit'' ||colspan=8| ''register'' ||colspan=4| Bit operations same as EM78 and PIC
|-
! 1 || 0 || ''c'' ||colspan=12| ''k'' ||colspan=4| Control transfers same as EM78 and 14-bit PIC
|-
|colspan=19|
|-
! 1 || 1 ||colspan=3| ''opcode'' || 0 || 0 ||colspan=8| ''8-bit immediate'' ||colspan=4| Operations with 8-bit literal same as EM78 (except INT)
|-
! 1 || 1 ||colspan=5| ''opcode'' ||colspan=8| ''register or immediate'' ||colspan=4| Instruction set extensions
|-
| 1 || 1 || 0 || 0 || 0 || 0 || 1 ||colspan=8| ''f'' ||align=left| JE ''r'' || || ||align=left| Skip if W = f
|-
| 1 || 1 || 0 || 0 || 0 || 1 || 0 ||colspan=8| ''f'' ||align=left| JGE ''r'' || || ||align=left| Skip if W > f
|-
| 1 || 1 || 0 || 0 || 0 || 1 || 1 ||colspan=8| ''f'' ||align=left| JLE ''r'' || || ||align=left| Skip if W < f
|-
| 1 || 1 || 0 || 0 || 1 || 0 || 1 ||colspan=8| ''k'' ||align=left| JE ''k'' || || ||align=left| Skip if W = k
|-bgcolor=lightgrey
| 1 || 1 || 0 || 0 || 1 || 1 || 0 ||colspan=8| ''k'' ||align=left colspan=4| ''(reserved)''
|-
| 1 || 1 || 0 || 0 || 1 || 1 || 1 ||colspan=8| ''f'' ||align=left| TBRDA ''f'' || || ||align=left| Read ROM at TBHP:TBLP into f; msbits into W
|-
| 1 || 1 || 0 || 1 || 0 || 0 || 1 ||colspan=8| ''k'' ||align=left| SJC ''address'' || || ||align=left| Jump to PC + sext(''k'') if carry set
|-
| 1 || 1 || 0 || 1 || 0 || 1 || 0 ||colspan=8| ''k'' ||align=left| SJNC ''address'' || || ||align=left| Jump to PC + sext(''k'') if carry clear
|-
| 1 || 1 || 0 || 1 || 0 || 1 || 1 ||colspan=8| ''k'' ||align=left| SJZ ''address'' || || ||align=left| Jump to PC + sext(''k'') if zero flag set
|-
| 1 || 1 || 0 || 1 || 1 || 0 || 1 ||colspan=8| ''k'' ||align=left| SJNZ ''address'' || || ||align=left| Jump to PC + sext(''k'') if zero flag clear
|-
| 1 || 1 || 0 || 1 || 1 || 1 || ''d'' ||colspan=8| ''f'' ||align=left| RR ''f''/RRA || || ||align=left| dest ← f<<7 | f>>1, rotate right without carry
|-
| 1 || 1 || 1 || 0 || 0 || 0 || 1 ||colspan=8| ''f'' ||align=left| XCH ''f'' || || ||align=left| Exchange f ↔ W
|-
| 1 || 1 || 1 || 0 || 0 || 1 || ''d'' ||colspan=8| ''f'' ||align=left| RL ''f''/RLA || || ||align=left| dest ← f<<1 | f>>7, rotate left without carry
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 1 ||colspan=8| ''f'' ||align=left| MUL ''f''{{prime||f|c=<sup>‡</sup>}} || || ||align=left| PRODH:PRODL ←  f × W
|-bgcolor=lightgrey
| 1 || 1 || 1 || 0 || 1 || 1 || ''x'' ||colspan=8| ''k'' ||colspan=4 align=left| ''(reserved)''
|-
| 1 || 1 || 1 || 1 || 0 || 0 || ''d'' ||colspan=8| ''f'' ||align=left| SUBB || C || Z ||align=left| dest ← f + ~W + C, subtract with carry
|-
| 1 || 1 || 1 || 1 || 0 || 1 || 0 || 0 || 0 || 0 || 0 ||colspan=4| ''k'' ||align=left| SBANK ''k''<sup>*</sup> || || ||align=left| Select special function register bank ''k''
|-
| 1 || 1 || 1 || 1 || 0 || 1 || 0 || 0 || 1 || 0 || 0 ||colspan=4| ''k'' ||align=left| GBANK ''k''<sup>*</sup> || || ||align=left| Select RAM bank ''k''
|-
| 1 || 1 || 1 || 1 || 0 || 1 || 0 || 1 || 0 || 0 || 0 ||colspan=4| ''k'' ||align=left| LCALL ''k''<sup>*</sup> || || ||align=left| Long call with 19-bit address (2-word instruction)
|-
| 1 || 1 || 1 || 1 || 0 || 1 || 0 || 1 || 1 || 0 || 0 ||colspan=4| ''k'' ||align=left| LJMP ''k''<sup>*</sup> || || ||align=left| Long jump with 19-bit address (2-word instruction)
|-
| 1 || 1 || 1 || 1 || 0 || 1 || 1 ||colspan=8| ''f'' ||align=left| TBRD ''f''{{prime||f|c=<sup>*</sup>}} || || ||align=left| Read ROM at TBHP:TBLP into f
|-
| 1 || 1 || 1 || 1 || 1 || 0 || 1 ||colspan=8| ''f'' ||align=left| NEG ''f'' || C || Z ||align=left| f ← −f (f ← ~f + 1), negate
|-
| 1 || 1 || 1 || 1 || 1 || 1 || ''d'' ||colspan=8| ''f'' ||align=left| ADC ''f'' || C || Z ||align=left| dest ← f + W + C, add with carry
|-
|}
<nowiki/>*: Same opcode as 13-bit EM78<br/>
†: Only on EM89F768N; operands and results in special registers<br/>
‡: Only on EM88F794N, MTF213 and MTF351

==Mid-range core devices (14 bit)==
These devices feature a 14-bit wide code memory, and an improved 8 level deep call stack. The instruction set differs very little from the baseline devices, but the 2 additional opcode bits allow 128 registers and 2048 words of code to be directly addressed.  There are a few additional miscellaneous instructions, and two additional 8-bit literal instructions, add and subtract.  The mid-range core is available in the majority of devices labeled PIC12 and PIC16.

{|class="wikitable" style="text-align:center"
|+ 14-bit PIC instruction set
! 1<br/>3 || 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 ||<br/>8 ||<br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || C<br/>? || Z<br/>? || Description
|-
|colspan=18|
|-
! 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=7| ''opcode'' ||colspan=4| Miscellaneous instructions
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||align=left| NOP || || ||align=left| No operation (MOVW 0,W)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 ||align=left| RETURN || || ||align=left| Return from subroutine, W unmodified
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 1 ||align=left| RETFIE || || ||align=left| Return from interrupt
|- style="background:lightgrey;"
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 0 || 1 || 0 ||align=left| OPTION || || ||align=left| Copy W to OPTION register ''(deprecated)''
|- 
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 0 || 1 || 1 ||align=left| SLEEP || || ||align=left| Go into standby mode
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 1 || 0 || 0 ||align=left| CLRWDT || || ||align=left| Restart watchdog timer
|- style="background:lightgrey;"
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 1 ||colspan=2| ''f'' ||align=left| TRIS ''f'' || || ||align=left| Copy W to tri-state register (''f'' = 1, 2 or 3) ''(deprecated)''
|-
|colspan=18|
|-
! 0 || 0 ||colspan=4| ''opcode'' || ''d'' ||colspan=7| ''register'' ||colspan=4| ALU operations: dest ← OP(f,W)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=7| ''f'' ||align=left| MOVWF ''f'' || || ||align=left| f ← W
|-
| 0 || 0 || 0 || 0 || 0 || 1 || ''d'' ||colspan=7| ''f'' ||align=left| CLR ''f'',''d'' || || Z ||align=left| dest ← 0, usually written CLRW or CLRF ''f''
|-
| 0 || 0 || 0 || 0 || 1 || 0 || ''d'' ||colspan=7| ''f'' ||align=left| SUBWF ''f'',''d'' || C || Z ||align=left| dest ← f−W (dest ← f+~W+1)
|-
| 0 || 0 || 0 || 0 || 1 || 1 || ''d'' ||colspan=7| ''f'' ||align=left| DECF ''f'',''d'' || || Z ||align=left| dest ← f−1
|-
| 0 || 0 || 0 || 1 || 0 || 0 || ''d'' ||colspan=7| ''f'' ||align=left| IORWF ''f'',''d'' || || Z ||align=left| dest ← f {{pipe}} W, logical inclusive or
|-
| 0 || 0 || 0 || 1 || 0 || 1 || ''d'' ||colspan=7| ''f'' ||align=left| ANDWF ''f'',''d'' || || Z ||align=left| dest ← f & W, logical and
|-
| 0 || 0 || 0 || 1 || 1 || 0 || ''d'' ||colspan=7| ''f'' ||align=left| XORWF ''f'',''d'' || || Z ||align=left| dest ← f ^ W, logical exclusive or
|-
| 0 || 0 || 0 || 1 || 1 || 1 || ''d'' ||colspan=7| ''f'' ||align=left| ADDWF ''f'',''d'' || C || Z ||align=left| dest ← f+W
|-
| 0 || 0 || 1 || 0 || 0 || 0 || ''d'' ||colspan=7| ''f'' ||align=left| MOVF ''f'',''d'' || || Z ||align=left| dest ← f
|-
| 0 || 0 || 1 || 0 || 0 || 1 || ''d'' ||colspan=7| ''f'' ||align=left| COMF ''f'',''d'' || || Z ||align=left| dest ← ~f, bitwise complement
|-
| 0 || 0 || 1 || 0 || 1 || 0 || ''d'' ||colspan=7| ''f'' ||align=left| INCF ''f'',''d'' || || Z ||align=left| dest ← f+1
|-
| 0 || 0 || 1 || 0 || 1 || 1 || ''d'' ||colspan=7| ''f'' ||align=left| DECFSZ ''f'',''d'' || || ||align=left| dest ← f−1, then skip if zero
|-
| 0 || 0 || 1 || 1 || 0 || 0 || ''d'' ||colspan=7| ''f'' ||align=left| RRF ''f'',''d'' || C || ||align=left| dest ← CARRY<<7 {{pipe}} f>>1, rotate right through carry
|-
| 0 || 0 || 1 || 1 || 0 || 1 || ''d'' ||colspan=7| ''f'' ||align=left| RLF ''f'',''d'' || C || ||align=left| dest ← f<<1 {{pipe}} CARRY, rotate left through carry
|-
| 0 || 0 || 1 || 1 || 1 || 0 || ''d'' ||colspan=7| ''f'' ||align=left| SWAPF ''f'',''d'' || || ||align=left| dest ← f<<4 {{pipe}} f>>4, swap nibbles
|-
| 0 || 0 || 1 || 1 || 1 || 1 || ''d'' ||colspan=7| ''f'' ||align=left| INCFSZ ''f'',''d'' || || ||align=left| dest ← f+1, then skip if zero
|-
|colspan=18|
|-
! 0 || 1 ||colspan=2| ''opc'' ||colspan=3| ''bit'' ||colspan=7| ''register'' ||colspan=4| Bit operations
|-
| 0 || 1 || 0 || 0 ||colspan=3| ''bit'' ||colspan=7| ''f'' ||align=left| BCF ''f'',''b'' || || ||align=left| Clear bit b of f
|-
| 0 || 1 || 0 || 1 ||colspan=3| ''bit'' ||colspan=7| ''f'' ||align=left| BSF ''f'',''b'' || || ||align=left| Set bit b of f
|-
| 0 || 1 || 1 || 0 ||colspan=3| ''bit'' ||colspan=7| ''f'' ||align=left| BTFSC ''f'',''b'' || || ||align=left| Skip if bit b of f is clear
|-
| 0 || 1 || 1 || 1 ||colspan=3| ''bit'' ||colspan=7| ''f'' ||align=left| BTFSS ''f'',''b'' || || ||align=left| Skip if bit b of f is set
|-
|colspan=18|
|-
! 1 || 0 || ''c'' ||colspan=11| ''k'' ||colspan=4| Control transfers
|-
| 1 || 0 || 0 ||colspan=11| ''k'' ||align=left| CALL ''k'' || || ||align=left| Call subroutine
|-
| 1 || 0 || 1 ||colspan=11| ''k'' ||align=left| GOTO ''k'' || || ||align=left| Jump to address k
|-
|colspan=18|
|-
! 1 || 1 ||colspan=4| ''opcode'' ||colspan=8| ''8-bit immediate'' ||colspan=4| Operations with W and 8-bit literal: W ← OP(k,W)
|-
| 1 || 1 || 0 || 0 || style="background:lightgrey;"| ''x'' || style="background:lightgrey;"| ''x'' ||colspan=8| ''k'' ||align=left| MOVLW ''k'' || || ||align=left| W ← k
|-
| 1 || 1 || 0 || 1 || style="background:lightgrey;"| ''x'' || style="background:lightgrey;"| ''x'' ||colspan=8| ''k'' ||align=left| RETLW ''k'' || || ||align=left| W ← k, then return from subroutine
|-
| 1 || 1 || 1 || 0 || 0 || 0 ||colspan=8| ''k'' ||align=left| IORLW ''k'' || || Z ||align=left| W ← k {{pipe}} W, bitwise logical or
|-
| 1 || 1 || 1 || 0 || 0 || 1 ||colspan=8| ''k'' ||align=left| ANDLW ''k'' || || Z ||align=left| W ← k & W, bitwise and
|-
| 1 || 1 || 1 || 0 || 1 || 0 ||colspan=8| ''k'' ||align=left| XORLW ''k'' || || Z ||align=left| W ← k ^ W, bitwise exclusive or
|- style="background:lightgrey;"
| 1 || 1 || 1 || 0 || 1 || 1 ||colspan=8| ''k'' || style="text-align:left;" colspan="4"| ''(reserved)''
|-
| 1 || 1 || 1 || 1 || 0 || style="background:lightgrey;"| ''x'' ||colspan=8| ''k'' ||align=left| SUBLW ''k'' || C || Z ||align=left| W ← k−W (dest ← k+~W+1)
|-
| 1 || 1 || 1 || 1 || 1 || style="background:lightgrey;"| ''x'' ||colspan=8| ''k'' ||align=left| ADDLW ''k'' || C || Z ||align=left| W ← k+W
|-
|colspan=18|
|-
! 1<br/>3 || 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 || <br/>8 || <br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || C<br/>? || Z<br/>? || Description
|}

==Enhanced mid-range core devices (14 bit)==
Enhanced mid-range core devices introduce a deeper hardware stack, additional reset methods, 14 additional instructions and [[C programming language]] optimizations.<ref>{{cite web|title=Introducing the Enhanced Mid-Range Architecture|url=http://www.microchip.com/stellent/groups/SiteComm_sg/documents/DeviceDoc/en542713.pdf|website=Microchip}}</ref>  In particular. there are two <code>INDF registers</code> (<code>INDF0</code> and <code>INDF1</code>), and two corresponding <code>FSR</code> register pairs (<code>FSR''n''L</code> and <code>FSR''n''H</code>).  Special instructions use <code>FSR''n''</code> registers like address registers, with a variety of [[addressing mode]]s.
{|class="wikitable" style="text-align:center"
|+ 14-bit enhanced PIC additional instructions
! 1<br/>3 || 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 || <br/>8 || <br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || C<br/>? || Z<br/>? || Description
|-
|colspan=18|
|-
! 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=7| ''opcode'' ||colspan=4| Miscellaneous instructions
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||align=left| RESET || || ||align=left| Software reset
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 || 0 ||align=left| CALLW || || ||align=left| Push PC, then jump to PCLATH:W
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 || 1 ||align=left| BRW || || ||align=left| PC ← PC + W, relative jump using W
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || ''n'' || 0 || 0 ||align=left| MOVIW ++FSR''n'' || || Z ||align=left| Increment FSR''n'', then W ← INDF''n''
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || ''n'' || 0 || 1 ||align=left| MOVIW −−FSR''n'' || || Z ||align=left| Decrement FSR''n'', then W ← INDF''n''
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || ''n'' || 1 || 0 ||align=left| MOVIW FSR''n''++ || || Z ||align=left| W ← INDF''n'', then increment FSR''n''
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || ''n'' || 1 || 1 ||align=left| MOVIW FSR''n''−− || || Z ||align=left| W ← INDF''n'', then decrement FSR''n''
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || ''n'' ||colspan=2| ''m'' ||align=left| MOVWI using FSR''n'' || || ||align=left| INDF''n'' ← W, same modes as MOVIW
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=5| ''k'' ||align=left| MOVLB ''k'' || || ||align=left| BSR ← k, move literal to bank select register
|-
|colspan=18|
|-
! 1 || 1 ||colspan=4| ''opcode'' || ''d'' ||colspan=7| ''register'' ||colspan=4| ALU operations: dest ← OP(f,W)
|-
| 1 || 1 || 0 || 1 || 0 || 1 || ''d'' ||colspan=7| ''f'' ||align=left| LSLF ''f'',''d'' || C || Z ||align=left| dest ← ''f'' << 1, logical shift left
|-
| 1 || 1 || 0 || 1 || 1 || 0 || ''d'' ||colspan=7| ''f'' ||align=left| LSRF ''f'',''d'' || C || Z ||align=left| dest ← ''f'' >> 1, logical shift right
|-
| 1 || 1 || 0 || 1 || 1 || 1 || ''d'' ||colspan=7| ''f'' ||align=left| ASRF ''f'',''d'' || C || Z ||align=left| dest ← ''f'' >> 1, arithmetic shift right
|-
| 1 || 1 || 1 || 0 || 1 || 1 || ''d'' ||colspan=7| ''f'' ||align=left| SUBWFB ''f'',''d'' || C || Z ||align=left| dest ← ''f'' + ~W + C, subtract with carry
|-
| 1 || 1 || 1 || 1 || 0 || 1 || ''d'' ||colspan=7| ''f'' ||align=left| ADDWFC ''f'',''d'' || C || Z ||align=left| dest ← ''f'' + W + C, add with carry
|-
|colspan=18|
|-
! 1 || 1 ||colspan=5| ''opcode'' ||colspan=7| ''k'' ||colspan=4| Operations with literal ''k''
|-
| 1 || 1 || 0 || 0 || 0 || 1 || 0 || ''n'' ||colspan=6| ''k'' ||align=left| ADDFSR FSR''n'',''k'' || || ||align=left| FSR''n'' ← FSR''n'' + k, add 6-bit signed offset
|-
| 1 || 1 || 0 || 0 || 0 || 1 || 1 ||colspan=7| ''k'' ||align=left| MOVLP ''k'' || || ||align=left| PCLATH ← k, move 7-bit literal to PC latch high
|-
| 1 || 1 || 0 || 0 || 1 ||colspan=9| ''k'' ||align=left| BRA ''k'' || || ||align=left| PC ← PC + k, branch relative using 9-bit signed offset
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 0 || ''n'' ||colspan=6| ''k'' ||align=left| MOVIW ''k''[FSR''n''] || || Z ||align=left| W ← [FSR''n''+''k''], 6-bit signed offset
|-
| 1  || 1 || 1 || 1 || 1 || 1 || 1 || ''n'' ||colspan=6| ''k'' ||align=left| MOVWI ''k''[FSR''n''] || || ||align=left| [FSR''n''+''k''] ← W, 6-bit signed offset
|-
|colspan=18|
|-
! 1<br/>3 || 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 || <br/>8 || <br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || C<br/>? || Z<br/>? || Description
|}

==Holtek clones (14 or 16 bit)==
[[Holtek]] make numerous 8-bit microcontrollers with a 14-bit instruction word equivalent to the (non-enhanced) mid-range core.  The instruction encodings all fit into 14 bits and provide 7-bit operand addresses, but models with 4K or 8K words of program ROM provide 15- or 16-bit wide ROM and extend the basic 11-bit destination address using bits 14–15 of the instruction as bits 11–12 of the address. Some models extend the 7-bit RAM addresses by using bit 14 of the instruction as bit 7 of the operand address.

The instruction format is identical to Microchip's, but the opcodes are assigned in a different order, and the manufacturer uses different instruction mnemonics.  The accumulator is called ACC rather than W, and the destination is specified by a suffix to the instruction mnemonic rather than an operand.

In addition to the opcode assignment, there are semantic differences in a few instructions:
* The subtract instructions subtract the operand from the accumulator, while Microchip's subtract instructions do the reverse.  (This makes the subtract immediate instruction redundant, as it is equivalent to an add of the negative.)
* The move-to-accumulator and clear instructions do not modify any flags.

Several operations have been added to the 14-bit PICmicro repertoire:
* Rotate one bit left and right ''without'' carry,
* Set operand to all-ones,
* Skip if operand is zero (without incrementing or decrementing it first),
* Add and subtract with carry,
* Decimal adjust after addition, for [[binary-coded decimal]] arithmetic, and
* Read from program ROM, for table lookup.  This uses TBHP and TBLP registers as a 16-bit pointer, fetches the word there, and stores the low byte in a specified location.  The high 6–8 bits of the fetched word are stored in the TBLH register.  A second form uses only TBLP and reads from the highest 256-byte page in ROM.
* Most models<!--Only the HT82K69E, HT82K70A, HT82K70E and HT82M98 do not--> support a second instruction to reset the watchdog timer, which must alternate with the first; repetitions of one instruction are ignored.  This permits two independent watchdog routines to run, and failure of either will trigger the watchdog.
* Holtek provide two indirect addressing registers, like the enhanced 14-bit PIC.  Some models (e.g. HT66F70A) provide three.

{|class="wikitable" style="text-align:center"
|+ 14-bit Holtek instruction set<ref>{{cite web |title=Mouse Adventures #3: Writing a Disassembler |first=Ash "Ninji" |last=Wolf |date=12 December 2018 |access-date=8 July 2019 |url=https://wuffs.org/blog/mouse-adventures-part-3}}</ref>
! 1<br/>3 || 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 ||<br/>8 ||<br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || PIC equiv. || C<br/>? || Z<br/>? || Description
|-
|colspan=19|
|-
! 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=3| ''opcode'' ||colspan=5| Miscellaneous instructions
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||align=left| NOP ||align=left| NOP || || ||align=left| No operation (MOV A,A)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||align=left| CLR WDT1 ||align=left| CLRWDT || || ||align=left| Restart watchdog timer
|- 
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 ||align=left| HALT ||align=left| SLEEP || || ||align=left| Go into low-power  mode
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 ||align=left| RET ||align=left| RETURN || || ||align=left| Return from subroutine
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 ||align=left| RETI ||align=left| RETFIE || || ||align=left| Return from interrupt
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 ||align=left| CLR WDT2 ||bgcolor=lightgrey| — || || ||align=left| Restart watchdog timer
|-
|colspan=19|
|-
! 0 || 0 ||colspan=4| ''opcode'' || ''d'' ||colspan=7| ''address'' ||colspan=5| ALU operations: dest ← OP(ACC,[m])
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=7| ''m'' ||align=left| MOV [''m''],A ||align=left| MOVWF ''m'' || || ||align=left| [m] ← ACC
|-
| 0 || 0 || 0 || 0 || 0 || 1 || ''d'' ||colspan=7| ''m'' ||align=left| CPLA/CPL [''m''] ||align=left| COMF ''m'',''d'' || || Z ||align=left| dest ← ~[m], bitwise complement
|-
| 0 || 0 || 0 || 0 || 1 || 0 || ''d'' ||colspan=7| ''m'' ||align=left| SUB/SUBM A,[''m''] ||bgcolor=lightgrey align=left| ≠SUBWF ''m'',''d'' || C || Z ||align=left| dest ← ACC − [m] (dest ← ACC+~[m]+1)
|-
| 0 || 0 || 0 || 0 || 1 || 1 || ''d'' ||colspan=7| ''m'' ||align=left| ADD/ADDM A,[''m''] ||align=left| ADDWF ''m'',''d'' || C || Z ||align=left| dest ← ACC + [m]
|-
| 0 || 0 || 0 || 1 || 0 || 0 || ''d'' ||colspan=7| ''m'' ||align=left| XORA/XOR [''m''] ||align=left| XORWF ''m'',''d'' || || Z ||align=left| dest ← ACC ^ [m], logical exclusive or
|-
| 0 || 0 || 0 || 1 || 0 || 1 || ''d'' ||colspan=7| ''m'' ||align=left| ORA/OR [''m''] ||align=left| IORWF ''m'',''d'' || || Z ||align=left| dest ← ACC {{!}} [m], logical inclusive or
|-
| 0 || 0 || 0 || 1 || 1 || 0 || ''d'' ||colspan=7| ''m'' ||align=left| ANDA/AND [''m''] ||align=left| ANDWF ''m'',''d'' || || Z ||align=left| dest ← ACC & [m], logical and
|-
| 0 || 0 || 0 || 1 || 1 || 1 || 0 ||colspan=7| ''m'' ||align=left| MOV A,[''m''] ||bgcolor=lightgrey align=left| ≈MOVF ''m'',0 || || ||align=left| ACC ← [m]
|- style="background:lightgrey;"
| 0 || 0 || 0 || 1 || 1 || 1 || 1 ||colspan=7| ''m'' || — ||align=left| ≈MOVF ''m'',1 || || ||align=left| [m] ← [m]
|-
|colspan=19|
|-
! 0 || 0 || 1 ||colspan=3| ''opcode'' ||colspan=8| ''8-bit immediate'' ||colspan=5| Operations with 8-bit literal: ACC ← OP(ACC,k)
|- style="background:lightgrey;"
| 0 || 0 || 1 || 0 || 0 || 0 ||colspan=8| ''k'' || style="text-align:left;" colspan="5"| ''(reserved)''
|-
| 0 || 0 || 1 || 0 || 0 || 1 ||colspan=8| ''k'' ||align=left| RET A,''k'' ||align=left| RETLW ''k'' || || ||align=left| ACC ← k, then return from subroutine
|-
| 0 || 0 || 1 || 0 || 1 || 0 ||colspan=8| ''k'' ||align=left| SUB A,''k'' ||bgcolor=lightgrey align=left| ≠SUBLW ''k'' || C || Z ||align=left| ACC ← ACC − k (ACC ← ACC+~k+1) 
|-
| 0 || 0 || 1 || 0 || 1 || 1 ||colspan=8| ''k'' ||align=left| ADD A,''k'' ||align=left| ADDLW ''k'' || C || Z ||align=left| ACC ← ACC + k 
|-
| 0 || 0 || 1 || 1 || 0 || 0 ||colspan=8| ''k'' ||align=left| XOR A,''k'' ||align=left| XORLW ''k'' || || Z ||align=left| ACC ← ACC ^ k, logical exclusive or
|-
| 0 || 0 || 1 || 1 || 0 || 1 ||colspan=8| ''k'' ||align=left| OR A,''k'' ||align=left| IORLW ''k'' || || Z ||align=left| ACC ← ACC {{!}} k, logical inclusive or
|-
| 0 || 0 || 1 || 1 || 1 || 0 ||colspan=8| ''k'' ||align=left| AND A,''k'' ||align=left| ANDLW ''k'' || || Z ||align=left| ACC ← ACC & k, logical and
|-
| 0 || 0 || 1 || 1 || 1 || 1 ||colspan=8| ''k'' ||align=left| MOV A,''k'' ||align=left| MOVLW ''k'' || || ||align=left| ACC ← k
|-
|colspan=19|
|-
! 0 || 1 ||colspan=4| ''opcode'' || ''d'' ||colspan=7| ''address'' ||colspan=5| ALU operations: dest ← OP(ACC,[m])
|-
| 0 || 1 || 0 || 0 || 0 || 0 || ''d'' ||colspan=7| ''m'' ||align=left| SZA/SZ [''m''] ||bgcolor=lightgrey| — || || ||align=left| dest ← [m], skip next instruction if zero
|-
| 0 || 1 || 0 || 0 || 0 || 1 || ''d'' ||colspan=7| ''m'' ||align=left| SWAPA/SWAP [''m''] ||align=left| SWAPF ''m'',''d'' || || ||align=left| dest ← [m]<<4 {{!}} [m]>>4, swap nibbles
|-
| 0 || 1 || 0 || 0 || 1 || 0 || ''d'' ||colspan=7| ''m'' ||align=left| SBC/SBCM A,[''m''] ||bgcolor=lightgrey align=left| ≠SUBWFB ''m'',''d'' || C || Z ||align=left| dest ← ACC + ~[m] + C, subtract with carry
|-
| 0 || 1 || 0 || 0 || 1 || 1 || ''d'' ||colspan=7| ''m'' ||align=left| ADC/ADCM A,[''m''] ||align=left| ADDWFC ''m'',''d'' || C || Z ||align=left| dest ← ACC + [m] + C, add with carry
|-
| 0 || 1 || 0 || 1 || 0 || 0 || ''d'' ||colspan=7| ''m'' ||align=left| INCA/INC [''m''] ||align=left| INCF ''m'',''d'' || || Z ||align=left| dest ← [m] + 1
|-
| 0 || 1 || 0 || 1 || 0 || 1 || ''d'' ||colspan=7| ''m'' ||align=left| DECA/DEC [''m''] ||align=left| DECF ''m'',''d'' || || Z ||align=left| dest ← [m] − 1
|-
| 0 || 1 || 0 || 1 || 1 || 0 || ''d'' ||colspan=7| ''m'' ||align=left| SIZA/SIZ [''m''] ||align=left| INCFSZ ''m'',''d'' || || ||align=left| dest ← [m] + 1, then skip if zero
|-
| 0 || 1 || 0 || 1 || 1 || 1 || ''d'' ||colspan=7| ''m'' ||align=left| SDZA/SDZ [''m''] ||align=left| DECFSZ ''m'',''d'' || || ||align=left| dest ← [m] − 1, then skip if zero
|-
| 0 || 1 || 1 || 0 || 0 || 0 || ''d'' ||colspan=7| ''m'' ||align=left| RLA/RL [''m''] ||bgcolor=lightgrey| — || || ||align=left| dest ← [m] << 1 {{!}} [m] >> 7, rotate left 1 bit
|-
| 0 || 1 || 1 || 0 || 0 || 1 || ''d'' ||colspan=7| ''m'' ||align=left| RRA/RR [''m''] ||bgcolor=lightgrey| — || || ||align=left| dest ← [m] << 7 {{!}} [m] >> 1, rotate right 1 bit
|-
| 0 || 1 || 1 || 0 || 1 || 0 || ''d'' ||colspan=7| ''m'' ||align=left| RLCA/RLC [''m''] ||align=left| RLF ''m'',''d'' || C || ||align=left| dest ← [m] << 1 {{!}} C, rotate left through carry
|-
| 0 || 1 || 1 || 0 || 1 || 1 || ''d'' ||colspan=7| ''m'' ||align=left| RRCA/RRC [''m''] ||align=left| RRF ''m'',''d'' || C || ||align=left| dest ← C << 7 {{!}} [m] >> 1, rotate right through carry
|-
|colspan=19|
|-
! 0 || 1 || 1 || 1 ||colspan=3| ''opcode'' ||colspan=7| ''address'' ||colspan=5| Special operations: [m] ← special
|- style="background:lightgrey;"
| 0 || 1 || 1 || 1 || 0 || 0 || ''x'' ||colspan=7| ''m'' || style="text-align:left;" colspan="5"| ''(reserved)''
|-
| 0 || 1 || 1 || 1 || 0 || 1 || 0 ||colspan=7| ''m'' ||align=left| TABRDC [''m''] ||bgcolor=lightgrey| — || || ||align=left| TBLH:[m] ← ROM memory at TBHP:TBLP, table lookup
|-
| 0 || 1 || 1 || 1 || 0 || 1 || 1 ||colspan=7| ''m'' ||align=left| TABRDL [''m''] ||bgcolor=lightgrey| — || || ||align=left| 
Read from last page of ROM at 0xff:TBLP
|- style="background:lightgrey;"
| 0 || 1 || 1 || 1 || 1 || 0 || 0 ||colspan=7| ''m'' || style="text-align:left;" colspan="5"| ''(reserved)''
|-
| 0 || 1 || 1 || 1 || 1 || 0 || 1 ||colspan=7| ''m'' ||align=left| DAA [''m''] ||bgcolor=lightgrey| — || C || ||align=left| [m] ← DAA(ACC), decimal adjust after BCD addition 
|-
| 0 || 1 || 1 || 1 || 1 || 1 || 0 ||colspan=7| ''m'' ||align=left| CLR [''m''] ||bgcolor=lightgrey align=left| ≈CLRF ''m'' || || ||align=left| [m] ← 0
|-
| 0 || 1 || 1 || 1 || 1 || 1 || 1 ||colspan=7| ''m'' ||align=left| SET [''m''] ||bgcolor=lightgrey| — || || ||align=left| [m] ← 255
|-
|colspan=19|
|-
! 1 || 0 || ''c'' ||colspan=11| ''k'' ||colspan=5| Control transfers
|-
| 1 || 0 || 0 ||colspan=11| ''k'' ||align=left| CALL ''k'' ||align=left| CALL ''k'' || || ||align=left| Call subroutine
|-
| 1 || 0 || 1 ||colspan=11| ''k'' ||align=left| JMP ''k'' ||align=left| GOTO ''k'' || || ||align=left| Jump to address k
|-
|colspan=19|
|-
! 1 || 1 ||colspan=2| ''opc'' ||colspan=3| ''bit'' ||colspan=7| ''address'' ||colspan=5| Bit operations
|-
| 1 || 1 || 0 || 0 ||colspan=3| ''bit'' ||colspan=7| ''m'' ||align=left| SET [''m''].''b'' ||align=left| BSF ''m'',''b'' || || ||align=left| Set bit b of [m]
|-
| 1 || 1 || 0 || 1 ||colspan=3| ''bit'' ||colspan=7| ''m'' ||align=left| CLR [''m''].''b'' ||align=left| BCF ''m'',''b'' || || ||align=left| Clear bit b of [m]
|-
| 1 || 1 || 1 || 0 ||colspan=3| ''bit'' ||colspan=7| ''m'' ||align=left| SNZ [''m''].''b'' ||align=left| BTFSS ''m'',''b'' || || ||align=left| Skip if bit b of [m] is set
|-
| 1 || 1 || 1 || 1 ||colspan=3| ''bit'' ||colspan=7| ''m'' ||align=left| SZ [''m''].''b'' ||align=left| BTFSC ''m'',''b'' || || ||align=left| Skip if bit b of [m] is clear
|-
|colspan=19|
|-
! 1<br/>3 || 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 || <br/>8 || <br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || PIC equiv. || C<br/>? || Z<br/>? || Description
|}
<!--
Not yet documented:
* TABRDL instruction (table read last page) uses all-ones rather than TBHP
* ITABRD and ITABRDL, which add a pre-increent of TBLP
* Long instructions as described in https://www.holtek.com/documents/10179/116745/an0334e.pdf
-->

==Padauk microcontrollers (13, 14, 15 or 16 bit)==
[[Padauk Technology]] make a series of PIC-like microcontrollers notable for their extremely low cost, beginning at {{USD|0.033}} in quantity,<ref>{{cite web
 |title=What's up with these 3-cent microcontrollers? (A review of the Padauk PMS150C and friends)
 |first=Jay |last=Carlson
 |url=https://jaycarlson.net/2019/09/06/whats-up-with-these-3-cent-microcontrollers/
 |date=6 September 2019 |access-date=2020-05-18
}}</ref> with many models costing less than {{USD|0.10}}.<ref name="tim" >{{cite web
 |title=The "terrible" 3 cent MCU – a short survey of sub $0.10 microcontrollers.
 |website=Tim's blog
 |url=https://cpldcpu.word-press.com/2019/08/12/the-terrible-3-cent-mcu/
 |date=12 August 2019 |access-date=2020-05-18
}}</ref><ref>
{{cite web
 |title= Free PDK Documentation
 |url=https://free-pdk.github.io/
 |quote=Padauk µCs sport an interesting architecture that can be a seen as a ... extension of the Microchip PIC architecture.
}}
</ref><ref>
{{cite web
 |title= Chiptunes on an ATtiny4 and the 3 Cent Micro: Porting to Padauk
 |url=https://gir.st/chiptunes.html
 |quote=According to some, Padauk's instruction set is heavily inspired by older PICs, with most operations taking place on a single accumulator register.
}}</ref>

Although clearly derived from the Microchip PIC12 series,<ref name="tim" /><ref>
Jenny List
[https://hackaday.com/2019/08/28/everything-you-want-to-know-about-the-cheapest-processors-available/ "Everything you want to know about the cheapest processors available"].
2019.
</ref>
there are some significant differences:
* They do not use the FSR/INDF mechanism for performing indirect memory access, instead having indirect load and store instructions which use an arbitrary RAM location as a pointer;
* they use a RAM-based call stack, with a stack pointer register;
* the [[carry flag]] uses a "borrow bit" convention for subtracts, rather than the "carry bit" convention used by Microchip;
* they also include a signed [[overflow flag]], which like the digit carry, is set by add, subtract and compare instructions (every instruction which sets the carry flag ''except'' for shift instructions);
* they have separate RAM and I/O register addresses spaces (64 and 32 bytes, respectively, in the 13-bit instruction set);
* bit operations are limited to the I/O space and first 16 RAM addresses;
* the single-operand instructions with a memory source and accumulator destination are omitted;
* single-operand instructions with accumulator source and destination are provided;
* subtraction operations compute destination − source, exchanging input operands depending on the destination;
* they operate faster, requiring 1 cycle for most instructions and 2 cycles for control transfers; and
* some models support [[temporal multithreading]], having multiple execution contexts whose execution is interleaved.

{|class="wikitable" style="text-align:center"
|+ 13-bit Padauk instruction set<ref>{{cite web |title=Documentation for PADAUK FPPA MCUs |first=Ash "Ninji" |last=Wolf |website=[[GitHub]] |date=12 December 2018 |access-date=2020-05-18 |url=https://github.com/free-pdk/fppa-pdk-documentation}}</ref><ref>{{cite web |url=http://www.padauk.com.tw/upload/doc/PMC150,%20PMS150%20datasheet%20V108_EN_20181211.pdf#page=38 |title=PMC150/PMS150 8-bit OTP Type IO Controller |type=data sheet |version=Version 1.8 |date=11 December 2018 |pages=38–51 |access-date=2020-06-08 |author=Padauk Technology Co. Ltd. |id=PDK-DS-PMX150-EN-V108}}</ref>
! 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 ||<br/>8 ||<br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || PIC<br/>equivalent || C<br/>? || Z<br/>? || Description
|-
|colspan=18|
|-
! 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=4| ''opcode'' ||colspan=5| Miscellaneous instructions
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||align=left| NOP ||align=left| NOP || || ||align=left| No operation
|-bgcolor=lightgrey
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=5 align=left| ''(reserved)''
|-bgcolor=lightgrey
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || ''x'' ||colspan=5 align=left| ''(reserved)''
|-bgcolor=lightgrey
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || ''x'' ||colspan=5 align=left| ''(reserved)''
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 ||align=left| LDSPTL ||bgcolor=lightgrey| — || || ||align=left rowspan=2| A ← ROM[<nowiki/>[SP]], load low/high byte of ROM word using 16-bit pointer on top of stack
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 ||align=left| LDSPTH ||bgcolor=lightgrey| — || || 
|-bgcolor=lightgrey
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=3| — ||colspan=5 align=left| ''(reserved)''
|-
|colspan=18|
|-
! 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=4| ''opcode'' ||colspan=5| One-operand instructions on accumulator<br>Same as one-operand instructions on memory (below) except
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 || 1 || 1 ||align=left| PCADD A ||bgcolor=lightgrey align=left| ≈ADDWF PCL,1 || || ||align=left| PC ← PC + A, add to program counter (not {{s|XCH A}})
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || 1 || 0 ||align=left| SWAP A ||bgcolor=lightgrey| — || || ||align=left| A ← A<<4 | A>>4, swap nibbles (not {{s|CEQSN A}})
|-
|colspan=18|
|-bgcolor=lightgrey
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 ||colspan=4| — ||colspan=5 align=left| ''(reserved)''
|-
! 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 ||colspan=4| ''opcode'' ||colspan=5| System control instructions
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 0 || 0 ||align=left| WDRESET ||align=left| CLRWDT || || ||align=left| Restart watchdog timer
|-bgcolor=lightgrey
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 0 || 1 ||colspan=5 align=left| ''(reserved)''
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 1 || 0 ||align=left| PUSHAF ||bgcolor=lightgrey| — || || ||align=left| Push A then flags on top of stack
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 1 || 1 ||align=left| POPAF ||bgcolor=lightgrey| — || C || Z ||align=left| Pop flags then A from top of stack
|-bgcolor=lightgrey
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || 1 || 0 || 0 ||colspan=5 align=left| ''(reserved)''
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || 1 || 0 || 1 ||align=left| RESET ||align=left| RESET || || ||align=left| Software reset
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || 1 || 1 || 0 ||align=left| STOPSYS ||align=left| SLEEP || || ||align=left| Go into standby mode (clock stopped)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || 1 || 1 || 1 ||align=left| STOPEXE ||bgcolor=lightgrey| —  || || ||align=left| Go into standby mode (clock running)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || 0 || 0 || 0 ||align=left| ENGINT ||align=left| BSF&nbsp;INTCON,GIE || || ||align=left| Enable interrupts
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || 0 || 0 || 1 ||align=left| DISGINT ||align=left| BCF&nbsp;INTCON,GIE || || ||align=left| Disable interrupts
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || 0 || 1 || 0 ||align=left| RET ||align=left| RETURN || || ||align=left| Return from subroutine, A unmodified
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || 0 || 1 || 1 ||align=left| RETI ||align=left| RETFIE || || ||align=left| Return from interrupt
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || 1 || 0 || 0 ||align=left| MUL ||bgcolor=lightgrey| — || || ||align=left| MULRH:A ← A × MULOP (not all models)
|-bgcolor=lightgrey
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || 1 || 0 || 1 ||colspan=5 align=left| ''(reserved)''
|-bgcolor=lightgrey
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || 1 || 1 || ''x'' ||colspan=5 align=left| ''(reserved)''
|-
|colspan=18|
|-
! 0 || 0 || 0 || 0 || 0 ||colspan=3| ''opcode'' ||colspan=5| ''ioaddr'' ||colspan=5| Byte-wide I/O operations
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 ||colspan=5| ''ioaddr'' ||align=left| XOR ''ioaddr'',A ||bgcolor=lightgrey| — || || ||align=left| IO[ioaddr] ← A ^ IO[address]
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 ||colspan=5| ''ioaddr'' ||align=left| MOV ''ioaddr'',A ||bgcolor=lightgrey| — || || ||align=left| IO[ioaddr] ← A
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 ||colspan=5| ''ioaddr'' ||align=left| MOV A,''ioaddr'' ||bgcolor=lightgrey| — || || Z ||align=left| A ← IO[ioaddr]
|-
|colspan=18|
|-
! 0 || 0 || 0 || 0 || 0 || 1 || 1 || ''c'' ||colspan=4| ''address'' || ''c'' ||colspan=5| 16-bit operations (RAM address limited, even)
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 ||colspan=4| ''address'' || 0 ||align=left| STT16 ''addr'' ||bgcolor=lightgrey| — || || ||align=left| Timer16 ← [address]
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 ||colspan=4| ''address'' || 1 ||align=left| LDT16 ''addr'' ||bgcolor=lightgrey| — || || ||align=left| [address] ← Timer16
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 ||colspan=4| ''address'' || 0 ||align=left| IDXM ''addr'',A ||bgcolor=lightgrey| — || || ||align=left| [<nowiki/>[address]] ← A, indirect memory address 
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 ||colspan=4| ''address'' || 1 ||align=left| IDXM A,''addr'' ||bgcolor=lightgrey| — || || ||align=left| A ← [<nowiki/>[address]], indirect memory address
|-
|colspan=18|
|-
! 0 || 0 || 0 || 0 || 1 ||colspan=8| ''k'' ||colspan=5| Return literal constant
|-
| 0 || 0 || 0 || 0 || 1 ||colspan=8| ''k'' ||align=left| RET ''k'' ||align=left| RETLW ''k'' || || ||align=left| A ← ''k'', then return from subroutine
|-
|colspan=18|
|-
! 0 || 0 || 0 || 1 || ''c'' ||colspan=3| ''bit'' || ''c'' ||colspan=4| ''address'' ||colspan=5| Bit operations with RAM (first 16 bytes only)
|-
| 0 || 0 || 0 || 1 || 0 ||colspan=3| ''bit'' || 0 ||colspan=4| ''address'' ||align=left| T0SN ''addr''.''b'' ||align=left| BTFSC ''addr'',''b'' || || ||align=left| Skip if bit ''b'' of [''addr''] is clear
|-
| 0 || 0 || 0 || 1 || 0 ||colspan=3| ''bit'' || 1 ||colspan=4| ''address'' ||align=left| T1SN ''addr''.''b'' ||align=left| BTFSS ''addr'',''b'' || || ||align=left| Skip if bit ''b'' of [''addr''] is set
|-
| 0 || 0 || 0 || 1 || 1 ||colspan=3| ''bit'' || 0 ||colspan=4| ''address'' ||align=left| SET0 ''addr''.''b'' ||align=left| BCF ''addr'',''b'' || || ||align=left| Clear bit ''b'' of [''addr'']
|-
| 0 || 0 || 0 || 1 || 1 ||colspan=3| ''bit'' || 1 ||colspan=4| ''address'' ||align=left| SET1 ''addr''.''b'' ||align=left| BSF ''addr'',''b'' || || ||align=left| Set bit ''b'' of [''addr'']
|-
|colspan=18|
|-
! 0 || 0 || 1 || ''d'' ||colspan=3| ''opcode'' ||colspan=6| ''address'' ||colspan=5| ALU operations between A and memory
|-
| 0 || 0 || 1 || 0 || 0 || 0 || 0 ||colspan=6| ''address'' ||align=left| ADD ''addr'',A ||align=left| ADDWF ''addr'',1 || C || Z ||align=left| [''addr''] ← [''addr''] + A
|-
| 0 || 0 || 1 || 0 || 0 || 0 || 1 ||colspan=6| ''address'' ||align=left| SUB ''addr'',A ||align=left| SUBWF ''addr'',1 || C || Z ||align=left| [''addr''] ← [''addr''] − A
|-
| 0 || 0 || 1 || 0 || 0 || 1 || 0 ||colspan=6| ''address'' ||align=left| ADDC&nbsp;''addr'',A ||aligh=left| ADDWFC ''addr'',1 || C || Z ||align=left| [''addr''] ← [''addr''] + A + C
|-
| 0 || 0 || 1 || 0 || 0 || 1 || 1 ||colspan=6| ''address'' ||align=left| SUBC&nbsp;''addr'',A ||bgcolor=lightgrey align=left| ≈SUBWFB&nbsp;''addr'',1 || C || Z ||align=left| [''addr''] ← [''addr''] − A − C
|-
| 0 || 0 || 1 || 0 || 1 || 0 || 0 ||colspan=6| ''address'' ||align=left| AND ''addr'',A ||align=left| ANDWF ''addr'',1 || || Z ||align=left| [''addr''] ← [''addr''] & A, logical and
|-
| 0 || 0 || 1 || 0 || 1 || 0 || 1 ||colspan=6| ''address'' ||align=left| OR ''addr'',A ||align=left| IORWF ''addr'',1 || || Z ||align=left| [''addr''] ← [''addr''] {{!}} A, logical inclusive or
|-
| 0 || 0 || 1 || 0 || 1 || 1 || 0 ||colspan=6| ''address'' ||align=left| XOR ''addr'',A ||align=left| XORWF ''addr'',1 || || Z ||align=left| [''addr''] ← [''addr''] ^ A, logical exclusive or
|-
| 0 || 0 || 1 || 0 || 1 || 1 || 1 ||colspan=6| ''address'' ||align=left| MOV ''addr'',A ||align=left| MOVWF ''addr'' || || ||align=left| [''addr''] ← A
|-
| 0 || 0 || 1 || 1 || 0 || 0 || 0 ||colspan=6| ''address'' ||align=left| ADD A,''addr'' ||align=left| ADDWF ''addr'',0 || C || Z ||align=left| A ← A + [''addr'']
|-
| 0 || 0 || 1 || 1 || 0 || 0 || 1 ||colspan=6| ''address'' ||align=left| SUB A,''addr'' ||bgcolor=lightgrey align=left| ≠SUBWF ''addr'',0 || C || Z ||align=left| A ← A − [''addr'']
|-
| 0 || 0 || 1 || 1 || 0 || 1 || 0 ||colspan=6| ''address'' ||align=left| ADDC&nbsp;A,''addr'' ||aligh=left| ADDWFC ''addr'',0 || C || Z ||align=left| A ← A + [''addr''] + C
|-
| 0 || 0 || 1 || 1 || 0 || 1 || 1 ||colspan=6| ''address'' ||align=left| SUBC&nbsp;A,''addr'' ||bgcolor=lightgrey align=left| ≠SUBWFB&nbsp;''addr'',0 || C || Z ||align=left| A ← A − [''addr''] − C
|-
| 0 || 0 || 1 || 1 || 1 || 0 || 0 ||colspan=6| ''address'' ||align=left| AND A,''addr'' ||align=left| ANDWF ''addr'',0 || || Z ||align=left| A ← [A] & [''addr''], logical and
|-
| 0 || 0 || 1 || 1 || 1 || 0 || 1 ||colspan=6| ''address'' ||align=left| OR A,''addr'' ||align=left| IORWF ''addr'',0 || || Z ||align=left| A ← A {{!}} [''addr''], logical inclusive or
|-
| 0 || 0 || 1 || 1 || 1 || 1 || 0 ||colspan=6| ''address'' ||align=left| XOR A,''addr'' ||align=left| XORWF ''addr'',0 || || Z ||align=left| A ← A ^ [''addr''], logical exclusive or
|-
| 0 || 0 || 1 || 1 || 1 || 1 || 1 ||colspan=6| ''address'' ||align=left| MOV A,''addr'' ||align=left| MOVF ''addr'',0 || || Z ||align=left| A ← [''addr'']
|-
|colspan=18|
|-
! 0 || 1 || 0 ||colspan=4| ''opcode'' ||colspan=6| ''address'' ||colspan=5| One-operand operations on memory
|-
| 0 || 1 || 0 || 0 || 0 || 0 || 0 ||colspan=6| ''address'' ||align=left| ADDC ''addr'' ||bgcolor=lightgrey| — || C || Z ||align=left| [''addr''] ← [''addr''] + C
|-
| 0 || 1 || 0 || 0 || 0 || 0 || 1 ||colspan=6| ''address'' ||align=left| SUBC ''addr'' ||bgcolor=lightgrey| — || C || Z ||align=left| [''addr''] ← [''addr''] − C
|-
| 0 || 1 || 0 || 0 || 0 || 1 || 0 ||colspan=6| ''address'' ||align=left| IZSN ''addr'' ||align=left| INCFSZ ''addr'',1 || C || Z ||align=left| [''addr''] ← [''addr''] + 1, then skip if zero
|-
| 0 || 1 || 0 || 0 || 0 || 1 || 1 ||colspan=6| ''address'' ||align=left| DZSN ''addr'' ||align=left| DECFSZ ''addr'',1 || C || Z ||align=left| [''addr''] ← [''addr''] − 1, then skip if zero
|-
| 0 || 1 || 0 || 0 || 1 || 0 || 0 ||colspan=6| ''address'' ||align=left| INC ''addr'' ||align=left| INCF ''addr'',1 || C || Z ||align=left| [''addr''] ← [''addr''] + 1
|-
| 0 || 1 || 0 || 0 || 1 || 0 || 1 ||colspan=6| ''address'' ||align=left| DEC ''addr'' ||align=left| DECF ''addr'',1 || C || Z ||align=left| [''addr''] ← [''addr''] − 1
|-
| 0 || 1 || 0 || 0 || 1 || 1 || 0 ||colspan=6| ''address'' ||align=left| CLEAR ''addr'' ||bgcolor=lightgrey align=left| ≈CLRF ''addr'' || || ||align=left| [''addr''] ← 0
|-
| 0 || 1 || 0 || 0 || 1 || 1 || 1 ||colspan=6| ''address'' ||align=left| XCH ''addr'' ||bgcolor=lightgrey| — || || ||align=left| A ← [''addr''], [''addr''] ← A
|-
| 0 || 1 || 0 || 1 || 0 || 0 || 0 ||colspan=6| ''address'' ||align=left| NOT ''addr'' ||align=left| COMF ''addr'',1 || || Z ||align=left| [''addr''] ← ~[''addr''], bitwise complement
|-
| 0 || 1 || 0 || 1 || 0 || 0 || 1 ||colspan=6| ''address'' ||align=left| NEG ''addr'' ||bgcolor=lightgrey| — || || Z ||align=left| [''addr''] ← −[''addr''], negate
|-
| 0 || 1 || 0 || 1 || 0 || 1 || 0 ||colspan=6| ''address'' ||align=left| SR ''addr'' ||bgcolor=lightgrey align=left| ≈LSRF ''addr'',1 || C || ||align=left| [''addr''] ← [''addr''] >> 1, logical shift right
|-
| 0 || 1 || 0 || 1 || 0 || 1 || 1 ||colspan=6| ''address'' ||align=left| SL ''addr'' ||bgcolor=lightgrey align=left| ≈LSLF ''addr'',1 || C || ||align=left| [''addr''] ← [''addr''] << 1, shift left
|-
| 0 || 1 || 0 || 1 || 1 || 0 || 0 ||colspan=6| ''address'' ||align=left| SRC ''addr'' ||align=left| RRF ''addr'',1 || C || ||align=left| [''addr''] ← C << 7 {{!}} [''addr''] >> 1, rotate right through carry
|-
| 0 || 1 || 0 || 1 || 1 || 0 || 1 ||colspan=6| ''address'' ||align=left| SLC ''addr'' ||align=left| RLF ''addr'',1 || C || ||align=left| [''addr''] ← [''addr''] << 1 {{!}} C, rotate left through carry
|-
| 0 || 1 || 0 || 1 || 1 || 1 || 0 ||colspan=6| ''address'' ||align=left| CEQSN ''addr'' ||bgcolor=lightgrey| — || C || Z ||align=left| Compute A − [''addr''], then skip if zero
|-bgcolor=lightgrey
| 0 || 1 || 0 || 1 || 1 || 1 || 1 ||colspan=6| ''address'' ||align=left colspan=5| ''(reserved for CNEQSN)''
|-
|colspan=18|
|-
! 0 || 1 || 1 ||colspan=2| ''opc'' ||colspan=3| ''bit'' ||colspan=5| ''address'' ||colspan=5| Bit operations with I/O
|-
| 0 || 1 || 1 || 0 || 0 ||colspan=3| ''bit'' ||colspan=5| ''address'' ||align=left| T0SN&nbsp;''ioaddr''.''b'' ||align=left| BTFSC ''ioaddr'',''b'' || || ||align=left| Skip if bit ''b'' of [''ioaddr''] is clear
|-
| 0 || 1 || 1 || 0 || 1 ||colspan=3| ''bit'' ||colspan=5| ''address'' ||align=left| T1SN&nbsp;''ioaddr''.''b'' ||align=left| BTFSS ''ioaddr'',''b'' || || ||align=left| Skip if bit ''b'' of [''ioaddr''] is set
|-
| 0 || 1 || 1 || 1 || 0 ||colspan=3| ''bit'' ||colspan=5| ''address'' ||align=left| SET0 ''ioaddr''.''b'' ||align=left| BCF ''ioaddr'',''b'' || || ||align=left| Clear bit ''b'' of [''ioaddr'']
|-
| 0 || 1 || 1 || 1 || 1 ||colspan=3| ''bit'' ||colspan=5| ''address'' ||align=left| SET1 ''ioaddr''.''b'' ||align=left| BSF ''ioaddr'',''b'' || || ||align=left| Set bit ''b'' of [''ioaddr'']
|-
|colspan=18|
|-
! 1 || 0 ||colspan=3| ''opcode'' ||colspan=8| ''literal'' ||colspan=5| Literal operations: A ← OP(A,''k'')
|-
| 1 || 0 || 0 || 0 || 0 ||colspan=8| ''k'' ||align=left| ADD A,''k'' ||align=left| ADDLW ''k'' || C || Z ||align=left| A ← A + ''k''
|-
| 1 || 0 || 0 || 0 || 1 ||colspan=8| ''k'' ||align=left| SUB A,''k'' ||bgcolor=lightgrey align=left| ≠SUBLW ''k'' || C || Z ||align=left| A ← A − ''k''
|-
| 1 || 0 || 0 || 1 || 0 ||colspan=8| ''k'' ||align=left| CEQSN A,''k'' ||bgcolor=lightgrey| —  || C || Z ||align=left| Compute A − ''k'', then skip if zero
|-bgcolor=lightgrey
| 1 || 0 || 0 || 1 || 1 ||colspan=8| ''k'' ||align=left colspan=5| ''(reserved for CNEQSN)''
|-
| 1 || 0 || 1 || 0 || 0 ||colspan=8| ''k'' ||align=left| AND A,''k'' ||bgcolor=lightgrey align=left| ≈ANDLW ''k'' || || Z ||align=left| A ← A & k
|-
| 1 || 0 || 1 || 0 || 1 ||colspan=8| ''k'' ||align=left| OR A,''k'' ||bgcolor=lightgrey align=left| ≈IORLW ''k'' || || Z ||align=left| A ← A {{!}} k
|-
| 1 || 0 || 1 || 1 || 0 ||colspan=8| ''k'' ||align=left| XOR A,''k'' ||bgcolor=lightgrey align=left| ≈XORLW ''k'' || || Z ||align=left| A ← A ^ k
|-
| 1 || 0 || 1 || 1 || 1 ||colspan=8| ''k'' ||align=left| MOV A,''k'' ||align=left| MOVLW ''k'' || || ||align=left| A ← k
|-
|colspan=18|
|-
! 1 || 1 || ''c'' ||colspan=10| ''k'' ||colspan=5| Control transfers: PC ← ''k''
|-
| 1 || 1 || 0 ||colspan=10| ''k'' ||align=left| GOTO ''k'' ||align=left| GOTO ''k'' || || ||align=left| PC ← ''k''
|-
| 1 || 1 || 1 ||colspan=10| ''k'' ||align=left| CALL ''k'' ||align=left| CALL ''k'' || || ||align=left| Push PC, then PC ← ''k''
|-
|colspan=18|
|-
! 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 ||<br/>8 ||<br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || PIC<br/>equivalent || C<br/>? || Z<br/>? || Description
|}

The 14-, 15- and 16-bit instruction sets primarily differ in having wider address fields, although some encoding changes are made to allow a few additional instructions (such as {{code|CNEQSN}}, which performs a compare and skip if ''not'' equal.)

{|class="wikitable" style="text-align:center"
|+ 14-bit Padauk instruction set<ref>{{cite web |title=PADAUK FPPA core devices (14 bit) instruction set |first=Ash "Ninji" |last=Wolf |date=23 May 2020 |access-date=2020-06-08 |url=https://free-pdk.github.io/PADAUK_FPPA_14_bit_instruction_set.html}}</ref><ref>{{cite web |url=http://www.padauk.com.tw/upload/doc/PFS154%20datasheet_v104_EN_20190618.pdf#page=71 |title=PFS154 8bit MTP Type IO controller Data Sheet |version=Version 1.04 |date=18 June 2019 |pages=71–84 |access-date=2020-06-09 |author=Padauk Technology Co. Ltd. |id=PDK-DS-PFS154_RN_V104}}</ref>
! 1<br/>3 || 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 ||<br/>8 ||<br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || PIC<br/>equivalent || C<br/>? || Z<br/>? || Description
|-
|colspan=19|
|-
! 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=4| ''opcode'' ||colspan=5| Miscellaneous instructions same as 13-bit
|-bgcolor=lightgrey
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=4| — ||colspan=5 align=left| ''(reserved)''
|-bgcolor=lightgrey
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=5| — ||colspan=5 align=left| ''(reserved)''
|-bgcolor=lightgrey
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 ||colspan=5| — ||colspan=5 align=left| ''(reserved)''
|-
! 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 ||colspan=4| ''opcode'' ||colspan=5| One-operand instructions on A same as 13-bit
|-
! 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 ||colspan=4| ''opcode'' ||colspan=5| System control instructions same as 13-bit
|-bgcolor=lightgrey
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 ||colspan=6| — ||colspan=5 align=left| ''(reserved)''
|-
|colspan=18|
|-
! 0 || 0 || 0 || 0 || 0 ||colspan=3| ''opcode'' ||colspan=6| ''address'' ||colspan=5| Byte-wide I/O operations same as 13-bit, but opcodes changed
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 ||colspan=6| ''ioaddr'' ||align=left| XOR ''ioaddr'',A ||bgcolor=lightgrey| — || || ||align=left| IO[ioaddr] ← A ^ IO[address]
|-bgcolor=lightgrey
| 0 || 0 || 0 || 0 || 0 || 1 || 0 ||colspan=7| — ||colspan=5 align=left| ''(reserved)''
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 ||colspan=6| ''ioaddr'' ||align=left| MOV ''ioaddr'',A ||bgcolor=lightgrey| — || || ||align=left| IO[ioaddr] ← A
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 ||colspan=6| ''ioaddr'' ||align=left| MOV A,''ioaddr'' ||bgcolor=lightgrey| — || || Z ||align=left| A ← IO[ioaddr]
|-
|colspan=19|
|-
! 0 || 0 || 0 || 0 || 1 || 0 ||colspan=8| ''k'' ||colspan=5| Return literal constant same as 13-bit
|-
! 0 || 0 || 0 || 0 || 1 || 1 || ''c'' ||colspan=6| ''address'' || ''c'' ||colspan=5| 16-bit operations same as 13-bit, but 128-byte range
|-
|colspan=19|
|-
! 0 || 0 || 0 || 1 || 0 ||colspan=3| ''bit'' ||colspan=6| ''address'' ||colspan=5| Copy bit to I/O
|-
| 0 || 0 || 0 || 1 || 0 ||colspan=3| ''bit'' ||colspan=6| ''address'' ||align=left| SWAPC&nbsp;''ioaddr''.''b'' ||bgcolor=lightgrey| — || C || ||align=left| Swap carry with [''ioaddr''] bit ''b''
|-
|colspan=19|
|-
! 0 || 0 || 0 || 1 || 1 || ''c'' || ''d'' ||colspan=7| ''address'' ||colspan=5| Additional 2-operand operations
|-
| 0 || 0 || 0 || 1 || 1 || 0 || 0 ||colspan=7| ''address'' ||align=left| COMP A,''addr'' ||bgcolor=lightgrey| —  || C || Z ||align=left| A − [''addr''], flags set, result discarded
|-
| 0 || 0 || 0 || 1 || 1 || 0 || 1 ||colspan=7| ''address'' ||align=left| COMP ''addr'',A ||bgcolor=lightgrey| —  || C || Z ||align=left| [''addr''] − A, flags set, result discarded
|-
| 0 || 0 || 0 || 1 || 1 || 1 || 0 ||colspan=7| ''address'' ||align=left| NADD A,''addr'' ||align=left| SUBWF&nbsp;''addr'',0  || C || Z ||align=left|  A ← [''addr''] + −A (A ← [''addr''] + ~A + 1)
|-
| 0 || 0 || 0 || 1 || 1 || 1 || 1 ||colspan=7| ''address'' ||align=left| NADD ''addr'',A ||bgcolor=lightgrey| —  || C || Z ||align=left|  [''addr''] ← A + −[''addr''] ([''addr''] ← A + ~[''addr''] + 1)
|-
|colspan=19|
|-
! 0 || 0 || 1 || ''d'' ||colspan=3| ''opcode'' ||colspan=7| ''address'' ||colspan=5| 2-operand instructions same as 13-bit
|-
|colspan=19|
|-
! 0 || 1 || 0 ||colspan=4| ''opcode'' ||colspan=7| ''address'' ||colspan=5| One-operand operations on memory same as 13-bit, plus CNEQSN
|-
| 0 || 1 || 0 || 1 || 1 || 1 || 1 ||colspan=7| ''address'' ||align=left| CNEQSN ''addr'' ||bgcolor=lightgrey| — || C || Z ||align=left| Compute A − [''addr''], then skip if non-zero
|-
|colspan=19|
|-
! 0 || 1 || 1 ||colspan=2| ''opc'' ||colspan=3| ''bit'' ||colspan=6| ''ioaddr'' ||colspan=5| Bit operations with I/O same as 13-bit, but 64-byte range
|-
! 1 || 0 || 0 ||colspan=2| ''opc'' ||colspan=3| ''bit'' ||colspan=6| ''address'' ||colspan=5| Bit operations with memory same as 13-bit,  but 64-byte range
|-
|colspan=19|
|-
! 1 || 0 || 1 ||colspan=3| ''opcode'' ||colspan=8| ''literal'' ||colspan=5| Literal operations same as 13-bit, plus CNEQSN
|-
| 1 || 0 || 1 || 0 || 1 || 1 ||colspan=8| ''k'' ||align=left| CNEQSN A,''k'' ||bgcolor=lightgrey| — || C || Z ||align=left| Compute A − ''k'', then skip if non-zero
|-
|colspan=19|
|-
! 1 || 1 || ''c'' ||colspan=11| ''k'' ||colspan=5| Control transfers same as 13-bit
|-
|colspan=19|
|-
! 1<br/>13 || 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 ||<br/>8 ||<br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || PIC<br/>equivalent || C<br/>? || Z<br/>? || Description
|}

==PIC18 high end core devices (16 bit)==
In 2000, Microchip introduced the PIC18 architecture.[http://mdubuc.freeshell.org/Sdcc/] Unlike the 17 series, it has proven to be very popular, with a large number of device variants presently in manufacture. In contrast to earlier devices, which were more often than not programmed in assembly, C has become the predominant development language.<ref>{{Cite web|url=http://www.microchipc.com/sourcecode/|title = Microchip PIC micros and C - source and sample code}}</ref>

The PIC18 has a 12-bit RAM address space, divided into 16 pages of 256 bytes.  The 8-bit <code>f</code> field determines the address in combination with the <code>a</code> bit and the 4-bit bank select register (<code>BSR</code>).  If <code>a</code>=0, the <code>BSR</code> is ignored and the <code>f</code> field is sign-extended to the range 0x000&ndash;0x07F (global RAM) or 0xF80&ndash;0xFFF (special function registers).  If <code>a</code>=1, the <code>f</code> field is extended with the <code>BSR</code> to generate the 12-bit address.

The PIC18 extends the <code>FSR</code>/<code>INDF</code> mechanism used in previous PICmicro processors for indirect addressing in two ways:

First, it provides ''three''  file select registers.  The <code>FSR''n''</code> registers are 12 bits long (each split into two 8-bit portions <code>FSR0L</code> through <code>FSR2H</code>), and access to the corresponding <code>INDF''n''</code> register (<code>INDF0</code> through <code>INDF2</code>) acts as an alias for the addressed byte.

Second, there are addressing modes.  For each of the three, there is not just one <code>INDF''n''</code> register, but five, and the one used determines the addressing mode:
* <code>INDF''n''</code>: Access the byte at location <code>FSR''n''</code>
* <code>POSTDEC''n''</code>: Access the byte at <code>FSR''n''</code>, then decrement <code>FSR''n''</code>
* <code>POSTINC''n''</code>: Access the byte at <code>FSR''n''</code>, then increment <code>FSR''n''</code>
* <code>PREINC''n''</code>: Increment <code>FSR''n''</code>, then access the byte at the incremented <code>FSR''n''</code>
* <code>PLUSW''n''</code>: Access the byte at <code>FSR''n'' + W</code> (indexed addressing).

There are also instructions to directly load an FSR pair with a 12-bit address, and a <code>MOVFF</code> instruction that moves a byte between two 12-bit addresses.

{|class="wikitable" style="text-align:center"
|+ PIC18 16-bit instruction set<ref>{{Citation |url=http://ww1.microchip.com/downloads/en/DeviceDoc/39605F.pdf |title=PIC18F1220/1320 Data Sheet |year=2007 |author=Microchip Technology, Inc. |access-date=2012-04-02}}</ref>
|-
! 1<br/>5 || 1<br/>4 || 1<br/>3 || 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 || <br/>8 || <br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || C<br/>? || Z<br/>? || N<br/>? || Description
|-
|colspan=21|
|-
! 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=8| ''opcode'' ||colspan=5| Miscellaneous instructions
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||align=left| NOP || || || ||align=left| No operation
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 ||align=left| SLEEP || || || ||align=left| Go into standby mode
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 ||align=left| CLRWDT || || || ||align=left| Restart watchdog timer
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 ||align=left| PUSH || || || ||align=left| Push PC on top of stack
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 ||align=left| POP || || || ||align=left| Pop (and discard) top of stack
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 ||align=left| DAW || C || || ||align=left| Decimal adjust W
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 ||align=left| TBLRD∗ || || || ||align=left| Table read: TABLAT ← mem[TBLPTR]
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 1 ||align=left| TBLRD∗+ || || || ||align=left| Table read with postincrement
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 || 0 ||align=left| TBLRD∗− || || || ||align=left| Table read with postdecrement
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 || 1 ||align=left| TBLRD+∗ || || || ||align=left| Table read with pre-increment
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 ||colspan=2| ''mod'' ||align=left| TBLWR || || || ||align=left| Table write, same modes as TBLRD
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 || ''s'' ||align=left| RETFIE [, FAST] || || || ||align=left| Return from interrupt
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 1 || ''s'' ||align=left| RETURN [, FAST] || || || ||align=left| Return from subroutine
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 || 0 || 0 ||align=left| CALLW<sup>*</sup> || || || ||align=left| Push PC, jump to PCLATU:PCLATH:W
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || 1 || 1 || 1 || 1 || 1 ||align=left| RESET || 0 || 0 ||0 ||align=left| Software reset
|-
|colspan=21|
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||style="background:lightgrey;" colspan=4| &mdash;0&mdash; ||colspan=4| ''k'' ||align=left| MOVLB || || || ||align=left| Move literal ''k'' to bank select register
|-
! 0 || 0 || 0 || 0 || 1 ||colspan=3| ''opcode'' ||colspan=8| ''literal'' ||colspan=5| Literal operations: W ← OP(k,W)
|-
| 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 ||colspan=8| ''k'' ||align=left| SUBLW ''k'' || || || ||align=left| W ← k − W
|-
| 0 || 0 || 0 || 0 || 1 || 0 || 0 || 1 ||colspan=8| ''k'' ||align=left| IORLW ''k'' || || || ||align=left| W ← k {{pipe}} W, logical inclusive or
|-
| 0 || 0 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=8| ''k'' ||align=left| XORLW ''k'' || || || ||align=left| W ← k ^ W, exclusive or
|-
| 0 || 0 || 0 || 0 || 1 || 0 || 1 || 1 ||colspan=8| ''k'' ||align=left| ANDLW ''k'' || || || ||align=left| W ← k & W, logical and
|-
| 0 || 0 || 0 || 0 || 1 || 1 || 0 || 0 ||colspan=8| ''k'' ||align=left| RETLW ''k'' || || || ||align=left| RETURN W ← k
|-
| 0 || 0 || 0 || 0 || 1 || 1 || 0 || 1 ||colspan=8| ''k'' ||align=left| MULLW ''k'' || || || ||align=left| W ← k × W
|-
| 0 || 0 || 0 || 0 || 1 || 1 || 1 || 0 ||colspan=8| ''k'' ||align=left| MOVLW ''k'' || || || ||align=left| W ← k
|-
| 0 || 0 || 0 || 0 || 1 || 1 || 1 || 1 ||colspan=8| ''k'' ||align=left| ADDLW ''k'' || || || ||align=left| W ← k + W
|-
|colspan=21|
|-
! 0 ||colspan=5| ''opcode'' || ''d'' || ''a'' ||colspan=8| ''register'' ||colspan=5| ALU operations: dest ← OP(f,W)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || ''a'' ||colspan=8| ''f'' ||align=left| MULWF ''f'',''a'' || || || ||align=left| PRODH:PRODL ← W × f (unsigned)
|-
| 0 || 0 || 0 || 0 || 0 || 1 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| DECF ''f'',''d'',''a'' || C || Z || N ||align=left| dest ← f − 1
|-
| 0 || 0 || 0 || 1 || 0 || 0 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| IORWF ''f'',''d'',''a'' || || Z || N ||align=left| dest ← f {{pipe}} W, logical inclusive or
|-
| 0 || 0 || 0 || 1 || 0 || 1 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| ANDWF ''f'',''d'',''a'' || || Z || N ||align=left| dest ← f & W, logical and
|-
| 0 || 0 || 0 || 1 || 1 || 0 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| XORWF ''f'',''d'',''a'' || || Z || N ||align=left| dest ← f ^ W, exclusive or
|-
| 0 || 0 || 0 || 1 || 1 || 1 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| COMF ''f'',''d'',''a'' || || Z || N ||align=left| dest ← ~f, bitwise complement
|-
| 0 || 0 || 1 || 0 || 0 || 0 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| ADDWFC ''f'',''d'',''a'' || C || Z || N ||align=left| dest ← f + W + C
|-
| 0 || 0 || 1 || 0 || 0 || 1 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| ADDWF ''f'',''d'',''a'' || C || Z || N ||align=left| dest ← f + W
|-
| 0 || 0 || 1 || 0 || 1 || 0 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| INCF ''f'',''d'',''a'' || C || Z || N ||align=left| dest ← f + 1
|-
| 0 || 0 || 1 || 0 || 1 || 1 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| DECFSZ ''f'',''d'',''a'' || || || ||align=left| dest ← f − 1, skip if 0
|-
| 0 || 0 || 1 || 1 || 0 || 0 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| RRCF ''f'',''d'',''a'' || C || Z || N ||align=left| dest ← f>>1 {{pipe}} C<<7, rotate right through carry
|-
| 0 || 0 || 1 || 1 || 0 || 1 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| RLCF ''f'',''d'',''a'' || C || Z || N ||align=left| dest ← f<<1 {{pipe}} C, rotate left through carry
|-
| 0 || 0 || 1 || 1 || 1 || 0 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| SWAPF ''f'',''d'',''a'' || || || ||align=left| dest ← f<<4 {{pipe}} f>>4, swap nibbles
|-
| 0 || 0 || 1 || 1 || 1 || 1 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| INCFSZ ''f'',''d'',''a'' || || || ||align=left| dest ← f + 1, skip if 0
|-
| 0 || 1 || 0 || 0 || 0 || 0 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| RRNCF ''f'',''d'',''a'' || || Z || N ||align=left| dest ← f>>1 {{pipe}} f<<7, rotate right (no carry)
|-
| 0 || 1 || 0 || 0 || 0 || 1 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| RLNCF ''f'',''d'',''a'' || || Z || N ||align=left| dest ← f<<1 {{pipe}} f>>7, rotate left (no carry)
|-
| 0 || 1 || 0 || 0 || 1 || 0 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| INFSNZ ''f'',''d'',''a'' || || || ||align=left| dest ← f + 1, skip if not 0
|-
| 0 || 1 || 0 || 0 || 1 || 1 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| DCFSNZ ''f'',''d'',''a'' || || || ||align=left| dest ← f − 1, skip if not 0
|-
| 0 || 1 || 0 || 1 || 0 || 0 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| MOVF ''f'',''d'',''a'' || || Z || N ||align=left| dest ← f
|-
| 0 || 1 || 0 || 1 || 0 || 1 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| SUBFWB ''f'',''d'',''a'' || C || Z || N ||align=left| dest ← W + ~f + C (dest ← W − f − C̅)
|-
| 0 || 1 || 0 || 1 || 1 || 0 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| SUBWFB ''f'',''d'',''a'' || C || Z || N ||align=left| dest ← f + ~W + C (dest ← f − W − C̅)
|-
| 0 || 1 || 0 || 1 || 1 || 1 || ''d'' || ''a'' ||colspan=8| ''f'' ||align=left| SUBWF ''f'',''d'',''a'' || C || Z || N ||align=left| dest ← f − W (dest ← f + ~W + 1)
|-
|colspan=21|
|-
! 0 || 1 || 1 || 0 ||colspan=3| ''opcode''  || ''a'' ||colspan=8| ''register'' ||colspan=5| ALU operations, do not write to W
|-
| 0 || 1 || 1 || 0 || 0 || 0 || 0 || ''a'' ||colspan=8| ''f'' ||align=left| CPFSLT ''f'',''a'' || || || ||align=left| skip if f &lt; W (unsigned)
|-
| 0 || 1 || 1 || 0 || 0 || 0 || 1 || ''a'' ||colspan=8| ''f'' ||align=left| CPFSEQ ''f'',''a'' || || || ||align=left| skip if f == W
|-
| 0 || 1 || 1 || 0 || 0 || 1 || 0 || ''a'' ||colspan=8| ''f'' ||align=left| CPFSGT ''f'',''a'' || || || ||align=left| skip if f &gt; W (unsigned)
|-
| 0 || 1 || 1 || 0 || 0 || 1 || 1 || ''a'' ||colspan=8| ''f'' ||align=left| TSTFSZ ''f'',''a'' || || || ||align=left| skip if f == 0
|-
| 0 || 1 || 1 || 0 || 1 || 0 || 0 || ''a'' ||colspan=8| ''f'' ||align=left| SETF ''f'',''a'' || || || ||align=left| f ← 0xFF
|-
| 0 || 1 || 1 || 0 || 1 || 0 || 1 || ''a'' ||colspan=8| ''f'' ||align=left| CLRF ''f'',''a'' || || 1 || ||align=left| f ← 0, PSR.Z ← 1
|-
| 0 || 1 || 1 || 0 || 1 || 1 || 0 || ''a'' ||colspan=8| ''f'' ||align=left| NEGF ''f'',''a'' || C || Z || N ||align=left| f ← −f
|-
| 0 || 1 || 1 || 0 || 1 || 1 || 1 || ''a'' ||colspan=8| ''f'' ||align=left| MOVWF ''f'',''a'' || || || ||align=left| f ← W
|-
|colspan=21|
|-
| 0 || 1 || 1 || 1 ||colspan=3| ''bit'' || ''a'' ||colspan=8| ''f'' ||align=left| BTG ''f'',''b'',''a'' || || || ||align=left| Toggle bit b of f
|-
! 1 || 0 ||colspan=2| ''opc''  ||colspan=3| ''bit'' || ''a'' ||colspan=8| ''register'' ||colspan=5| Bit operations
|-
| 1 || 0 || 0 || 0 ||colspan=3| ''bit'' || ''a'' ||colspan=8| ''f'' ||align=left| BSF ''f'',''b'',''a'' || || || ||align=left| Set bit b of f
|-
| 1 || 0 || 0 || 1 ||colspan=3| ''bit'' || ''a'' ||colspan=8| ''f'' ||align=left| BCF ''f'',''b'',''a'' || || || ||align=left| Clear bit b of f
|-
| 1 || 0 || 1 || 0 ||colspan=3| ''bit'' || ''a'' ||colspan=8| ''f'' ||align=left| BTFSS ''f'',''b'',''a'' || || || ||align=left| Skip if bit b of f is set
|-
| 1 || 0 || 1 || 1 ||colspan=3| ''bit'' || ''a'' ||colspan=8| ''f'' ||align=left| BTFSC ''f'',''b'',''a'' || || || ||align=left| Skip if bit b of f is clear
|-
|colspan=21|
|-
! 1 || 1 || 0 ||colspan=2| ''opc''  ||colspan=12| ''address'' ||colspan=5| Large-address operations
|-
| 1 || 1 || 0 || 0 ||colspan=12| ''source'' || style="text-align:left;" rowspan="2"| MOVFF ''s'',''d'' ||rowspan=2| ||rowspan=2| ||rowspan=2| || style="text-align:left;" rowspan="2"| Move absolute
|-
| 1 || 1 || 1 || 1 ||colspan=12| ''destination''
|-
| 1 || 1 || 0 || 1 || 0 ||colspan=11| ''n'' ||align=left| BRA ''n'' || || || ||align=left| Branch to PC + 2''n''
|-
| 1 || 1 || 0 || 1 || 1 ||colspan=11| ''n'' ||align=left| RCALL ''n'' || || || ||align=left| Subroutine call to PC + 2''n''
|-
|colspan=21|
|-
! 1 || 1 || 1 || 0 || 0 ||colspan=3| ''cond''  ||colspan=8| ''n'' ||colspan=5| Conditional branch (to PC+2''n'')
|-
| 1 || 1 || 1 || 0 || 0 || 0 || 0 || 0 ||colspan=8| ''n'' ||align=left| BZ ''n'' || || || ||align=left| Branch if PSR.Z is set
|-
| 1 || 1 || 1 || 0 || 0 || 0 || 0 || 1 ||colspan=8| ''n'' ||align=left| BNZ ''n'' || || || ||align=left| Branch if PSR.Z is clear
|-
| 1 || 1 || 1 || 0 || 0 || 0 || 1 || 0 ||colspan=8| ''n'' ||align=left| BC ''n'' || || || ||align=left| Branch if PSR.C is set
|-
| 1 || 1 || 1 || 0 || 0 || 0 || 1 || 1 ||colspan=8| ''n'' ||align=left| BNC ''n'' || || || ||align=left| Branch if PSR.C is clear
|-
| 1 || 1 || 1 || 0 || 0 || 1 || 0 || 0 ||colspan=8| ''n'' ||align=left| BOV ''n'' || || || ||align=left| Branch if PSR.V is set
|-
| 1 || 1 || 1 || 0 || 0 || 1 || 0 || 1 ||colspan=8| ''n'' ||align=left| BNOV ''n'' || || || ||align=left| Branch if PSR.V is clear
|-
| 1 || 1 || 1 || 0 || 0 || 1 || 1 || 0 ||colspan=8| ''n'' ||align=left| BN ''n'' || || || ||align=left| Branch if PSR.N is set
|-
| 1 || 1 || 1 || 0 || 0 || 1 || 1 || 1 ||colspan=8| ''n'' ||align=left| BNN ''n'' || || || ||align=left| Branch if PSR.N is clear
|-
|colspan=21|
|-
! 1 || 1 || 1 || 0 || 1 || 0 ||colspan=2| ''opc'' ||colspan=8| ''k'' ||colspan=5| Extensions for using FSR2 as software stack pointer<sup>*</sup>
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 0 || 0 ||colspan=2| ''n'' ||colspan=6| ''k'' ||align=left| ADDFSR ''n'',''k''<sup>*</sup> || || || ||align=left| FSRn += k
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 0 || 0 || 1 || 1 ||colspan=6| ''k'' ||align=left| ADDULNK ''k''<sup>*</sup> || || || ||align=left| FSR2 += k, pop PC
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 0 || 1 ||colspan=2| ''n'' ||colspan=6| ''k'' ||align=left| SUBFSR ''n'',''k''<sup>*</sup> || || || ||align=left| FSRn −= k
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 0 || 1 || 1 || 1 ||colspan=6| ''k'' ||align=left| SUBULNK ''k''<sup>*</sup>||  || || ||align=left| FSR2 −= k, pop PC
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 1 || 0 ||colspan=8| ''k'' ||align=left| PUSHL ''k''<sup>*</sup> || || || ||align=left| [FSR2] ← k, decrement FSR2
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 1 || 1 || 0 ||colspan=7| ''s'' ||rowspan=2 align=left| MOVSF ''src'',''f''{{hair space}}<sup>*</sup> ||rowspan=2| ||rowspan=2| ||rowspan=2| ||rowspan=2 align=left| f ← FSR2[s]
|-
| 1 || 1 || 1 || 1 ||colspan=12| ''f''
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 1 || 1 || 1 || colspan="7" |''s'' ||rowspan=2 align=left| MOVSS ''src'',''dst''<sup>*</sup>|| rowspan="2" |  ||rowspan=2| ||rowspan=2| ||rowspan=2 align=left| FSR2[d] ← FSR2[s]
|-
| 1 || 1 || 1 || 1 ||colspan=5 style="background:lightgrey;| —0— ||colspan=7| ''d''
|-
|colspan=21|
|-
! 1 || 1 || 1 || 0 || 1 || 1 ||colspan=2| ''opc''  ||colspan=8| ''k'' ||colspan=5| 2-word instructions
|-
| 1 || 1 || 1 || 0 || 1 || 1 || 0 || ''s'' ||colspan=8| ''k'' (lsbits) || style="text-align:left;" rowspan="2"| CALL ''k''[, FAST] ||rowspan=2| ||rowspan=2| ||rowspan=2| || style="text-align:left;" rowspan="2"| Call subroutine (20-bit address)
|-
| 1 || 1 || 1 || 1 ||colspan=12| ''k'' (msbits)
|-
| 1 || 1 || 1 || 0 || 1 || 1 || 1 || 0 ||style="background:lightgrey;"| 0 ||style="background:lightgrey;"| 0 ||colspan=2| ''f'' ||colspan=4| ''k'' (msb) || style="text-align:left;" rowspan="2"| LFSR ''f'',''k'' ||rowspan=2| ||rowspan=2| ||rowspan=2| || style="text-align:left;" rowspan="2"| Move 12-bit literal to FSR''f''
|-
| 1 || 1 || 1 || 1 || 0 || 0 || 0 || 0 ||colspan=8| ''k'' (lsbits)
|-
| 1 || 1 || 1 || 0 || 1 || 1 || 1 || 1 ||colspan=8| ''k'' (lsbits) || style="text-align:left;" rowspan="2"| GOTO ''k'' ||rowspan=2| ||rowspan=2| ||rowspan=2| || style="text-align:left;" rowspan="2"| Absolute jump, PC ← k (20-bit address)
|-
| 1 || 1 || 1 || 1 ||colspan=12| ''k'' (msbits)
|-
|colspan=21|
|-
! 1 || 1 || 1 || 1 ||colspan=12| ''k'' ||colspan=5| No operation, second word of 2-word instructions
|-
|colspan=21|
|-
! 1<br/>5 || 1<br/>4 || 1<br/>3 || 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 || <br/>8 || <br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Mnemonic || C<br/>? || Z<br/>? || N<br/>? || Description
|}
<nowiki/>*: These extended instructions are only available on some models, and then only if the <code>XINST</code> configuration bit is set.

==PIC24 and dsPIC 16-bit microcontrollers==
In 2001, Microchip introduced the dsPIC series of chips,<ref>
{{Cite web
|url=http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2018&mcparam=en013529
|title = Microchip Technology debuts world's highest performing 16-bit microcontrollers: dsPIC
|archive-url=https://web.archive.org/web/20041213035811/http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2018&mcparam=en013529
|archive-date=2004-12-13
}}</ref>
which entered mass production in late 2004. They are Microchip's first inherently 16-bit microcontrollers.  PIC24 devices are designed as general purpose microcontrollers.  dsPIC devices include [[digital signal processing]] capabilities in addition.

Instructions come in two main varieties.  One is like the classic one-operand PIC instructions, with an operation between W0 and a value in a specified f register (i.e. the first 8K of RAM), and a destination select bit selecting which is updated with the result.  The W registers are memory-mapped, so the f operand may specify a W register.

The other form, new to the PIC24, specifies three W register operands, two of which allow a 3-bit addressing mode specification:

{|class="wikitable" style="text-align:center"
|+ PIC24 addressing modes
|-
!colspan=3| source operand               ||colspan=3| destination operand          ||rowspan=2| Description
|-
! ppp     || Reg      || Syntax          || qqq     || Reg      || Syntax
|-
| 000     || ''ssss'' || W''s''          || 000     || ''dddd'' || W''d''          ||align=left| Register direct
|-
| 001     || ''ssss'' || [W''s'']        || 001     || ''dddd'' || [W''d'']        ||align=left| Indirect
|-
| 010     || ''ssss'' || [W''s''−−]      || 010     || ''dddd'' || [W''d''−−]      ||align=left| Indirect with postdecrement
|-
| 011     || ''ssss'' || [W''s''++]      || 011     || ''dddd'' || [W''d''++]      ||align=left| Indirect with postincrement
|-
| 100     || ''ssss'' || [−−W''s'']      || 100     || ''dddd'' || [−−W''d'']      ||align=left| Indirect with predecrement
|-
| 101     || ''ssss'' || [++W''s'']      || 101     || ''dddd'' || [++W''d'']      ||align=left| Indirect with preincrement
|-
| 11''k'' || ''kkkk'' || #''u5''         ||colspan=3 style="background:lightgrey;"| (Unused, illegal) ||align=left| 5-bit unsigned immediate
|-
| 11''x'' || ''ssss'' || [W''s''+W''w''] || 11''x'' || ''dddd'' || [W''d''+W''w''] ||align=left| Indirect with register offset
|}
The register offset addressing mode is only available for the <code>MOV ''src'',''dst''</code> instruction, where the Ww register may be used as a register offset for the source, destination, or both.  All other instructions use this encoding for an unsigned 5-bit immediate source instead.

For the operands to <code>TBLRD</code> and <code>TBLWT</code> which access program memory, only the indirect modes are allowed, and refer to addresses in code memory.

A few instructions are 2 words long.  The second word is a NOP, which includes up to 16 bits of additional immediate operand.

{|class="wikitable" style="text-align:center"
|+ PIC24 24-bit instruction set<ref name="dsPIC30F">{{Citation |url=http://ww1.microchip.com/downloads/en/DeviceDoc/70157C.pdf |title=dsPIC30F Programmer's Reference Manual |year=2008 |publisher=Microchip Technology |id=DS70157C |access-date=2012-07-02}}</ref>
|-

! 2<br>3 || 2<br>2 || 2<br>1 || 2<br>0 || 1<br>9 || 1<br>8 || 1<br>7 || 1<br>6 || 1<br>5 || 1<br>4 || 1<br>3 || 1<br>2 || 1<br>1 || 1<br>0 || <br>9 || <br>8 || <br>7 || <br>6 || <br>5 || <br>4 || <br>3 || <br>2 || <br>1 || <br>0 || Mnemonic || C<br>? || Z<br>? || N<br>? || Description
<!--|-
!colspan=4| 23–20 ||colspan=4| 19–16 ||colspan=4| 15–12 ||colspan=4| 11–8 ||colspan=4| 7–4 ||colspan=4 width=45pt| 3–0 || Mnemonic || C<br/>? || Z<br/>? || N<br/>? || Description-->
|-
|colspan=29|
|-
! 0 || 0 || 0 || 0 ||colspan=4| ''opcode'' ||colspan=16| ''offset'' ||colspan=5| Control transfers
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=16| — ||align=left| NOP || || || ||align=left| No operation
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||style="background:lightgrey;" colspan=9| &mdash;0&mdash; ||colspan=7| ''n''&lt;22:16&gt; ||align=left| CALL/GOTO ''addr23'' || || || ||align=left| (second word)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=16| ''n'' ||align=left| DO #''k'',''addr'' || || || ||align=left| (second word)
|-
|colspan=29|
|-
! 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 ||colspan=2| ''opc'' ||colspan=9| —0— ||colspan=4| a ||colspan=5| Computed control transfer (to 16-bit Wa)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 ||colspan=9 style="background:lightgrey;"| —0— ||colspan=4| ''a'' ||align=left| CALL R''a'' || || || ||align=left| Push PC, jump to Wa
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 1 ||colspan=9 style="background:lightgrey;"| —0— ||colspan=4| ''a'' ||align=left| RCALL R''a'' || || || ||align=left| Push PC, jump to PC+2×Wa
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=9 style="background:lightgrey;"| —0— ||colspan=4| ''a'' ||align=left| GOTO R''a'' || || || ||align=left| Jump to Wa
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 || 1 ||colspan=9 style="background:lightgrey;"| —0— ||colspan=4| ''a'' ||align=left| BRA R''a'' || || || ||align=left| Jump to PC+2×Wa
|-
|colspan=29|
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 ||colspan=15| ''n''&lt;15:1&gt; || 0 || style="text-align:left;" rowspan="2"| CALL&nbsp;''addr23'' ||rowspan=2| ||rowspan=2| ||rowspan=2| || style="text-align:left;" rowspan="2"| Push PC, jump to absolute address
|-
|colspan=8| —0— ||colspan=9 style="background:lightgrey;"| —0—  ||colspan=7| ''n''&lt;22:16&gt;
|-style="background:lightgrey;"
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 ||colspan=16| — || colspan="5" style="text-align:left;"| (Reserved)
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 0 || 0 ||colspan=15| ''n'' || 0 || style="text-align:left;" rowspan="2"| GOTO&nbsp;''addr23'' ||rowspan=2| ||rowspan=2| ||rowspan=2| || style="text-align:left;" rowspan="2"| Jump to absolute address
|-
|colspan=8| —0— ||colspan=9 style="background:lightgrey;"| —0—  ||colspan=7| ''n''&lt;22:16&gt;
|-style="background:lightgrey;"
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 0 || 1 || 0 || B ||colspan=10| ''k'' ||colspan=4| ''d'' ||align=left| RETLW[.B]&nbsp;#''k'',W''d'' || || || ||align=left| Wd = k, pop PC
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 0 ||colspan=14 style="background:lightgrey;"| —0— ||align=left| RETURN || || || ||align=left| pop PC
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 1 ||colspan=14 style="background:lightgrey;"| —0— ||align=left| RETFIE || C || Z || N ||align=left| pop SR, PC
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 ||colspan=16| ''n'' ||align=left| RCALL ''address'' || || || ||align=left| Push PC, PC += 2×s16
|-
| 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 || 0 || 0 ||colspan=14| ''k'' || style="text-align:left;" rowspan="2"| DO #''k'',''addr'' ||rowspan=2| ||rowspan=2| ||rowspan=2| || style="text-align:left;" rowspan="2"| Zero-overhead loop: k+1 is repeat count, PC+2×n last instruction 
|-
|colspan=8| —0— ||colspan=16| ''n''
|-
| 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 || 0 || 0 ||colspan=14| ''k'' ||align=left| REPEAT #''k'' || || || ||align=left| Repeat next instruction k+1 times
|-
| 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 ||colspan=16| ''n'' ||align=left| RCALL ''address'' || || || ||align=left| Push PC, PC += 2×s16
|-style="background:lightgrey;"
| 0 || 0 || 0 || 0 || 1 || 0 || 1 ||colspan=17| — || colspan="5" style="text-align:left;"| (Reserved)
|-
| 0 || 0 || 0 || 0 || 1 || 1 || 0 || ''a'' ||colspan=16| ''n'' ||align=left| BRA O''a'', addr || || || ||rowspan=2 align=left| If accumulator an overflowed/saturated, PC += 2×simm16
|-
| 0 || 0 || 0 || 0 || 1 || 1 || 1 || ''a'' ||colspan=16| ''n'' ||align=left| BRA S''a'', addr || || ||
|-
|colspan=29|
|-
! 0 ||colspan=4| ''opcode'' ||colspan=4| ''w'' || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||colspan=5| Reverse subtract: ''dest'' ← ''source'' − W''w''
|-
| 0 || 0 || 0 || 1 || 0 ||colspan=4| ''w'' || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| SUBR[.B] W''w'',''src'',''dst'' || C || Z || N ||align=left| dst ← src − Ww = src + ~Ww + 1)
|-
| 0 || 0 || 0 || 1 || 1 ||colspan=4| ''w'' || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| SUBBR[.B]&nbsp;W''w'',''src'',''dst'' || C || Z || N ||align=left| dst ← src − Ww − C̅ = src + ~Ww + C
|-
| 0 || 0 || 1 || 0 ||colspan=16| ''k'' ||colspan=4| ''d'' ||align=left| MOV #''k'',W''d'' || || || ||align=left| Wd ← #imm16
|-
|colspan=29|
|-
! 0 || 0 || 1 || 1 ||colspan=4| ''cond'' ||colspan=16| ''n'' ||colspan=5| Conditional branch to PC+2×''n''
|-
| 0 || 0 || 1 || 1 || 0 || 0 || 0 || 0 ||colspan=16| ''n'' ||align=left| BRA OV,''addr'' || || || ||align=left| ...if PSR.V is set 
|-
| 0 || 0 || 1 || 1 || 0 || 0 || 0 || 1 ||colspan=16| ''n'' ||align=left| BRA C,''addr'' || || || ||align=left| ...if PSR.C is set 
|-
| 0 || 0 || 1 || 1 || 0 || 0 || 1 || 0 ||colspan=16| ''n'' ||align=left| BRA Z,''addr'' || || || ||align=left| ...if PSR.Z is set 
|-
| 0 || 0 || 1 || 1 || 0 || 0 || 1 || 1 ||colspan=16| ''n'' ||align=left| BRA N,''addr'' || || || ||align=left| ...if PSR.N is set 
|-
| 0 || 0 || 1 || 1 || 0 || 1 || 0 || 0 ||colspan=16| ''n'' ||align=left| BRA LE,''addr'' || || || ||align=left| ...if PSR.Z, or PSR.N ≠ PSR.V 
|-
| 0 || 0 || 1 || 1 || 0 || 1 || 0 || 1 ||colspan=16| ''n'' ||align=left| BRA LT,''addr'' || || || ||align=left| ...if PSR.N ≠ PSR.V 
|-
| 0 || 0 || 1 || 1 || 0 || 1 || 1 || 0 ||colspan=16| ''n'' ||align=left| BRA LEU,''addr'' || || || ||align=left| ...if PSR.Z is set, or PSR.C is clear 
|-
| 0 || 0 || 1 || 1 || 0 || 1 || 1 || 1 ||colspan=16| ''n'' ||align=left| BRA ''addr'' || || || ||align=left| ...unconditionally 
|-
| 0 || 0 || 1 || 1 || 1 || 0 || 0 || 0 ||colspan=16| ''n'' ||align=left| BRA NOV,''addr'' || || || ||align=left| ...if PSR.V is clear 
|-
| 0 || 0 || 1 || 1 || 1 || 0 || 0 || 1 ||colspan=16| ''n'' ||align=left| BRA NC,''addr'' || || || ||align=left| ...if PSR.C is clear 
|-
| 0 || 0 || 1 || 1 || 1 || 0 || 1 || 0 ||colspan=16| ''n'' ||align=left| BRA NZ,''addr'' || || || ||align=left| ...if PSR.Z is clear 
|-
| 0 || 0 || 1 || 1 || 1 || 0 || 1 || 1 ||colspan=16| ''n'' ||align=left| BRA NN,''addr'' || || || ||align=left| ...if PSR.N is clear 
|-
| 0 || 0 || 1 || 1 || 1 || 1 || 0 || 0 ||colspan=16| ''n'' ||align=left| BRA GT,''addr'' || || || ||align=left| ...if PSR.Z is clear, and PSR.N = PSR.V 
|-
| 0 || 0 || 1 || 1 || 1 || 1 || 0 || 1 ||colspan=16| ''n'' ||align=left| BRA GE,''addr'' || || || ||align=left| ...if PSR.N = PSR.V 
|-
| 0 || 0 || 1 || 1 || 1 || 1 || 1 || 0 ||colspan=16| ''n'' ||align=left| BRA GTU,''addr'' || || || ||align=left| ...if PSR.Z is clear, and PSR.C is set 
|-style="background:lightgrey;"
| 0 || 0 || 1 || 1 || 1 || 1 || 1 || 1 ||colspan=16| ''n'' || colspan="5" style="text-align:left;"| (Reserved)
|-
|colspan=29|
|-
! 0 ||colspan=4| ''opcode'' ||colspan=4| ''w'' || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||colspan=5| ALU operations: ''dest'' ← OP(W''w'',''source'')
|-
| 0 || 1 || 0 || 0 || 0 ||colspan=4| ''w'' || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| ADD[.B] W''w'',''src'',''dst'' || C || Z || N ||align=left| dst ← Ww + src
|-
| 0 || 1 || 0 || 0 || 1 ||colspan=4| ''w'' || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| ADDC[.B] W''w'',''src'',''dst'' || C || Z || N ||align=left| dst ← Ww + src + C
|-
| 0 || 1 || 0 || 1 || 0 ||colspan=4| ''w'' || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| SUB[.B] W''w'',''src'',''dst'' || C || Z || N ||align=left| dst ← Ww − src
|-
| 0 || 1 || 0 || 1 || 1 ||colspan=4| ''w'' || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| SUBB[.B] W''w'',''src'',''dst'' || C || Z || N ||align=left| dst ← Ww − ~src − C̅ = Ww + ~src + C
|-
| 0 || 1 || 1 || 0 || 0 ||colspan=4| ''w'' || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| AND[.B] W''w'',''src'',''dst'' || || Z || N ||align=left| dst ← Ww & src
|-
| 0 || 1 || 1 || 0 || 1 ||colspan=4| ''w'' || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| XOR[.B] W''w'',''src'',''dst'' || || Z || N ||align=left| dst ← Ww ^ src
|-
| 0 || 1 || 1 || 1 || 0 ||colspan=4| ''w'' || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| IOR[.B] W''w'',''src'',''dst'' || || Z || N ||align=left| dst ← Ww {{pipe}} src
|-
| 0 || 1 || 1 || 1 || 1 ||colspan=4| ''w'' || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| MOV[.B] ''src'',''dst'' || || Z || N ||align=left| dst ← src (offset mode allowed)
|-
|colspan=29|
|-
| 1 || 0 || 0 || 0 || 0 ||colspan=15| ''f'' ||colspan=4| ''d'' ||align=left| MOV ''f'',W''d'' || || || ||align=left| Wd ← f
|-
| 1 || 0 || 0 || 0 || 1 ||colspan=15| ''f'' ||colspan=4| ''s'' ||align=left| MOV W''s'',''f'' || || || ||align=left| f ← Ws
|-
| 1 || 0 || 0 || 1 || 0 ||colspan=4| ''k'' || ''B'' ||colspan=3| ''k'' ||colspan=4| ''d'' ||colspan=3| ''k'' ||colspan=4| ''s'' ||align=left| MOV[.B]&nbsp;[W''s''+''s10''],W''d'' || || || ||align=left| Load with 10-bit offset
|-
| 1 || 0 || 0 || 1 || 1 ||colspan=4| ''k'' || ''B'' ||colspan=3| ''k'' ||colspan=4| ''d'' ||colspan=3| ''k'' ||colspan=4| ''s'' ||align=left| MOV[.B]&nbsp;''Ws'',[''Wd''+''s10''] || || || ||align=left| Store with 10-bit offset
|-
|colspan=29|
|-
! 1 || 0 || 1 || 0 || 0 ||colspan=3| ''opcode'' ||colspan=4| ''b'' || ''Z'' || ''B'' ||colspan=3| —0— ||colspan=3| ''p'' ||colspan=4| ''s'' ||colspan=5| Bit operations on ''source''
|-
| 1 || 0 || 1 || 0 || 0 || 0 || 0 || 0 ||colspan=4| ''b'' || 0 || ''B'' ||colspan=3 style="background:lightgrey;"| —0— ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| BSET[.B] #''b'',''src'' || || || ||align=left| Set bit b of src
|-
| 1 || 0 || 1 || 0 || 0 || 0 || 0 || 1 ||colspan=4| ''b'' || 0 || ''B'' ||colspan=3 style="background:lightgrey;"| —0— ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| BCLR[.B] #''b'',''src'' || || || ||align=left| Clear bit b of src
|-
| 1 || 0 || 1 || 0 || 0 || 0 || 1 || 0 ||colspan=4| ''b'' || 0 || ''B'' ||colspan=3 style="background:lightgrey;"| —0— ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| BTG[.B] #''b'',''src'' || || || ||align=left| Toggle bit b of src
|-
| 1 || 0 || 1 || 0 || 0 || 0 || 1 || 1 ||colspan=4| ''b'' || 0 || 0 ||colspan=3 style="background:lightgrey;"| —0— ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| BTST.C #''b'',''src'' || C || || ||align=left| Set PSR.C = bit b of src
|-
| 1 || 0 || 1 || 0 || 0 || 0 || 1 || 1 ||colspan=4| ''b'' || 1 || 0 ||colspan=3 style="background:lightgrey;"| —0— ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| BTST.Z #''b'',''src'' || || Z || ||align=left| Set PSR.Z = {{overline|bit b of src}}
|-
| 1 || 0 || 1 || 0 || 0 || 1 || 0 || 0 ||colspan=4| ''b'' || ''Z'' || 0 ||colspan=3 style="background:lightgrey;"| —0— ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| BTSTS.''z'' #''b'',''src'' ||colspan=2| C/Z || ||align=left| Test bit b of src (into C or Z), then set
|-
| 1 || 0 || 1 || 0 || 0 || 1 || 0 || 1 || ''Z'' ||colspan=4| ''w'' || 0 ||colspan=3 style="background:lightgrey;"| —0— ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| BTST.''z'' W''w'',''src'' ||colspan=2| C/Z || ||align=left| Test bit Ww of src
|-
| 1 || 0 || 1 || 0 || 0 || 1 || 1 || 0 ||colspan=4| ''b'' || 0 || 0 ||colspan=3 style="background:lightgrey;"| —0— ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| BTSS #''b'',''src'' || || || ||align=left| Test bit, skip if set
|-
| 1 || 0 || 1 || 0 || 0 || 1 || 1 || 1 ||colspan=4| ''b'' || 0 || 0 ||colspan=3 style="background:lightgrey;"| —0— ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| BTS #''b'',''src'' || || || ||align=left| Test bit, skip if clear
|-
|colspan=29|
|-
! 1 || 0 || 1 || 0 || 1 ||colspan=3| ''opcode'' ||colspan=3| ''b'' ||colspan=13| ''f'' ||colspan=5| Bit operations on ''f''
|-
| 1 || 0 || 1 || 0 || 1 || 0 || 0 || 0 ||colspan=3| ''b'' ||colspan=12| ''f'' || ''b'' ||align=left| BSET[.B] ''f'',#''b'' || || || ||align=left| Set bit b of f
|-
| 1 || 0 || 1 || 0 || 1 || 0 || 0 || 1 ||colspan=3| ''b'' ||colspan=13| ''f'' ||align=left| BCLR.B ''f'',#''b'' || || || ||align=left| Clear bit b of f
|-
| 1 || 0 || 1 || 0 || 1 || 0 || 1 || 0 ||colspan=3| ''b'' ||colspan=13| ''f'' ||align=left| BTG.B ''f'',#''b'' || || || ||align=left| Toggle bit b of f
|-
| 1 || 0 || 1 || 0 || 1 || 0 || 1 || 1 ||colspan=3| ''b'' ||colspan=13| ''f'' ||align=left| BTST.B ''f'',#''b'' || || Z || ||align=left| Test bit b of f
|-
| 1 || 0 || 1 || 0 || 1 || 1 || 0 || 0 ||colspan=3| ''b'' ||colspan=13| ''f'' ||align=left| BTSTS.B ''f'',#''b'' || || Z || ||align=left| Test bit b of f, then set
|-
| 1 || 0 || 1 || 0 || 1 || 1 || 0 || 1 || ''Z'' ||colspan=4| ''w'' || 0 ||colspan=3 style="background:lightgrey;"| —0— ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| BSW.''z'' ''src'',W''w'' || || || ||align=left| Copy PSW.C or {{overline|PSW.Z}} to bit Ww of src
|-
| 1 || 0 || 1 || 0 || 1 || 1 || 1 || 0 ||colspan=3| ''b'' ||colspan=13| ''f'' ||align=left| BTSS ''f'',#''b'' || || || ||align=left| Test bit, skip if set
|-
| 1 || 0 || 1 || 0 || 1 || 1 || 1 || 1 ||colspan=3| ''b'' ||colspan=13| ''f'' ||align=left| BTSC ''f'',#''b'' || || || ||align=left| Test bit, skip if clear
|-
|colspan=29|
|-
! 1 || 0 || 1 || 1 || 0 || 0 ||colspan=3| ''opcode'' || ''B'' ||colspan=10| ''k'' ||colspan=4| ''d'' ||colspan=5| Register-immediate operations: W''d'' ← OP(W''d'',''k'')
|-
| 1 || 0 || 1 || 1 || 0 || 0 || 0 || 0 || 0 || ''B'' ||colspan=10| ''k'' ||colspan=4| ''d'' ||align=left| ADD[.B] #''u10'',W''d'' || C || Z || N ||align=left| Wd ← Wd + k
|-
| 1 || 0 || 1 || 1 || 0 || 0 || 0 || 0 || 1 || ''B'' ||colspan=10| ''k'' ||colspan=4| ''d'' ||align=left| ADC[.B] #''u10'',W''d'' || C || Z || N ||align=left| Wd ← Wd + k + C
|-
| 1 || 0 || 1 || 1 || 0 || 0 || 0 || 1 || 0 || ''B'' ||colspan=10| ''k'' ||colspan=4| ''d'' ||align=left| SUB[.B] #''u10'',W''d'' || C || Z || N ||align=left| Wd ← Wd − k
|-
| 1 || 0 || 1 || 1 || 0 || 0 || 0 || 1 || 1 || ''B'' ||colspan=10| ''k'' ||colspan=4| ''d'' ||align=left| SUBB[.B] #''u10'',W''d'' || C || Z || N ||align=left| Wd ← Wd − k − C̅
|-
| 1 || 0 || 1 || 1 || 0 || 0 || 1 || 0 || 0 || ''B'' ||colspan=10| ''k'' ||colspan=4| ''d'' ||align=left| AND[.B] #''u10'',W''d'' || || Z || N ||align=left| Wd ← Wd & k
|-
| 1 || 0 || 1 || 1 || 0 || 0 || 1 || 0 || 1 || ''B'' ||colspan=10| ''k'' ||colspan=4| ''d'' ||align=left| XOR[.B] #''u10'',W''d'' || || Z || N ||align=left| Wd ← Wd ^ k
|-
| 1 || 0 || 1 || 1 || 0 || 0 || 1 || 1 || 0 || ''B'' ||colspan=10| ''k'' ||colspan=4| ''d'' ||align=left| IOR[.B] #''u10'',W''d'' || || Z || N ||align=left| Wd ← Wd {{pipe}} k
|-
| 1 || 0 || 1 || 1 || 0 || 0 || 1 || 1 || 1 || ''B'' ||colspan=10| ''k'' ||colspan=4| ''d'' ||align=left| MOV[.B] #''u10'',W''d'' || || || ||align=left| Wd ← k
|-
|colspan=29|
|-
! 1 || 0 || 1 || 1 || 0 || 1 ||colspan=3| ''opcode'' || ''B'' || ''D'' ||colspan=13| ''f'' ||colspan=5| ALU operations: dest ← OP(''f'',W0)
|-
| 1 || 0 || 1 || 1 || 0 || 1 || 0 || 0 || 0 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| ADD[.B] ''f''[,WREG] || C || Z || N ||align=left| dest ← f + W0
|-
| 1 || 0 || 1 || 1 || 0 || 1 || 0 || 0 || 1 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| ADC[.B] ''f''[,WREG] || C || Z || N ||align=left| dest ← f + W0 + C
|-
| 1 || 0 || 1 || 1 || 0 || 1 || 0 || 1 || 0 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| SUB[.B] ''f''[,WREG] || C || Z || N ||align=left| dest ← f − W0
|-
| 1 || 0 || 1 || 1 || 0 || 1 || 0 || 1 || 1 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| SUBB[.B] ''f''[,WREG] || C || Z || N ||align=left| dest ← f − W0 + C̅
|-
| 1 || 0 || 1 || 1 || 0 || 1 || 1 || 0 || 0 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| AND[.B] ''f''[,WREG] || || Z || N ||align=left| dest ← f & W0
|-
| 1 || 0 || 1 || 1 || 0 || 1 || 1 || 0 || 1 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| XOR[.B] ''f''[,WREG] || || Z || N ||align=left| dest ← f ^ W0
|-
| 1 || 0 || 1 || 1 || 0 || 1 || 1 || 1 || 0 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| IOR[.B] ''f''[,WREG] || || Z || N ||align=left| dest ← f {{pipe}} W0
|-
| 1 || 0 || 1 || 1 || 0 || 1 || 1 || 1 || 1 || ''B'' || 1 ||colspan=13| ''f'' ||align=left| MOV[.B] WREG,''f'' || || || ||align=left| f ← W0
|-
|colspan=29|
|-
! 1 || 0 || 1 || 1 || 1 || 0 || 0 ||colspan=2| ''opc'' ||colspan=4| ''w'' ||colspan=3| ''d'' || 0 ||colspan=3| ''p'' ||colspan=4| ''s'' ||colspan=5| 16×16→32 multiplication
|-
| 1 || 0 || 1 || 1 || 1 || 0 || 0 || 0 || 0 ||colspan=4| ''w'' ||colspan=3| ''d'' || 0 ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| MUL.UU W''w'',''src'',W''d'' || || || ||align=left| Wd+1:Wd ← Ww × src (unsigned)
|-
| 1 || 0 || 1 || 1 || 1 || 0 || 0 || 0 || 1 ||colspan=4| ''w'' ||colspan=3| ''d'' || 0 ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| MUL.US W''w'',''src'',W''d'' || || || ||align=left| Wd+1:Wd ← Ww × src (src signed)
|-
| 1 || 0 || 1 || 1 || 1 || 0 || 0 || 1 || 0 ||colspan=4| ''w'' ||colspan=3| ''d'' || 0 ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| MUL.SU W''w'',''src'',W''d'' || || || ||align=left| Wd+1:Wd ← Ww × src (Ww signed)
|-
| 1 || 0 || 1 || 1 || 1 || 0 || 0 || 1 || 1 ||colspan=4| ''w'' ||colspan=3| ''d'' || 0 ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| MUL.SS W''w'',''src'',W''d'' || || || ||align=left| Wd+1:Wd ← Ww × src (signed)
|-
|colspan=29|
|-
! 1 || 0 || 1 || 1 || 1 || 0 || 1 ||colspan=2| ''opc'' || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||colspan=5| Program memory access (indirect modes only)
|-
| 1 || 0 || 1 || 1 || 1 || 0 || 1 || 0 || 0 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| TBLRDL[.B] ''src'',''dst'' || || || ||align=left| dst ← ROM[TBLPAG:src] (bits 15:0)
|-
| 1 || 0 || 1 || 1 || 1 || 0 || 1 || 0 || 1 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| TBLRDH[.B] ''src'',''dst'' || || || ||align=left| dst ← ROM[TBLPAG:src] (bits 23:16)
|-
| 1 || 0 || 1 || 1 || 1 || 0 || 1 || 1 || 0 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| TBLWTL[.B] ''src'',''dst'' || || || ||align=left| ROM[TBLPAG:dst] ← src (bits 15:0)
|-
| 1 || 0 || 1 || 1 || 1 || 0 || 1 || 1 || 1 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| TBLWTH[.B] ''src'',''dst'' || || || ||align=left| ROM[TBLPAG:dst] ← src (bits 23:16)
|-
|colspan=29|
|-
| 1 || 0 || 1 || 1 || 1 || 1 || 0 || 0 || 0 || ''B'' || 0 ||colspan=13| ''f'' ||align=left| MUL[.B] ''f'' || || || ||align=left| W3:W2 ← f × W0 (unsigned)
|-style="background:lightgrey;"
| 1 || 0 || 1 || 1 || 1 || 1 || 0 || 0 || 0 || ''B'' || 1 ||colspan=13| — || style="text-align:left;" colspan="5"| (Reserved)
|-style="background:lightgrey;"
| 1 || 0 || 1 || 1 || 1 || 1 || 0 || 0 || 1 ||colspan=15| — ||style="text-align:left;" colspan="5"| (Reserved)
|-style="background:lightgrey;"
| 1 || 0 || 1 || 1 || 1 || 1 || 0 || 1 ||colspan=16| — ||style="text-align:left;" colspan="5"| (Reserved)
|-
| 1 || 0 || 1 || 1 || 1 || 1 || 1 || 0 || 0 || 0 ||colspan=3 style="background:lightgrey;"| —0— ||colspan=3| ''d'' || 0 ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| MOV.D ''src'',W''d'' || || || ||align=left| Load register pair
|-
| 1 || 0 || 1 || 1 || 1 || 1 || 1 || 0 || 1 || 0 ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3 style="background:lightgrey;"| —0— ||colspan=3| ''s'' ||width=10pt| 0 ||align=left| MOV.D W''s'',''dst'' || || || ||align=left| Store register pair
|-style="background:lightgrey;"
| 1 || 0 || 1 || 1 || 1 || 1 || 1 || 1 ||colspan=16| — || style="text-align:left;" colspan="5"| (Reserved)
|-
|colspan=29|
|-
! 1 || 1 || 0 || 0 || 0 ||colspan=3| ''m'' || ''A'' || ''S'' ||colspan=2| ''x'' ||colspan=2| ''y'' ||colspan=4| ''i'' ||colspan=4| ''j'' ||colspan=2| ''a'' ||colspan=5| DSP MAC (dsPIC only)
|-
|colspan=29|
|-
! 1 || 1 || 0 || 0 || 1 ||colspan=19|  ||colspan=5| Other DSP instructions (dsPIC only)
|-
| 1 || 1 || 0 || 0 || 1 || 1 || 1 || 1 || 0 || 0 ||colspan=3 style="background:lightgrey;"| —0— ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| FF1R ''src'',W''d'' || C || || ||align=left| Find first one from right (lsb)
|-
| 1 || 1 || 0 || 0 || 1 || 1 || 1 || 1 || 1 || 0 ||colspan=3 style="background:lightgrey;"| —0— ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| FF1L ''src'',W''d'' || C || || ||align=left| Find first one from left (msb)
|-
|colspan=29|
|-
! 1 || 1 || 0 || 1 || 0 || 0 ||colspan=3| ''opcode'' || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||colspan=5| Shift/rotate general operand
|-
| 1 || 1 || 0 || 1 || 0 || 0 || 0 || 0 || 0 || B ||colspan=3| q ||colspan=4| d ||colspan=3| p ||colspan=4| s ||align=left| SL[.B] ''src'',''dst'' || C || Z || N ||align=left| dst ← src &lt;&lt; 1, shift left (into carry)
|-
| 1 || 1 || 0 || 1 || 0 || 0 || 0 || 1 || 0 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| LSR[.B] ''src'',''dst'' || C || Z || N ||align=left| dst ← src &gt;&gt; 1, logical shift right
|-
| 1 || 1 || 0 || 1 || 0 || 0 || 0 || 1 || 1 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| ASR[.B] ''src'',''dst'' || C || Z || N ||align=left| dst ← src &gt;&gt; 1, arithmetic shift right
|-
| 1 || 1 || 0 || 1 || 0 || 0 || 1 || 0 || 0 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| RLNC[.B] ''src'',''dst'' || || Z || N ||align=left| dst ← src &lt;&lt;&lt; 1, rotate left (no carry)
|-
| 1 || 1 || 0 || 1 || 0 || 0 || 1 || 0 || 1 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| RLC[.B] ''src'',''dst'' || C || Z || N ||align=left| C:dst ← src:C &lt;&lt; 1, rotate left through carry
|-
| 1 || 1 || 0 || 1 || 0 || 0 || 1 || 1 || 0 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| RRNC[.B] ''src'',''dst'' || || Z || N ||align=left| dst ← src &gt;&gt;&gt; 1, rotate right (no carry)
|-
| 1 || 1 || 0 || 1 || 0 || 0 || 1 || 1 || 1 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| RRC[.B] ''src'',''dst'' || C || Z || N ||align=left| dst:C ← C:src &gt;&gt; 1, rotate right through carry
|-
! 1 || 1 || 0 || 1 || 0 || 1 ||colspan=3| ''opcode'' || ''B'' || ''D'' ||colspan=13| ''f'' ||colspan=5| Shift/rotate ''f''
|-
| 1 || 1 || 0 || 1 || 0 || 1 || 0 || 0 || 0 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| SL[.B] ''f''[,WREG] || C || Z || N ||align=left| dest ← f &lt;&lt; 1, shift left (into carry)
|-
| 1 || 1 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| LSR[.B] ''f''[,WREG] || C || Z || N ||align=left| dest ← f &gt;&gt; 1, logical shift right
|-
| 1 || 1 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| ASR[.B] ''f''[,WREG] || C || Z || N ||align=left| dest ← f &gt;&gt; 1, arithmetic shift right
|-
| 1 || 1 || 0 || 1 || 0 || 1 || 1 || 0 || 0 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| RLNC[.B] ''f''[,WREG] || || Z || N ||align=left| dest ← f &lt;&lt;&lt; 1, rotate left (no carry)
|-
| 1 || 1 || 0 || 1 || 0 || 1 || 1 || 0 || 1 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| RLC[.B] ''f''[,WREG] || C || Z || N ||align=left| C:dest ← f:C &lt;&lt; 1, rotate left through carry
|-
| 1 || 1 || 0 || 1 || 0 || 1 || 1 || 1 || 0 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| RRNC[.B] ''f''[,WREG] || || Z || N ||align=left| dest ← f &gt;&gt;&gt; 1, rotate right (no carry)
|-
| 1 || 1 || 0 || 1 || 0 || 1 || 1 || 1 || 1 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| RRC[.B] ''f''[,WREG] || C || Z || N ||align=left| dest:C ← C:f &gt;&gt; 1, rotate right through carry
|-
|colspan=29|
|-
! 1 || 1 || 0 || 1 || 1 || 0 || 0 || 0 || ''U'' ||colspan=4| ''t'' ||colspan=4| ''d'' || ''D'' || 0 || 0 ||colspan=4| ''s'' ||colspan=5| Divide step (prefix with REPEAT #17)
|-
| 1 || 1 || 0 || 1 || 1 || 0 || 0 || 0 || 0 ||colspan=4 style="background:lightgrey;"| —0— ||colspan=4| ''d'' || 0 || 0 || 0 ||colspan=4| ''s'' ||align=left| DIV.S W''d'',W''s'' || C || Z || N ||align=left| W0 ← Wd/Ws, W1 ← remainder
|-
| 1 || 1 || 0 || 1 || 1 || 0 || 0 || 0 || 0 ||colspan=4| ''t'' ||colspan=4| ''d'' || 1 || 0 || 0 ||colspan=4| ''s'' ||align=left| DIV.SD W''d'',W''s'' || C || Z || N ||align=left| W0 ← Wt:Wd/Ws, W1 ← remainder
|-
| 1 || 1 || 0 || 1 || 1 || 0 || 0 || 0 || 1 ||colspan=4 style="background:lightgrey;"| —0— ||colspan=4| ''d'' || 0 || 0 || 0 ||colspan=4| s ||align=left| DIV.U W''d'',W''s'' || C || Z || N ||align=left| W0 ← Wd/Ws, W1 ← remainder
|-
| 1 || 1 || 0 || 1 || 1 || 0 || 0 || 0 || 1 ||colspan=4| ''t'' ||colspan=4| ''d'' || 1 || 0 || 0 ||colspan=4| ''s'' ||align=left| DIV.UD W''d'',W''s'' || C || Z || N ||align=left| W0 ← Wt:Wd/Ws, W1 ← remainder
|-
| 1 || 1 || 0 || 1 || 1 || 0 || 0 || 1 || 0 ||colspan=4| ''t'' ||colspan=4 style="background:lightgrey;"| —0— || 0 || 0 || 0 ||colspan=4| ''s'' ||align=left| DIVF W''t'',W''s'' || C || Z || N ||align=left| W0 ← Wt:0/Ws, W1 ← remainder
|-style="background:lightgrey;"
| 1 || 1 || 0 || 1 || 1 || 0 || 0 || 1 || 1 ||colspan=15| — || style="text-align:left;" colspan="5"| (Reserved)
|-style="background:lightgrey;"
| 1 || 1 || 0 || 1 || 1 || 0 || 1 ||colspan=17| — || style="text-align:left;" colspan="5"| (Reserved)
|-
|colspan=29|
|-
! 1 || 1 || 0 || 1 || 1 || 1 ||colspan=3| ''opcode'' ||colspan=4| ''w'' ||colspan=4| ''d'' || ''i'' || 0 || 0 ||colspan=4| ''s'' ||colspan=5| Shift/rotate multiple
|-
| 1 || 1 || 0 || 1 || 1 || 1 || 0 || 0 || 0 ||colspan=4| ''w'' ||colspan=4| ''d'' || 0 || 0 || 0 ||colspan=4| ''s'' ||align=left| SL W''w'',W''s'',W''d'' || || Z || N ||align=left| Wd ← Ww &lt;&lt; Ws
|-
| 1 || 1 || 0 || 1 || 1 || 1 || 0 || 0 || 0 ||colspan=4| ''w'' ||colspan=4| ''d'' || 1 || 0 || 0 ||colspan=4| ''k'' ||align=left| SL W''v'',#''u4'',W''d'' || || Z || N ||align=left| Wd ← Ww &lt;&lt; k
|-
| 1 || 1 || 0 || 1 || 1 || 1 || 1 || 0 || 0 ||colspan=4| ''w'' ||colspan=4| ''d'' || 0 || 0 || 0 ||colspan=4| ''s'' ||align=left| LSR W''w'',W''s'',W''d'' || || Z || N ||align=left| Wd ← Ww &gt;&gt; Ws, logical shift right
|-
| 1 || 1 || 0 || 1 || 1 || 1 || 1 || 0 || 0 ||colspan=4| ''w'' ||colspan=4| ''d'' || 1 || 0 || 0 ||colspan=4| ''k'' ||align=left| LSR W''v'',#''u4'',W''d'' || || Z || N ||align=left| Wd ← Ww &gt;&gt; k, logical shift right
|-
| 1 || 1 || 0 || 1 || 1 || 1 || 1 || 0 || 1 ||colspan=4| ''w'' ||colspan=4| ''d'' || 0 || 0 || 0 ||colspan=4| ''s'' ||align=left| ASR W''w'',W''s'',W''d'' || || Z || N ||align=left| Wd ← Ww &gt;&gt; Ws, arithmetic shift right
|-
| 1 || 1 || 0 || 1 || 1 || 1 || 1 || 0 || 1 ||colspan=4| ''w'' ||colspan=4| ''d'' || 1 || 0 || 0 ||colspan=4| ''k'' ||align=left| ASR W''v'',#''u4'',W''d'' || || Z || N ||align=left| Wd ← Ww &gt;&gt; k, arithmetic shift right
|-
| 1 || 1 || 0 || 1 || 1 || 1 || 1 || 1 || 0 ||colspan=4 style="background:lightgrey;"| —0—  ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| FBCL ''src'',W''d'' || C || || ||align=left| Find permissible arithmetic normalization shift
|-
|colspan=29|
|-
| 1 || 1 || 1 || 0 || 0 || 0 || 0 || 0 || 0 ||colspan=4 style="background:lightgrey;"| —0—  || ''B'' || 0 || 0 || 0 ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| CP0[.B] ''src'' || C || Z || N ||align=left| Compare with zero, src − 0
|-
| 1 || 1 || 1 || 0 || 0 || 0 || 0 || 1 || 0 ||colspan=4| ''w'' || ''B'' || 0 || 0 || 0 ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| CP[.B] W''w'',''src'' || C || Z || N ||align=left| Compare, Ww − src (Ww + ~src + 1)
|-
| 1 || 1 || 1 || 0 || 0 || 0 || 0 || 1 || 1 ||colspan=4| ''w'' || ''B'' || 0 || 0 || 0 ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| CPB[.B] W''w'',''src'' || C || Z || N ||align=left| Compare with borrow, Ww − src − C̅ (Ww + ~src + C)
|-
| 1 || 1 || 1 || 0 || 0 || 0 || 1 || 0 || 0 || ''B'' || 0 ||colspan=13| ''f'' ||align=left| CP0[.B] ''f'' || C || Z || N ||align=left| Compare with zero, f − 0
|-
| 1 || 1 || 1 || 0 || 0 || 0 || 1 || 1 || 0 || ''B'' || 0 ||colspan=13| ''f'' ||align=left| CP[.B] ''f'' || C || Z || N ||align=left| Compare, f − W0
|-
| 1 || 1 || 1 || 0 || 0 || 0 || 1 || 1 || 1 || ''B'' || 0 ||colspan=13| ''f'' ||align=left| CPB[.B] ''f'' || C || Z || N ||align=left| Compare with borrow, f − W0 − C̅ (f + ~W0 + C)
|-style="background:lightgrey;"
| 1 || 1 || 1 || 0 || 0 || 1 || 0 ||colspan=17| — || colspan="5" style="text-align:left;"| (Reserved)
|-
|colspan=29|
|-
! 1 || 1 || 1 || 0 || 0 || 1 || 1 ||colspan=2| ''opc'' ||colspan=4| ''w'' || ''B'' ||colspan=6| —0— ||colspan=4| ''s'' ||colspan=5| Compare and skip
|-
| 1 || 1 || 1 || 0 || 0 || 1 || 1 || 0 || 0 ||colspan=4| ''w'' || ''B'' ||colspan=6 style="background:lightgrey;"| —0— ||colspan=4| ''s'' ||align=left| CPSGT[.B] W''w'',W''s'' || || || ||align=left| ...if Ww &gt; Ws, signed
|-
| 1 || 1 || 1 || 0 || 0 || 1 || 1 || 0 || 1 ||colspan=4| ''w'' || ''B'' ||colspan=6 style="background:lightgrey;"| —0— ||colspan=4| ''s'' ||align=left| CPSLT[.B] W''w'',W''s'' || || || ||align=left| ...if Ww &lt; Ws, signed
|-
| 1 || 1 || 1 || 0 || 0 || 1 || 1 || 1 || 0 ||colspan=4| ''w'' || ''B'' ||colspan=6 style="background:lightgrey;"| —0— ||colspan=4| ''s'' ||align=left| CPSNE[.B] W''w'',W''s'' || || || ||align=left| ...if Ww ≠ Ws
|-
| 1 || 1 || 1 || 0 || 0 || 1 || 1 || 1 || 1 ||colspan=4| ''w'' || ''B'' ||colspan=6 style="background:lightgrey;"| —0— ||colspan=4| ''s'' ||align=left| CPSNE[.B] W''w'',W''s'' || || || ||align=left| ...if Ww = Ws
|-
|colspan=29|
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 0 || 0 || 0 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| INC[.B] ''src'',''dst'' || C || Z || N ||align=left| dst ← src+1
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 0 || 0 || 1 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| INC2[.B] ''src'',''dst'' || C || Z || N ||align=left| dst ← src+2
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 0 || 1 || 0 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| DEC[.B] ''src'',''dst'' || C || Z || N ||align=left| dst ← src−1
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 0 || 1 || 1 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| DEC2[.B] ''src'',''dst'' || C || Z || N ||align=left| dst ← src−2
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 1 || 0 || 0 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| NEG[.B] ''src'',''dst'' || C || Z || N ||align=left| dst ← ~src+1
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 1 || 0 || 1 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| COM[.B] ''src'',''dst'' || || Z || N ||align=left| dst ← ~src
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 1 || 1 || 0 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=7 style="background:lightgrey;"| —0— ||align=left| CLR[.B] ''dst'' || || || ||align=left| dst ← 0
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 1 || 1 || 1 || ''B'' ||colspan=3| ''q'' ||colspan=4| ''d'' ||colspan=7 style="background:lightgrey;"| —0— ||align=left| SETM[.B] ''dst'' || || || ||align=left| dst ← ~0
|-
| 1 || 1 || 1 || 0 || 1 || 1 || 0 || 0 || 0 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| INC[.B] ''f''[,WREG] || C || Z || N ||align=left| dest ← f+1
|-
| 1 || 1 || 1 || 0 || 1 || 1 || 0 || 0 || 1 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| INC2[.B] ''f''[,WREG] || C || Z || N ||align=left| dest ← f+2
|-
| 1 || 1 || 1 || 0 || 1 || 1 || 0 || 1 || 0 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| DEC[.B] ''f''[,WREG] || C || Z || N ||align=left| dest ← f−1
|-
| 1 || 1 || 1 || 0 || 1 || 1 || 0 || 1 || 1 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| DEC[.B] ''f''[,WREG] || C || Z || N ||align=left| dest ← f−2
|-
| 1 || 1 || 1 || 0 || 1 || 1 || 1 || 0 || 0 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| NEG[.B] ''f''[,WREG] || C || Z || N ||align=left| dest ← ~f+1
|-
| 1 || 1 || 1 || 0 || 1 || 1 || 1 || 0 || 1 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| COM[.B] ''f''[,WREG] || || Z || N ||align=left| dest ← ~f
|-
| 1 || 1 || 1 || 0 || 1 || 1 || 1 || 1 || 0 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| CLR[.B] ''f''[,WREG] || || || ||align=left| dest ← 0
|-
| 1 || 1 || 1 || 0 || 1 || 1 || 1 || 1 || 1 || ''B'' || ''D'' ||colspan=13| ''f'' ||align=left| SETM[.B] ''f''[,WREG] || || || ||align=left| dest ← ~0
|-
|colspan=29|
|-
! 1 || 1 || 1 || 1 || 0 || 0 ||colspan=2| ''m'' || ''A'' || 1 ||colspan=2| ''x'' ||colspan=2| ''y'' ||colspan=4| ''i'' ||colspan=4| ''j'' ||colspan=2| opc ||colspan=5| DSP MPY/MAC/ED/EDAC (dsPIC only)
|-style="background:lightgrey;"
| 1 || 1 || 1 || 1 || 0 || 1 ||colspan=18| — || colspan="5" style="text-align:left;"| (Reserved)
|-
|colspan=29|
|-
| 1 || 1 || 1 || 1 || 1 || 0 || 0 || 0 ||colspan=15| ''f'' || 0 ||align=left| PUSH ''f'' || || || ||align=left| Push f on top of stack
|-
| 1 || 1 || 1 || 1 || 1 || 0 || 0 || 1 ||colspan=15| ''f'' || 0 ||align=left| POP ''f'' || || || ||align=left| Pop f from top of stack
|-
| 1 || 1 || 1 || 1 || 1 || 0 || 1 || 0 || 0 || 0 ||colspan=14| ''k'' ||align=left| LNK #''u14'' || || || ||align=left| Push W14, W14 ← W15, W15 += k
|-
| 1 || 1 || 1 || 1 || 1 || 0 || 1 || 0 || 1 || 0 ||colspan=14 style="background:lightgrey;"| —0— ||align=left| ULNK || || || ||align=left| W15 ← W14, pop W14
|-
| 1 || 1 || 1 || 1 || 1 || 0 || 1 || 1 || 0 || 0 ||colspan=3| 000 ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| SE ''src'',''dst'' || C || Z || N ||align=left| dst ← sign_extend(src), copy bit 7 to bits 15:8
|-
| 1 || 1 || 1 || 1 || 1 || 0 || 1 || 1 || 1 || 0 ||colspan=3| 000 ||colspan=4| ''d'' ||colspan=3| ''p'' ||colspan=4| ''s'' ||align=left| ZE ''src'',''dst'' || 1 || Z || 0 ||align=left| dst ← zero_extend(src), clear bits 15:8
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 0 || 0 || 0 || 0 ||colspan=14| ''k'' ||align=left| DISI #''u14'' || || || ||align=left| Disable interrupt for ''k''+1 cycles
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 0 || 1 || 0 || 0 ||colspan=3| 000 ||colspan=4| ''d'' ||colspan=3| 000 ||colspan=4| ''s'' ||align=left| EXCH W''s'',W''d'' || || || ||align=left| Swap contents of registers Ws, Wd
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 0 || 1 || 0 || 1 ||colspan=3| 000 ||colspan=4| 0000 ||colspan=3| 000 ||colspan=4| ''s'' ||align=left| DAW.B W''s'' || C || || ||align=left| Decimal adjust based on C, DC
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 0 || 1 || 1 || ''B'' ||colspan=3| 000 ||colspan=4| 0000 ||colspan=3| 000 ||colspan=4| ''s'' ||align=left| SWAP[.B] W''s'' || || || ||align=left| Swap halves of Ws
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 0 || 0 || 0 ||colspan=14 style="background:lightgrey;"| —0— ||align=left| RESET || || || ||align=left| Software reset
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 0 || 0 || 1 || 0 ||colspan=12 style="background:lightgrey;"| —0— || ''k'' ||align=left| PWRSAV #''u1'' || || || ||align=left| Go into sleep or idle mode
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 0 || 0 || 1 || 1 ||colspan=13 style="background:lightgrey;"| —0— ||align=left| CLRWDT || || || ||align=left| Clear watchdog timer
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 0 || 1 || 0 || 0 ||colspan=13 style="background:lightgrey;"| —0— ||align=left| POP.S || || || ||align=left| Pop shadow registers (W0–3, part of PSR)
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 0 || 1 || 0 || 1 ||colspan=13 style="background:lightgrey;"| —0— ||align=left| PUSH.S || || || ||align=left| Push shadow registers (W0–3, part of PSR)
|-style="background:lightgrey;"
| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 0 || 1 || 1 ||colspan=14| — || style="text-align:left;" colspan="5"| (Reserved)
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 1 ||colspan=16 style="background:lightgrey;"| — ||align=left| NOPR || || || ||align=left| No operation (version #2)
|}

==References==
<references/>

{{Microchip Technology}}

[[Category:Microcontrollers]]
[[Category:Instruction set listings]]