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{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
| image = KL Intel i286.jpg
| image = KL Intel i286.jpg
| caption = An 8MHz Intel 80286 Microprocessor
| caption = An Intel A80286-8 processor with a gray ceramic heat spreader
| manuf1 = [[Intel]]<br>[[IBM]]<br>[[AMD]]<br>[[Harris]] ([[Intersil]])<br>[[Siemens AG]]<br>[[Fujitsu]]
| manuf1 = [[Intel]], [[IBM]], [[AMD]], [[Harris Corporation|Harris]] ([[Intersil]]), [[Siemens]], [[Fujitsu]]
| produced-start = February 1982
| model = 80286 Series
| produced-end = 1991<ref>{{cite web |url=https://www.cpushack.com/life-cycle-of-cpu.html |title=CPU History - The CPU Museum - Life Cycle of the CPU |website=cpushack.com |access-date=September 6, 2021 |archive-date=July 20, 2021 |archive-url=https://web.archive.org/web/20210720004826/https://www.cpushack.com/life-cycle-of-cpu.html |url-status=live }}</ref>
| produced-start = 1982
| slowest = 4 | slow-unit = MHz
| produced-end = early 1990s
| slowest = 6 | slow-unit = MHz (4 MHz for a short time)
| fastest = 25 | fast-unit = MHz
| fastest = 25 | fast-unit = MHz
| fsb = 6 MHz to 25 MHz
| fsb-slowest = 4 | fsb-slow-unit = MHz
| fsb-fastest = 25 | fsb-fast-unit = MHz
| transistors-nostep = 134K 1.5[[Micrometre| µm]]
| transistors = 120,000<ref>Ormsby, John, "Chip Design: A Race Worth Winning", Intel Corporation, Microcomputer Solutions, July/August 1988, page 18</ref> or 134,000, 1.5[[Micrometre|µm]]
| arch = [[x86-16]] (with [[Memory management unit|MMU]])
| arch = [[x86-16]] (with [[memory management unit|MMU]])
| pack1 = 68-pin [[Plastic leaded chip carrier|PLCC]]<br>100-pin [[PQFP]]<br>68-pin [[Pin grid array|PGA]]
| pack1 = 68-pin [[plastic leaded chip carrier|PLCC]]
| predecessor = [[Intel 80186]]
| pack2 = 68-pin [[leadless chip carrier|LCC]]
| pack3 = 68-pin [[pin grid array|PGA]]
| pack4 = 100-pin [[PQFP]] (engineering sample only)
| predecessor = [[8086]], [[8088]] (while [[Intel 80186|80186]] was contemporary)
| successor = [[Intel 80386]]
| successor = [[Intel 80386]]
| co-processor = [[Intel 80287]]
| co-processor = [[Intel 80287]]
| data-width = 16 bits
| address-width = 24 bits
| size-from = [[1.5 µm process|1.5&nbsp;µm]]<ref>{{cite web|url=https://en.wikichip.org/wiki/1.5_%C2%B5m_lithography_process|title=1.5 µm lithography process - WikiChip|website=en.wikichip.org|access-date=January 21, 2019|archive-date=September 9, 2018|archive-url=https://web.archive.org/web/20180909090836/https://en.wikichip.org/wiki/1.5_%C2%B5m_lithography_process|url-status=live}}</ref>
| sock1 = PGA68
| sock2 = PLCC-68
| sock3 = LCC-68
| support status = Unsupported
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
| name = P5
| name = Pentium (i586)
| image =
| image = Intel Pentium MMX Processor Logo.svg
| image_size = 150px
| image_size = 150px
| model = Pentium Series
| model = Pentium series
| model1 = Pentium OverDrive Series
| model1 = Pentium OverDrive series
| model2 = Pentium MMX Series
| model2 = Pentium MMX series
| created = March 22, 1993
| produced-start = March 22, 1993
| produced-end = July 15, 1999<ref name="discontinued">{{cite web|url=http://developer.intel.com/design/pcn/Processors/D0000777.pdf|title=Product Change Notification #777|date=February 9, 1999|publisher=Intel|archive-url=https://web.archive.org/web/20000127045353/http://developer.intel.com/design/pcn/Processors/D0000777.pdf|archive-date=January 27, 2000|url-status=dead|access-date=October 14, 2019}}</ref>{{better source needed|date=October 2019}}<!-- Note that this is for the P55C model, it's unclear if Tillamook was discontinued here as well or not. -->
| cores-nothread = 1
| cores = 1
| transistors-nostep = 3.1M 0.8 [[800 nanometer|µm]]
| transistors-nostep1 = 3.2M 0.6 [[600 nanometer|µm]]
| transistors = 3.1M 0.8 [[800 nanometer|μm]] (P5)
| transistors-nostep2 = 3.3M 350 [[350 nanometer|nm]]
| transistors1 = 3.2M 0.6 [[600 nanometer|μm]] (P54C)
| transistors-nostep3 = 4.5M 350 [[350 nanometer|nm]]
| transistors2 = 3.3M 350 [[350 nanometer|nm]] (P54CS)
| transistors3 = 4.5M 350 [[350 nanometer|nm]] (P55C)
| clock = 60 MHz to 300 MHz
| clock = 60–300 MHz
| l1cache = 16 KB to 32 KB
| l1cache = 16–32 KiB
| fsb = 50 MHz to 66 MHz
| fsb = 50–66 MHz
| arch1 = [[P5 (microarchitecture)|P5]] [[x86]] ([[IA-32]])
| arch = [[IA-32]]
| instructions = [[MMX (instruction set)|MMX]]
| microarch = P5
| extensions = [[MMX (instruction set)|MMX]]
| sock1 = [[Socket 4]]
| sock1 = [[Socket 4]]
| sock2 = [[Socket 5]]
| sock2 = [[Socket 5]]
| sock3 = [[Socket 7]]
| sock3 = [[Socket 7]]
| predecessor = [[Intel 80486 (microarchitecture)|Intel 80486]]
| predecessor = [[i486]]
| successor = [[P6 (microarchitecture)|P6]]
| successor = [[P6 (microarchitecture)|P6]], [[Pentium II]]
| support status = Unsupported
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
| name = P6
| name = P6
| image = Intel@250nm@P6@Deschutes@Pentium II@flipchip PB 713539-001 DSCx1 polysilicon microscope stitched@5x (38025161182).jpg
| image =
| caption = Die shot of [[Pentium II|Deschutes]] core
| image_size = 150px
| image_size =
| created = November 1, 1995
| created = {{start date and age|November 1, 1995}}
| model = Celeron Series
| slowest = 150<ref>{{cite web |title=Pentium® Pro Processor at 150 MHz, 166 MHz, 180 MHz and 200 MHz |url=https://www.dexsilicium.com/Intel_PentiumPro.pdf |publisher=Intel Corporation |page=1 |date=November 1995 |archive-url=https://web.archive.org/web/20160412090026/https://www.dexsilicium.com/Intel_PentiumPro.pdf |archive-date=April 2, 2016 |url-status=dead}}</ref>
| model1 = Pentium II Series
| fastest = 1.40
| model2 = Pentium III Series
| slow-unit = MHz
| model3 = Pentium Pro Series
| fsb-slowest = 66
| model4 = Pentium II Xeon Series
| fsb-fastest = 133
| model5 = Pentium III Xeon Series
| cores-nothread = 1
| fsb-slow-unit = MHz
| fsb-fast-unit = MHz
| transistors = 7.5M [[350 nanometer|350 nm]]
| l1cache = Pentium Pro: 16 KB (8 KB I cache + 8 KB D cache)<br /> Pentium II/III: 32 KB (16 KB I cache + 16 KB D cache)
| transistors1 = 7.5M [[250 nanometer|250 nm]] (B0, B1)
| l2cache = 128 KB to 512 KB<br />256 KB to 2048 KB (Xeon)
| transistors2 = 9.5M [[250 nanometer|250 nm]] (B0, C0)
| arch = [[x86]]
| transistors3 = 19M [[250 nanometer|250 nm]] (B0)
| extensions = [[MMX (instruction set)|MMX]] (Pentium II/III)<br />[[Streaming SIMD Extensions|SSE]] (Pentium III)
| transistors4 = 28M [[180 nanometer|180 nm]] (A1, A2, B0, C0, D0)
| microarch = P6
| transistors5 = 44M [[130 nanometer|130 nm]] (A1, B1, C1, D0)
| transistors1 = 5.5M [[600 nm process|500 nm]]
| clock = 233 MHz to 1.40 GHz
| transistors2 = 7.5M [[350 nm process|350 nm]]
| l1cache = 32 KB
| transistors3 = 7.5M [[250 nm process|250 nm]] (B0, B1)
| l2cache = 128 KB to 512 KB<br>256 KB to 2048 KB (Xeon)
| transistors4 = 9.5M [[250 nm process|250 nm]] (B0, C0)
| fsb = 66 MHz to 133 MHz
| transistors5 = 19M [[250 nm process|250 nm]] (B0)
| arch1 = [[P6 (microarchitecture)|P6]] [[x86]]
| transistors6 = 28M [[180 nm process|180 nm]] (A1, A2, B0, C0, D0)
| instructions = [[MMX (instruction set)|MMX]]
| transistors7 = 44M [[130 nm process|130 nm]] (A1, B1, C1, D0)
| extensions = [[Streaming SIMD Extensions|SSE]]
| numcores = 1
| sock1 = [[Socket 370]]
| sock2 = [[Socket 479]]
| sock1 = [[Socket 8]]
| predecessor = [[P5 (microarchitecture)|P5]]
| sock2 = [[Slot 1]]
| sock3 = [[Socket 370]]
| variant = [[Pentium M (microarchitecture)|Pentium M]]
| sock4 = [[Socket 479]]
| variant1 = [[Enhanced Pentium M (microarchitecture)|Enhanced Pentium M]]
| model = Celeron Series
| successor = [[NetBurst (microarchitecture)|NetBurst]]
| model1 = Pentium II Series
| model2 = Pentium III Series
| model3 = Pentium Pro Series
| model4 = Pentium II Xeon Series
| model5 = Pentium III Xeon Series
| predecessor = [[P5 (microarchitecture)|P5]]
| variant = Pentium M
| variant1 = Enhanced Pentium M
| successor = [[NetBurst (microarchitecture)|NetBurst]], [[Pentium M]]
| support status = Unsupported
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
| name = P6 Pentium M
| name = P6 Pentium M
| image =
| image = Pentium M.jpg
| image_size = 150px
| image_size = 150px
| created = 2004
| created = March 12, 2003
| model = A100 Series
| model = A100 Series
| model1 = EP80579 Series
| model1 = EP80579 Series
| model2 = Celeron M Series
| model2 = Celeron M Series
| model3 = Pentium M Series
| model3 = Pentium M Series
| cores-nothread = 1
| cores = 1
| transistors = 77M [[130 nanometer|130 nm]] (B1, B2)
| transistors = 77M [[130 nanometer|130 nm]] (B1, B2)
| transistors1 = 144M [[90 nanometer|90 nm]] (B0, C0)
| transistors1 = 144M [[90 nanometer|90 nm]] (B0, C0)
| transistors2 = 151M [[65 nanometer|65 nm]] (C0, D0)
| transistors2 = 151M [[65 nanometer|65 nm]] (C0, D0)
| clock = 600 MHz to 2.26 GHz
| clock = 600 MHz to 2.26 GHz
| l1cache = 32KB
| l1cache = 64KB (32 KB I Cache + 32 KB D cache)
| l2cache = 512 KB to 2048 KB
| l2cache = 512 KB to 2048 KB
| fsb = 400 MHz to 533 MHz
| fsb = 400 MT/s to 533 MT/s
| arch1 = [[P6 (microarchitecture)|P6]] [[x86]]
| arch = [[x86]]
| instructions = [[MMX (instruction set)|MMX]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]]
| microarch = P6
| extensions = [[Streaming SIMD Extensions|SSE]], [[SSE2]]
| socket = [[Socket M]]
| socket = [[Socket M]]
| predecessor = [[P5 (microarchitecture)|P5]]
| predecessor = [[NetBurst (microarchitecture)|NetBurst]]
| successor = [[Enhanced Pentium M (microarchitecture)|Enhanced Pentium M]]
| successor = [[Enhanced Pentium M (microarchitecture)|Enhanced Pentium M]]
| support status = Unsupported
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
Line 130: Line 154:
| model3 = Core Duo Series
| model3 = Core Duo Series
| model4 = Xeon LV Series
| model4 = Xeon LV Series
| cores-nothread = 1-2
| cores = 1-2
| transistors = 151M [[65 nanometer|65 nm]] (C0, D0)
| transistors = 151M [[65 nanometer|65 nm]] (C0, D0)
| clock = 1.06 GHz to 2.33 GHz
| clock = 1.06 GHz to 2.33 GHz
| l1cache = 32 KB
| l1cache = 64 KB
| l2cache = 1 MB to 2 MB<br>2 MB (Xeon)
| l2cache = 1 MB to 2 MB<br />2 MB (Xeon)
| fsb = 533 MHz to 667 MHz
| fsb = 533 MT/s to 667 MT/s
| arch1 = [[P6 (microarchitecture)|P6]] [[x86]]
| arch = [[x86]]
| instructions = [[MMX (instruction set)|MMX]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]]
| microarch = P6
| extensions = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]]
| socket = [[Socket M]]
| socket = [[Socket M]]
| predecessor = [[Pentium M (microarchitecture)|Pentium M]]
| predecessor = [[Pentium M (microarchitecture)|Pentium M]]
| successor = [[Intel Core (microarchitecture)|Intel Core]]
| successor = [[Intel Core (microarchitecture)|Intel Core]]
| support status = Unsupported
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
| name = NetBurst
| name = NetBurst
| image =
| image =
| image_size = 150px
| image_size =
| created = November 20, 2000
| created = {{start date and age|November 20, 2000}}
| model = Celeron Series
| model = Celeron Series
| model1 = Celeron D Series
| model1 = Celeron D Series
Line 153: Line 178:
| model3 = Pentium D Series
| model3 = Pentium D Series
| model4 = Xeon Series
| model4 = Xeon Series
| cores = 1-2 (2-4)
| cores = 1-2 (2-4 threads with HT)
| cores1 = 2-6 (2-6) (Xeon)
| cores1 =
| transistors = 42M [[180 nanometer|180 nm]] (B2, C1, D0, E0)
| transistors = 42M [[180 nanometer|180 nm]] (B2, C1, D0, E0)
| transistors1 = 55M [[130 nanometer|130 nm]] (B0, C1, D1, M0)
| transistors1 = 55M [[130 nanometer|130 nm]] (B0, C1, D1, M0)
Line 160: Line 185:
| transistors3 = 169M [[90 nanometer|90 nm]] (M0, N0, R0)
| transistors3 = 169M [[90 nanometer|90 nm]] (M0, N0, R0)
| transistors4 = 230M [[90 nanometer|90 nm]] (A0, B0)
| transistors4 = 230M [[90 nanometer|90 nm]] (A0, B0)
| transistors5 = 188M [[65 nanometer|65 nm]] (B1, C1, D0}
| transistors5 = 188M [[65 nanometer|65 nm]] (B1, C1, D0)
| transistors6 = 376M [[65 nanometer|65 nm]] (B1, C1, D0)
| transistors6 = 376M [[65 nanometer|65 nm]] (B1, C1, D0)
| transistors7 = 1,328M [[65 nanometer|65 nm]] (B0)
| transistors7 = 1,328M [[65 nanometer|65 nm]] (B0)
| clock = 267 MHz to 3.73 GHz
| clock = 1.3&nbsp;GHz to 3.8&nbsp;GHz
| l1cache = 8 KB to 16 KB per core
| l1cache = 8 KB to 16 KB per core
| l2cache = 128 KB to 2048 KB<br>256 KB to 2048 KB (Xeon)
| l2cache = 128 KB to 2048 KB
| l3cache = 4 MB to 16 MB shared
| l3cache = 4 MB to 16 MB shared
| fsb = 400 MT/s to 1066 MT/s
| fsb = 400 MT/s to 1066 MT/s
| arch1 = [[NetBurst (microarchitecture)|NetBurst]] [[x86]]
| microarch = NetBurst
| arch = [[x86]] ([[IA-32]]), [[x86-64]] (some)
| instructions = [[MMX (instruction set)|MMX]]
| extensions = [[x86-64]], [[Intel 64]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]]&nbsp;(some)
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]]
| sock1 = [[Socket 423]]
| sock1 = [[Socket 423]]
| sock2 = [[Socket 478]]
| sock2 = [[Socket 478]]
| sock3 = [[Socket 771]]
| sock3 = [[Socket 603]]
| sock4 = [[Socket 775]]
| sock4 = [[Socket 604]]
| sock5 = [[LGA 771]]
| sock6 = [[LGA 775]]
| predecessor = [[P6 (microarchitecture)|P6]]
| predecessor = [[P6 (microarchitecture)|P6]]
| successor = [[Intel Core (microarchitecture)|Intel Core]]
| successor = [[Intel Core (microarchitecture)|Intel Core]]<br/>[[IA-64]]
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
| name = Intel Core
| name = Intel Core
| image =
| image =
| image_size = 150px
| produced-start =
| created = 2006
| produced-end =
| created = {{start date and age|June 26, 2006}}&nbsp;(Xeon)<br/>{{start date and age|July 27, 2006}}&nbsp;(Core&nbsp;2)
| model = Celeron Series
<!-- | model = Celeron Series
| model1 = Pentium Series
| model1 = Pentium Series
| model2 = Pentium Dual-Core Series
| model2 = Pentium Dual-Core Series
| model3 = Core 2 Solo Series
| model3 = Core 2 Solo series
| model4 = Core 2 Duo Series
| model4 = Core 2 Duo series
| model5 = Core 2 Quad Series
| model5 = Core 2 Quad series
| model6 = Core 2 Extreme Series
| model6 = Core 2 Extreme Series
| model7 = Xeon Series
| model7 = Xeon Series -->
| model = P6 family ([[Celeron]], [[Pentium]], Pentium Dual-Core, Core 2 range, Xeon)
| cores = 1-4 (1-4)
| cores1 = 2-6 (2-6) (Xeon)
| numcores = 1–4 (2-6 Xeon)
| transistors = 105M [[65 nanometer|65 nm]] (A1, M0)
| transistors = 105M to 582M ([[65 nanometer|65 nm]])<br/>228M to 1900M ([[45 nm]])
<!-- (A1, M0)
| transistors1 = 167M [[65 nanometer|65 nm]] (G0)
| transistors1 = 167M [[65 nanometer|65 nm]] (G0)
| transistors2 = 291M [[65 nanometer|65 nm]] (B2, E1, G0, L2)
| transistors2 = 291M [[65 nanometer|65 nm]] (B2, E1, G0, L2)
| transistors3 = 582M [[65 nanometer|65 nm]] (B3, G0)
| transistors3 = 582M [[65 nanometer|65 nm]] (B3, G0) -->
| clock = 1.06 GHz to 3.33 GHz
| slowest = 933
| fastest = 3.5
| slow-unit = MHz
| fast-unit = GHz
| size-from = [[65 nanometer|65 nm]]
| size-to = [[45 nanometer|45 nm]]
| l1cache = 64 KB per core
| l1cache = 64 KB per core
| l2cache = 1 MB to 8 MB unified
| l2cache = 0.5 to 6 MB per two cores
| l3cache = 8 MB to 16 MB shared (Xeon)
| l3cache = 8 MB to 16 MB shared (Xeon&nbsp;7400)
| fsb = 533 MT/s to 1600 MT/s
| fsb-slowest = 533
| fsb-fastest = 1600
| arch1 = [[Intel Core]] [[x86]]
| instructions = [[MMX (instruction set)|MMX]]
| fsb-slow-unit = [[Transfer (computing)|MT/s]]
| fsb-fast-unit = MT/s
| extensions = [[x86-64]], [[Intel 64]]
| arch = [[x86-64]]
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]]
| microarch = Core
| instructions = [[x86]], [[x86-64]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]] (45nm Core 2 only), [[VT-x]] (some)
| sock1 = [[Socket M]] (µPGA 478)
| sock1 = [[Socket M]] (µPGA 478)
| sock2 = [[Socket P]] (µPGA 478)
| sock2 = [[Socket P]] (µPGA 478)
| sock3 = [[Socket T]] ([[LGA 775]])
| sock3 = [[Socket T]] ([[LGA 775]])
| sock4 = [[Micro-FCBGA|FCBGA]] (µBGA 479)
| sock4 = [[Socket J]] ([[LGA 771]])
| sock5 = [[Micro-FCBGA|FCBGA]] (µBGA 965)
| sock5 = [[Socket 604]]
| sock6 = [[Micro-FCBGA|FCBGA]] (µBGA 479)
| predecessor = [[NetBurst (microarchitecture)|NetBurst]]
| sock7 = [[Micro-FCBGA|FCBGA]] (µBGA 965)
| successor = [[Penryn (microarchitecture)|Penryn (tick)]]<br>[[Nehalem (microarchitecture)|Nehalem (tock)]]
| predecessor = [[NetBurst (microarchitecture)|NetBurst]]<br/>[[Enhanced Pentium M (microarchitecture)|Enhanced Pentium M]] ([[P6 (microarchitecture)|P6]])
| successor = [[Penryn (microarchitecture)|Penryn (tick)]]<br/>(a version of Core)<br/>[[Nehalem (microarchitecture)|Nehalem (tock)]]
| support status = Unsupported
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
| name = Penryn
| name = Penryn
| image =
| image_size = 150px
| image_size = 150px
| created = 2007-2008
| created = {{start date and age|November 2007}}
| model = Celeron Series
| model = P6 Family (Celeron, Pentium, Pentium Dual-Core, Core 2 range, Xeon)
<!-- Celeron Series
| model1 = Pentium Series
| model1 = Pentium Series
| model2 = Pentium Dual-Core Series
| model2 = Pentium Dual-Core Series
Line 227: Line 266:
| model5 = Core 2 Quad Series
| model5 = Core 2 Quad Series
| model6 = Core 2 Extreme Series
| model6 = Core 2 Extreme Series
| model7 = Xeon Series
| model7 = Xeon Series -->
| cores = 1-4 (1-4)
| cores = 1-4 (2-6 Xeon)
| cores2 = 2-6 (2-6) (Xeon)
<!-- | cores2 = 2-6 (2-6) (Xeon) -->
| transistors = 228M [[45 nanometer|45 nm]] (R0)
| transistors = 228M to 820M [[45 nanometer|45 nm]]
<!-- (R0)
| transistors1 = 410M [[45 nanometer|45 nm]] (C0, E0)
| transistors1 = 410M [[45 nanometer|45 nm]] (C0, E0)
| transistors2 = 456M [[45 nanometer|45 nm]] (R0, M0, M1)
| transistors2 = 456M [[45 nanometer|45 nm]] (R0, M0, M1)
| transistors3 = 820M [[45 nanometer|45 nm]] (C0, C1, E0)
| transistors3 = 820M [[45 nanometer|45 nm]] (C0, C1, E0) -->
| clock = 1.06 GHz to 3.33 GHz
| clock = 1.06 GHz to 3.33 GHz
| l1cache = 64 KB per core
| l1cache = 64 KB per core
| l2cache = 3 MB to 12 MB unified
| l2cache = 1 MB to 12 MB unified
| l3cache = 8 MB to 16 MB shared (Xeon)
| l3cache = 8 MB to 16 MB shared (Xeon)
| fsb = 533 MT/s to 1600 MT/s
| fsb = 533 MT/s to 1600 MT/s
| arch1 = [[Intel Core]] [[x86]]
| arch = [[x86-64]]
| instructions = [[MMX (instruction set)|MMX]]
| microarch = [[Intel Core (microarchitecture)|Core]]
| extensions = [[x86-64]], [[Intel 64]]
| instructions = [[x86]], [[x86-64]]
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]]
| extensions2 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| extensions1 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| sock1 = [[Socket M]] (µPGA 478)
| sock1 = [[Socket M]] (µPGA 478)
| sock2 = [[Socket P]] (µPGA 478)
| sock2 = [[Socket P]] (µPGA 478)
| sock3 = [[Socket T]] ([[LGA 775]])
| sock3 = [[Socket T]] ([[LGA 775]])
| sock4 = [[Micro-FCBGA|FCBGA]] (µBGA 479)
| sock4 = [[Micro-FCBGA|FCBGA]] (μBGA 479)
| sock5 = [[Micro-FCBGA|FCBGA]] (µBGA 965)
| sock5 = [[Micro-FCBGA|FCBGA]] (μBGA 965)
| predecessor = [[Intel Core (microarchitecture)|Intel Core]]
| predecessor = [[Core (microarchitecture)|Core]]
| successor = [[Nehalem (microarchitecture)|Nehalem]]
| successor = [[Nehalem (microarchitecture)|Nehalem]]
|image=
| support status = Unsupported
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
| name = Nehalem
| name = Nehalem
| image =
| image =
| caption = Logo for Core i7 Bloomfield processors
| image_size = 150px
| image_size = 150px
| created = November 2008
| created = {{start date and age|November 11, 2008}}
| model = Celeron Series
| model = Pentium, Core, Core i''n'' and Xeon Series
| model1 = Pentium Series
<!-- | model1 = Pentium Series
| model2 = Core i3 Series
| model2 = Core i5 7xx Series
| model3 = Core i5 Series
| model3 = Core i7 8xx/9xx Series
| model4 = Core i7 Series
| model4 = Core i7 9xx Extreme Series
| model5 = Core i7 Extreme Series
| model5 = Xeon Series -->
| model6 = Xeon Series
| cores = 2-6 (4-8 Xeon)
| cores = 2-6 (2-12)
<!-- (2-12)
| cores1 = 6 (12) (Extreme)
| cores1 = 6 (12) (Extreme)
| cores2 = 4-8 (4-16) (Xeon)
| cores2 = 4-8 (4-16) (Xeon) -->
| transistors = 731M [[45 nanometer|45 nm ]] (C0, D0)
| transistors = 731M to 2300M [[45 nanometer|45 nm]]
<!-- (C0, D0)
| transistors1 = 774M [[45 nanometer|45 nm]] (B0, B1)
| transistors1 = 774M [[45 nanometer|45 nm]] (B0, B1)
| transistors2 = 2,300M [[45 nanometer|45 nm]] (D0)
| transistors2 = 2,300M [[45 nanometer|45 nm]] (D0) -->
| clock = 1.06 GHz to 3.33 GHz
| clock = 1.06 GHz to 3.33 GHz
| l1cache = 64KB per core
| l1cache = 64 KB per core
| l2cache = 256KB per core
| l2cache = 256 KB per core
| l3cache = 4MB to 12MB shared
| l3cache = 2 MB to 24 MB shared
| dmi = 2.50GT/s
| dmi-slowest = 2.50
| qpi = 4.80GT/s to 6.40GT/s
| qpi-slowest = 4.80
| qpi-fastest = 6.40
| gpu =
| gpu =
| arch = [[x86-64]]
| arch1 = [[Nehalem (microarchitecture)|Nehalem]] [[x86]]
| microarch = Nehalem
| extensions = [[x86-64]], [[Intel 64]]
| instructions = [[MMX (instruction set)|MMX]]
| extensions1 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| instructions = [[x86]], [[x86-64]]
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| extensions2 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| sock1 = [[LGA 1156]]
| sock1 = [[LGA 1156]]
| sock2 = [[LGA 1366]]
| sock2 = [[LGA 1366]]
| sock3 = [[LGA 1567]]
| sock3 = [[LGA 1567]]
| sock4 = [[µPGA 988]]
| sock4 = [[Socket G1|µPGA 988]]
| predecessor = [[Intel Core (microarchitecture)|Intel Core (tock)]]<br>[[Penryn (microarchitecture)|Penryn (tick)]]
| predecessor = [[Core (microarchitecture)|Core (tock)]]<br />[[Penryn (microarchitecture)|Penryn (tick)]]
| successor = [[Westmere (microarchitecture)|Westmere (tick)]]<br>[[Sandy Bridge (microarchitecture)|Sandy Bridge (tock)]]
| successor = [[Westmere (microarchitecture)|Westmere (tick)]]<br />[[Sandy Bridge|Sandy Bridge (tock)]]
|size-from=[[45 nm]]
| support status = Unsupported
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
Line 293: Line 340:
| image =
| image =
| image_size = 150px
| image_size = 150px
| created = January 7, 2010
| created = {{start date and age|January 7, 2010}}
| model = Celeron Series
| model = Core i''n'', Xeon
| cores = 2-6 (4-10 Xeon)
| model1 = Pentium Series
<!-- | cores1 = 6 (12) (Extreme)
| model2 = Core i3 Series
| model3 = Core i5 Series
| cores2 = 4-10 (4-20) (Xeon) -->
| transistors = 382M to 2600M [[32 nanometer|32nm]]
| model4 = Core i7 Series
<!-- (C2)
| model5 = Core i7 Extreme Series
| model6 = Xeon Series
| cores = 2-6 (2-12)
| cores1 = 6 (12) (Extreme)
| cores2 = 4-10 (4-20) (Xeon)
| transistors = 382M [[32 nanometer|32nm]] (C2)
| transistors1 = 1,170M [[32 nanometer|32nm]] (B1)
| transistors1 = 1,170M [[32 nanometer|32nm]] (B1)
| transistors2 = 2,600M [[32 nanometer|32nm]] (A2)
| transistors2 = 2,600M [[32 nanometer|32nm]] (A2) -->
| clock = 1.06 GHz to 3.46 GHz
| clock = 1.06 GHz to 3.46 GHz
| l1cache = 64KB per core
| l1cache = 64 KB per core
| l2cache = 256KB per core
| l2cache = 256 KB per core
| l3cache = 4MB to 30MB shared
| l3cache = 2 MB to 30 MB shared
| dmi = 2.50GT/s
| dmi-slowest = 2.50
| qpi = 4.80GT/s to 6.40GT/s
| qpi-slowest = 4.80
| qpi-fastest = 6.40
| gpu = 533 MHz to 900 MHz<br>177M [[45 nanometer|45nm]] (K0)
| gpu = 533 MHz to 900 MHz<br>177M [[45 nanometer|45nm]] (K0)
| arch = [[x86-64]]
| arch1 = [[Nehalem (microarchitecture)|Nehalem]] [[x86]]
| microarch = [[Nehalem (microarchitecture)|Nehalem]]
| instructions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]]
| extensions = [[x86-64]], [[Intel 64]]
| instructions = [[IA-32]], [[x86-64]]
| extensions = [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]]
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| extensions1 = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| extensions2 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| extensions2 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| sock1 = [[LGA 1156]]
| sock1 = [[LGA 1156]]
| sock2 = [[LGA 1366]]
| sock2 = [[LGA 1366]]
| sock3 = [[LGA 1567]]
| sock3 = [[LGA 1567]]
| sock4 = [[µPGA 988]]
| sock4 = [[rPGA988A]]
| predecessor = [[Nehalem (microarchitecture)|Nehalem]]
| predecessor = [[Nehalem (microarchitecture)|Nehalem]]
| successor = [[Sandy Bridge (microarchitecture)|Sandy Bridge]]
| successor = [[Sandy Bridge]]
| support status = Unsupported
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
| name = Sandy Bridge
| name = Sandy Bridge
| image =
| image =
| created = {{start date and age|January 9, 2011}}
| image_size = 150px
| produced-end = September 27, 2013 <ref>{{Cite web |last= Shvets |first=Gennadiy |date=September 26, 2012 |title=Intel discontinues second-generation Core i5 and i7 CPUs |url=http://www.cpu-world.com/news_2012/2012092601_Intel_discontinues_second-generation_Core_i5_and_i7_CPUs.html |access-date=2020-07-29 |website=CPU World}}</ref>
| created = January 2011
| model = Celeron Series<br />Pentium Series<br />Core i3/i5/i7/i7 Extreme Series<br />[[Intel Sandy Bridge-based Xeon microprocessors|Xeon E3/E5 Series]]
| model = Celeron Series
| cores = 1–4 (4-6 Extreme, 2-8 Xeon)
| model1 = Pentium Series
<!-- (2–8)
| model2 = Core i3 Series
| cores1 = 4–6 (8–12) (Extreme)
| model3 = Core i5 Series
| cores2 = 2–8 (4–16) (Xeon) -->
| model4 = Core i7 Series
| code = 80619 (extreme desktop)<br />80620 (server LGA1356)<br />80621 (server LGA2011)<br />80623 (desktop)<br />80627 (mobile)
| model5 = Core i7 Extreme Series
| transistors = 504M to 2.27B [[32 nanometer|32nm]]
| model6 = Xeon E3 Series
<!-- (Q0)
| model7 = Xeon E5 Series
| transistors1 = 624 M [[32 nanometer|32nm]] (J1)
| cores = 1-4 (2-8)
| transistors2 = 1,160 M [[32 nanometer|32nm]] (D2)
| cores1 = 4-6 (8-12) (Extreme)
| transistors3 = 1,270 M [[32 nanometer|32nm]] (M0, M1)
| cores2 = 2-8 (4-16) (Xeon)
| transistors = 504M [[32 nanometer|32nm]] (Q0)
| transistors4 = 2,270 M [[32 nanometer|32nm]] (C1, C2) -->
| slowest = 1.60
| transistors1 = 624M [[32 nanometer|32nm]] (J1)
| fastest = 3.60
| transistors2 = 1,160M [[32 nanometer|32nm]] (D2)
| transistors3 = 1,270M [[32 nanometer|32nm]] {M0, M1)
| l1cache = 64&nbsp;[[Kibibyte|KB]] per core
| l2cache = 256&nbsp;KB per core
| transistors4 = 2,270M [[32 nanometer|32nm]] (C1, C2)
| l3cache = 1&nbsp;MB to 8&nbsp;MB shared<br />10&nbsp;MB to 15&nbsp;MB (Extreme)<br />3&nbsp;MB to 20&nbsp;MB (Xeon)
| clock = 1.60 GHz to 3.60 GHz
| l1cache = 64KB per core
| dmi-slowest = 5.00 GT/s
| gpu = [[Intel HD Graphics|HD Graphics]]<br />650&nbsp;[[Hertz|MHz]] to 1100&nbsp;MHz<br />[[Intel HD Graphics|HD Graphics 2000]]<br />650&nbsp;[[Hertz|MHz]] to 1250&nbsp;MHz<br />[[Intel HD Graphics|HD Graphics 3000]]<br />650&nbsp;MHz to 1350&nbsp;MHz<br />[[Intel HD Graphics|HD Graphics P3000]]<br />850&nbsp;MHz to 1350&nbsp;MHz
| l2cache = 256KB per core
| arch = [[x86-64]]
| l3cache = 3MB to 8MB shared<br>10MB to 15MB (Extreme)<br>3MB to 20MB (Xeon)
| microarch = Sandy Bridge
| dmi = 5.00GT/s
| instructions = [[x86]], [[x86-64]]
| gpu = [[Intel_HD_Graphics|HD Graphics 2000]]<br>650 MHz to 1250 MHz
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]]
| gpu1 = [[Intel_HD_Graphics|HD Graphics 3000]]<br>650 MHz to 1350 MHz
| extensions1 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| gpu2 = [[Intel_HD_Graphics|HD Graphics P3000]]<br>850 MHz to 1350 MHz
| extensions2 = [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[Trusted Execution Technology|TXT]]
| arch1 = [[Sandy Bridge (microarchitecture)|Sandy Bridge]] [[x86]]
| sock1 = [[LGA 1155]] (desktops and workstations)
| instructions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]]
| extensions = [[x86-64]], [[Intel 64]]
| sock2 = [[LGA 2011]] (high-end servers)
| sock3 = [[LGA 1356]] (low-end, dual-processor servers)
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| sock4 = [[Socket G2]]
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Trusted Execution Technology|TXT]], [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| sock1 = [[LGA 1155]]
| sock5 = [[BGA-1023]]
| sock2 = [[LGA 2011]]
| sock6 = [[BGA-1224]]
| predecessor = [[Nehalem (microarchitecture)|Nehalem]] (Tock)<br />[[Westmere (microarchitecture)|Westmere]] (Tick)
| sock3 = [[rPGA988B]]
| successor = [[Ivy Bridge (microarchitecture)|Ivy Bridge]] (Tick)<br />[[Haswell (microarchitecture)|Haswell]] (Tock)
| sock4 = [[BGA-1023]]
| sock5 = [[BGA-1224]]
|sock7=[[BGA-1284]]
| support status = Unsupported
| predecessor = [[Nehalem (microarchitecture)|Nehalem (tock)]]<br>[[Westmere (microarchitecture)|Westmere (tick)]]
| successor = [[Ivy Bridge (microarchitecture)|Ivy Bridge (tick)]]<br>[[Haswell (microarchitecture)|Haswell (tock)]]
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
| name = Ivy Bridge
| name = Ivy Bridge
| image =
| image = Ivy Bridge Codename Logo.jpg
| caption = Intel's internal Ivy Bridge logo<ref>{{cite web |title=Origin of a Codename: Ivy Bridge |url=http://www.intelfreepress.com/news/origin-of-a-codename-ivy-bridge/48 |website=Intel Free Press |language=en-US |date=April 19, 2012 |access-date=January 16, 2014 |url-status=dead |archive-url=https://web.archive.org/web/20140116133839/http://www.intelfreepress.com/news/origin-of-a-codename-ivy-bridge/48 |archive-date=January 16, 2014 |df=dmy-all}}</ref>
| image_size = 150px
| image_size = 240px
| created = April 29, 2012
| produced-start = {{Start date and age|April 29, 2012}}
| model = Pentium G Series
| produced-end = {{End date and age|June 5, 2015}}
| model1 = Core i3 Series
| soldby = [[Intel]]
| model2 = Core i5 Series
| designfirm = [[Intel]]
| model3 = Core i7 Series
| manuf1 = [[Intel]]
| model4 = Xeon E3 v2 Series
| size-from = [[Intel]] [[22 nm process|22 nm]]
| cores = 2-4 (4-8)
| model = Celeron G Series
| transistors = 624M [[22 nanometer|22nm]] (L1)
| model1 = Pentium G Series
| transistors1 = 1,480M [[22 nanometer|22nm]] (E1, N0)
| model2 = Core i3 Series
| clock = 1.70 GHz to 3.80 GHz
| l1cache = 64KB per core
| model3 = Core i5 Series
| model4 = Core i7 Series
| l2cache = 256KB per core
| model5 = [[Intel Ivy Bridge–based Xeon microprocessors|Xeon E3/E5/E7 v2 Series]]
| l3cache = 3MB to 8MB shared
| cores = 2–4 (Mainstream) <br/> 2–15 (Xeon)
| cpuid = 0306A9h
| transistors = 2.104B
| code = 80637 (desktop)
| clock = 1.4 to 4.1{{nbsp}}GHz
| code1 = 80638 (mobile)
| l1cache = 64{{nbsp}}[[Kibibyte|KB]] per core
| dmi = 5.00GT/s
| l2cache = 256{{nbsp}}KB per core
| gpu = [[Intel_HD_Graphics|HD Graphics 2500]]<br>650 MHz to 1150 MHz
| l3cache = 2 to 8{{nbsp}}MB shared
| gpu1 = [[Intel_HD_Graphics|HD Graphics 4000]]<br>350 MHz to 1300 MHz
| cpuid = 0306A9h
| gpu2 = [[Intel_HD_Graphics|HD Graphics P4000]]<br>650 MHz to 1250 MHz
| code = 80633 (extreme desktop) <br/> 80634 (server LGA1356) <br/> 80635 (server E5 LGA2011) <br/> 80636 (server E7 LGA2011) <br/> 80637 (desktop) <br/> 80638 (mobile)
| arch1 = [[Sandy Bridge (microarchitecture)|Sandy Bridge]] [[x86]]
| dmi-slowest = 5.00
| instructions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]]
| gpu = [[Intel HD Graphics|HD Graphics 2500]]<br />650 to 1150 MHz<br />[[Intel HD Graphics|HD Graphics 4000]]<br />350 to 1300 MHz<br />[[Intel HD Graphics|HD Graphics P4000]]<br />650 to 1250 MHz
| extensions = [[x86-64]], [[Intel 64]]
| arch = [[x86-64]]
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| microarch = [[Sandy Bridge]]
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Trusted Execution Technology|TXT]], [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| sock1 = [[LGA 1155]]
| instructions = [[x86]], [[x86-64]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[F16C]]
| sock2 = [[rPGA988B]]
| extensions1 = [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[Trusted Execution Technology|TXT]]
| sock3 = [[BGA-1023]]
| extensions2 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| sock4 = [[BGA-1224]]
| sock1 = '''Desktop & Workstation''' {{bulleted list |[[LGA 1155]] |[[LGA 2011]] |<br>}}
| predecessor = [[Sandy Bridge (microarchitecture)|Sandy Bridge]]
| sock2 = '''Server''' {{bulleted list |[[LGA 2011]] |[[LGA 2011|LGA 2011-1]] |[[LGA 1356]] |<br>}}
| successor = [[Haswell (microarchitecture)|Haswell]]
| sock3 = '''Mobile''' {{bulleted list |[[Socket G2]] |[[BGA 1023]] |[[BGA 1224]] |[[BGA 1284]]}}
| brand1 = [[Celeron]]
| brand2 = [[Pentium]]
| brand3 = [[Intel Core|Core]]
| brand4 = [[Xeon]]
| predecessor = [[Sandy Bridge]] (Tock)
| successor = [[Haswell (microarchitecture)|Haswell]] (Tock/Architecture)
| support status = Unsupported
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
| name = Haswell
| name = Haswell
| image =
| image = Haswell Chip.jpg
| caption = A Haswell [[Wafer (electronics)|wafer]] with several [[Die (integrated circuit)|dies]], with a pin for scale
| image_size = 150px
| produced-start = {{start date and age|June 4, 2013}}
| model = Core i3 Series
| produced-end =
| model1 = Core i5 Series
| brand1 = {{unbulleted list|Core i3|Core i5|Core i7|Xeon E3 v3|Xeon E5 v3|Xeon E7 v3|Pentium|Celeron}}
| model2 = Core i7 Series
| model = {{unbulleted list|Haswell|Haswell Refresh|Haswell-E|Haswell-EP|Haswell-EX}}
| created = 2013
| numcores = {{unbulleted list|2–4&nbsp;(mainstream)|6–8&nbsp;(enthusiast)|2–18&nbsp;(Xeon)}}
| cores = 2-4
| size-from = [[22 nanometer|22 nm]] ([[FinFET|Tri-Gate]])
| cores1 = 6+ (Extreme)
| cores2 = 8+ (Xeon)
| size-to =
| l1cache = 64&nbsp;[[Kibibyte|KB]] per core
| transistors = [[22 nanometer|22 nm]] transistors
| l2cache = 256&nbsp;KB per core
| clock =
| l3cache = 2–45&nbsp;[[Mebibyte|MB]] (shared)
| l1cache =
| l4cache = 128&nbsp;MB of [[eDRAM]] (Iris Pro models only)
| l2cache =
| l3cache =
| cpuid = 0306C3h
| code = {{unbulleted list|80646 (desktop [[LGA 1150]])|80647 (mobile [[Intel Socket G3|Socket G3]])|80648 (desktop [[LGA 2011|LGA 2011-3]])|80644 (server LGA 2011-3)}}
| llcache = 35MB
| dmi =
| dmi =
| gpu = {{unbulleted list|[[Intel HD Graphics|HD Graphics]] 4200|HD Graphics 4400|HD Graphics 4600|HD Graphics 5000|Iris 5100|Iris Pro 5200}}
| gpu =
| arch1 = [[Haswell (microarchitecture)|Haswell]] [[x86]]
| arch = [[x86-64]]
| microarch = Haswell
| instructions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[FMA instruction set|FMA3]]
| extensions = [[x86-64]], [[Intel 64]]
| instructions = [[x86]], [[x86-64]]
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| extensions = [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[Trusted Execution Technology|TXT]]
| extensions1 = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[FMA instruction set|FMA3]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2#Advanced Vector Extensions 2|AVX2]], and [[Transactional Synchronization Extensions|TSX]] (disabled via [[microcode]], except for Haswell-EX)
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Advanced_Vector_Extensions_2#Advanced_Vector_Extensions_2|AVX2]], [[Trusted Execution Technology|TXT]], [[Transactional_Synchronization_Extensions|TSX]]
| extensions3 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| extensions3 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| sock1 = [[LGA 1150]]
| sock1 = [[LGA 1150]]
| sock2 = [[rPGA947]]
| sock2 = [[rPGA 947]]
| sock3 = [[BGA-1364]]
| sock3 = BGA 1364
| sock4 = BGA 1168
| predecessor = [[Sandy Bridge (microarchitecture)|Sandy Bridge (tock)]]
| sock5 = [[LGA 2011-v3]]
| predecessor2 = [[Ivy Bridge (microarchitecture)|Ivy Bridge (tick)]]
| successor = [[Broadwell (microarchitecture)|Broadwell (tick)]]
| predecessor = [[Sandy Bridge]] (Tock)<br>[[Ivy Bridge (microarchitecture)|Ivy Bridge]] ([[Tick–tock model|Tick]])
| successor2 = [[Skylake (microarchitecture)|Skylake (tock)]]
| successor = [[Broadwell (microarchitecture)|Broadwell]] (Tick/Process)<br>[[Skylake (microarchitecture)|Skylake]] (Tock)
| support status = Unsupported
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
| name = Broadwell
| name = Broadwell
| image =
| image_size =
| produced-start = {{start date and age|October 27, 2014}}
| image_size = 150px
| produced-end = November 2018<ref>{{Cite web |last=Perillo |first=Ron |date=November 9, 2017 |title=Intel Broadwell-E CPUs Officially Discontinued |url=https://www.eteknix.com/intel-broadwell-e-cpus-officially-discontinued/ |access-date=2020-07-29 |website=eTeknix}}</ref>
| model = Core i3 Series<br>Core i5 Series<br>Core i7 Series
| size-from = [[14 nanometer|14 nm]] ([[FinFET|Tri-Gate]])
| created = 2014
| cores =
| size-to =
| cpuid = 0306D4h
| transistors = [[14 nanometer|14 nm transistors]]
| code = {{Unbulleted list|80658 (mainstream desktop/mobile, Xeon E3)|80660 (Xeon E5)|80669 (Xeon E7)|80671 (enthusiast desktop)|80674 (Xeon D)|80682 (Xeon D, Hewitt Lake)}}
| clock =
| l1cache =
| model =
| brand1 = {{unbulleted list|[[Core i3]]|[[Core i5]]|[[Core i7]]|[[List of Intel Core M microprocessors|Core M]]|[[Celeron]]|[[Pentium]]|[[Xeon]]}}
| l2cache =
| numcores = {{unbulleted list|2–4&nbsp;(mainstream)|6–10&nbsp;(enthusiast)|4–24&nbsp;(Xeon)}}
| l3cache =
| llcache = 35MB
| transistors =
| l1cache = 64 [[Kibibyte|KB]] per core
| dmi =
| l2cache = 256 KB per core
| gpu =
| l3cache = 2-6 [[Mebibyte|MB]] (shared)
| arch1 = [[Haswell (microarchitecture)|Haswell]] [[x86]]
| l4cache = 128 MB of [[eDRAM]] (Iris Pro models only)
| instructions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[FMA instruction set|FMA3]]
| dmi =
| extensions = [[x86-64]], [[Intel 64]]
| gpu = {{unbulleted list|HD 5300|HD 5500|HD 5700P|HD 6000|HD 6100|HD 6200|HD 6300P|HD Graphics}}
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| arch = [[x86-64]]
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Advanced_Vector_Extensions_2#Advanced_Vector_Extensions_2|AVX2]], [[Trusted Execution Technology|TXT]], [[Transactional_Synchronization_Extensions|TSX]]
| microarch = [[Haswell (microarchitecture)|Haswell]]
| extensions3 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| extensions2 = [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[Trusted Execution Technology|TXT]]
| socket =
| instructions = [[x86]], [[x86-64]]
| predecessor = [[Haswell (microarchitecture)|Haswell]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2|AVX2]], [[Transactional Synchronization Extensions|TSX]], [[FMA instruction set|FMA3]]
| successor = [[Skylake (microarchitecture)|Skylake]]
| extensions3 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| socket =
| sock1 = [[LGA 1150]]
| sock2 = [[BGA 1364]]
| sock3 = [[LGA 2011-v3]]
| predecessor = {{unbulleted list|[[Haswell (microarchitecture)|Haswell]] (Tock/Architecture)|[[Haswell (microarchitecture)#Haswell Refresh|Haswell Refresh]] (Optimization)}}
| successor = [[Skylake (microarchitecture)|Skylake]] (Tock/Architecture)
| support status = Unsupported
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
| name = Skylake
| name = Skylake
| image = Intel_CPU_Core_i7_6700K_Skylake_perspective.jpg
| image =
| caption = Intel Core i7-6700K with four physical cores
| image_size = 150px
<!----------------- General Info ----------------->
| model = Core i3 Series<br>Core i5 Series<br>Core i7 Series
| produced-start = {{Start date and age|August 5, 2015}}
| created = expected 2015-2016
| produced-end = {{End date and age|March 4, 2019}} (desktop processors)
| cores =
| soldby = [[Intel]]
| transistors = [[14 nanometer|14 nm]] transistors
| designfirm = [[Intel]]
| clock =
| manuf1 = [[Intel]]
| l1cache =
| cpuid = 0406e3h, 0506e3h
| l2cache =
| code = {{Unbulleted list|80662 (mainstream and mobile Xeon E3)|80673 (enthusiast and server)}}
| l3cache =
<!-------------------- Cache --------------------->
| llcache =
| l1cache = 64{{nbsp}}KB per core
| dmi =
| l2cache = 256{{nbsp}}KB per core <br /> (1{{nbsp}}MB per core for Skylake-X)
| gpu =
| l3cache = Up to 2{{nbsp}}MB per core <br /> (1.375{{nbsp}}MB per core for Skylake-X)
| arch1 = Skylake [[x86]]
| l4cache = 128{{nbsp}}MB of [[eDRAM]] (on select models)
| instructions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[FMA instruction set|FMA3]]
<!------- Architecture and classification -------->
| extensions = [[x86-64]], [[Intel 64]]
| application =
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| size-from = [[14 nm process|14&nbsp;nm]] bulk silicon 3D transistors ([[FinFET|Tri-Gate]])
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Advanced_Vector_Extensions_2#Advanced_Vector_Extensions_2|AVX2]], [[Trusted Execution Technology|TXT]], [[Transactional Synchronization Extensions|TSX]]
| microarch = Skylake
| extensions3 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| arch = [[x86-64]]
| socket =
| extensions = [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[Intel MPX|MPX]], [[Trusted Execution Technology|TXT]], [[Software Guard Extensions|SGX]]<ref name=i7-6700k>{{cite web|url=https://ark.intel.com/products/88195/Intel-Core-i7-6700K-Processor-8M-Cache-up-to-4_20-GHz|title=Intel Core i7-6700K Processor (8M Cache, up to 4.20 GHz)|website=Ark.intel.com|access-date=January 24, 2018}}</ref>
| predecessor = [[Haswell (microarchitecture)|Haswell (tock)]]<br>[[Broadwell (microarchitecture)|Broadwell (tick)]]
| extensions1 = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Intel ADX|ADX]]
| successor = [[Cannonlake|Cannonlake (tick)]]
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2|AVX2]], [[AVX-512]] (SkyLake-SP, SkyLake-W & SkyLake-X<ref name=tomshardware_purley>[http://www.tomshardware.com/news/intel-xeon-skylake-purley-cpu,31980.html Tom's Hardware: Skylake Xeon Platforms Spotted, Purley Makes A Quiet Splash At Computex]. June 3, 2016</ref>), [[Transactional Synchronization Extensions|TSX]], [[FMA instruction set|FMA3]]
| extensions3 = [[VT-x]], [[VT-d]]
| instructions = [[x86-64]] ([[Intel 64]])
| sock1 = '''Desktop''' {{bulleted list |[[LGA 1151]] |[[LGA 2066]] |<br>}}
| sock2 = '''Server & Workstation''' {{bulleted list |[[LGA 3647]] |[[LGA 2066]] |<br>}}
| sock3 = '''Mobile''' {{bulleted list |BGA 1168 |BGA 1356 |BGA 1515 |BGA 1440<ref>{{cite web |last1=Cutress |first1=Ian |date=August 5, 2015 |title=The Intel Skylake Mobile and Desktop Launch, with Architecture Analysis |url=http://www.anandtech.com/show/9582/intel-skylake-mobile-desktop-launch-architecture-analysis/4 |website=AnandTech |language=en-US |access-date=September 18, 2015}}</ref>}}
<!----------- Physical specifications ------------>
| numcores = 2–28
| clock = Up to 4.5&nbsp;GHz
<!--------- Products, models, variants ----------->
| brand1 = {{unbulleted list|Core i3|Core i5|Core i7|Core i9|Core m3|Core m5|Core m7|Xeon|Celeron|Pentium}}
<!------------------ History ------------------->
| predecessor = [[Broadwell (microarchitecture)|Broadwell]] (Tick/Process)
| successor = {{ubl|[[Kaby Lake]] (Optimization)|[[Cascade Lake (microprocessor)|Cascade Lake-SP]] (Skylake-SP)|[[Palm Cove (microarchitecture)|Palm Cove]] (Process)}}
| support status = Client: Legacy support for iGPU <br /> Xeon E3: Legacy support for iGPU<br />Other Xeon: supported
}}
}}
{{{{BASEPAGENAME}}/sandbox
{{{{BASEPAGENAME}}/sandbox
| name = Cannonlake
| name = Cannon Lake
| created = {{Start date and age|May 15, 2018}}
| model = Core i3 Series<br>Core i5 Series<br>Core i7 Series
| produced-end = {{End date and age|February 28, 2020}}
| created = 2016
| soldby = [[Intel]]
| cores =
| designfirm = [[Intel]]
| transistors = [[10 nanometer|10 nm transistors]]
| manuf1 = [[Intel]]
| clock =
| size-from = [[Intel]] [[10 nanometer|10 nm]] ([[FinFET|tri-gate]]) transistors
| l1cache =
| clock = 3.2{{nbsp}}GHz
| l2cache =
| l1cache = 64{{nbsp}}KB per core
| l3cache =
| l2cache = 256{{nbsp}}KB per core
| llcache =
| l3cache = 2{{nbsp}}MB per core
| dmi =
| arch = [[x86-64]]
| gpu =
| instructions = [[x86-64]], [[Intel 64]]
| arch1 = [[Skylake (microarchitecture)|Skylake]] [[x86]]
| extensions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[FMA instruction set|FMA3]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2#Advanced Vector Extensions 2|AVX2]], [[AVX-512]], [[Intel SHA extensions|SHA]],<ref name=":0">{{cite web |last=Kirsch |first=Nathan |date=February 21, 2016 |title=Intel Cannonlake Added To LLVM's Clang – AVX-512 |url=http://www.legitreviews.com/intel-cannonlake-added-to-llvms-clang_179210 |work=Legit Reviews |access-date=October 23, 2016 |archive-url=https://web.archive.org/web/20161023135525/http://www.legitreviews.com/intel-cannonlake-added-to-llvms-clang_179210 |archive-date=2016-10-23 |url-status=dead}}</ref> [[Trusted Execution Technology|TXT]], [[Transactional Synchronization Extensions|TSX]], [[Software Guard Extensions|SGX]], [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| instructions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[FMA instruction set|FMA3]]
| numcores = 2
| extensions = [[x86-64]], [[Intel 64]]
| gpu = Factory disabled
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| sock1 = BGA 1440
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Advanced_Vector_Extensions_2#Advanced_Vector_Extensions_2|AVX2]], [[Trusted Execution Technology|TXT]], [[Transactional_Synchronization_Extensions|TSX]]
| extensions3 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| brand1 = [[Intel Core|Core]]
| predecessor = Desktop: [[Coffee Lake]] (2nd optimization)<br>[[Kaby Lake Refresh]] (2nd optimization)
| socket =
| successor = [[Ice Lake (microprocessor)|Ice Lake]] (architecture)
| predecessor = [[Skylake (microarchitecture)|Skylake]]
| microarch = [[Palm Cove (microarchitecture)|Palm Cove]]
| successor =
| support status = Legacy support for iGPU
}}
}}
{{{{BASEPAGENAME}}/sandbox
| name = Apple A11 Bionic
| image = Apple A11.jpg
| caption =
| produced-start = September 12, 2017
| produced-end = present
| slowest =
| slow-unit =
| fastest = 2.39 GHz
| fast-unit =
| size-from = 10 nm
| size-to =
| soldby =
| designfirm = [[Apple Inc.]]
| manuf1 = [[TSMC]]
| arch = [[ARM architecture family#64/32-bit architecture|A64]]
| microarch = [[ARMv8-A|ARMv8&#8209;A]] compatible
| code = APL1W72
| numcores = 6
| core1 = Monsoon
| core2 = Mistral
| l1cache =32 KB instruction, 32 KB data
| l2cache =8 MB
| l3cache =none
| application = Mobile
| gpu = Apple-designed 3 core
| predecessor = [[Apple A10 Fusion]]
| successor =
| variant =
| pcode1 = test1
}}

{{clear}}
{{clear}}


Line 520: Line 629:
{{ {{BASEPAGENAME}}
{{ {{BASEPAGENAME}}
| image = KL Intel i286.jpg
| image = KL Intel i286.jpg
| caption = An 8MHz Intel 80286 Microprocessor
| caption = An Intel A80286-8 processor with a gray ceramic heat spreader
| manuf1 = [[Intel]]<br>[[IBM]]<br>[[AMD]]<br>[[Harris]] ([[Intersil]])<br>[[Siemens AG]]<br>[[Fujitsu]]
| manuf1 = [[Intel]], [[IBM]], [[AMD]], [[Harris Corporation|Harris]] ([[Intersil]]), [[Siemens]], [[Fujitsu]]
| produced-start = February 1982
| model = 80286 Series
| produced-end = 1991<ref>{{cite web |url=https://www.cpushack.com/life-cycle-of-cpu.html |title=CPU History - The CPU Museum - Life Cycle of the CPU |website=cpushack.com |access-date=September 6, 2021 |archive-date=July 20, 2021 |archive-url=https://web.archive.org/web/20210720004826/https://www.cpushack.com/life-cycle-of-cpu.html |url-status=live }}</ref>
| produced-start = 1982
| slowest = 4 | slow-unit = MHz
| produced-end = early 1990s
| slowest = 6 | slow-unit = MHz (4 MHz for a short time)
| fastest = 25 | fast-unit = MHz
| fastest = 25 | fast-unit = MHz
| fsb = 6 MHz to 25 MHz
| fsb-slowest = 4 | fsb-slow-unit = MHz
| fsb-fastest = 25 | fsb-fast-unit = MHz
| transistors-nostep = 134K 1.5[[Micrometre| µm]]
| transistors = 120,000<ref>Ormsby, John, "Chip Design: A Race Worth Winning", Intel Corporation, Microcomputer Solutions, July/August 1988, page 18</ref> or 134,000, 1.5[[Micrometre|µm]]
| arch = [[x86-16]] (with [[Memory management unit|MMU]])
| arch = [[x86-16]] (with [[memory management unit|MMU]])
| pack1 = 68-pin [[Plastic leaded chip carrier|PLCC]]<br>100-pin [[PQFP]]<br>68-pin [[Pin grid array|PGA]]
| pack1 = 68-pin [[plastic leaded chip carrier|PLCC]]
| predecessor = [[Intel 80186]]
| pack2 = 68-pin [[leadless chip carrier|LCC]]
| pack3 = 68-pin [[pin grid array|PGA]]
| pack4 = 100-pin [[PQFP]] (engineering sample only)
| predecessor = [[8086]], [[8088]] (while [[Intel 80186|80186]] was contemporary)
| successor = [[Intel 80386]]
| successor = [[Intel 80386]]
| co-processor = [[Intel 80287]]
| co-processor = [[Intel 80287]]
| data-width = 16 bits
| address-width = 24 bits
| size-from = [[1.5 µm process|1.5&nbsp;µm]]<ref>{{cite web|url=https://en.wikichip.org/wiki/1.5_%C2%B5m_lithography_process|title=1.5 µm lithography process - WikiChip|website=en.wikichip.org|access-date=January 21, 2019|archive-date=September 9, 2018|archive-url=https://web.archive.org/web/20180909090836/https://en.wikichip.org/wiki/1.5_%C2%B5m_lithography_process|url-status=live}}</ref>
| sock1 = PGA68
| sock2 = PLCC-68
| sock3 = LCC-68
| support status = Unsupported
}}
}}


{{Infobox CPU
{{Infobox CPU
| name = P5
| name = Pentium (i586)
| image =
| image = Intel Pentium MMX Processor Logo.svg
| image_size = 150px
| image_size = 150px
| model = Pentium Series
| model = Pentium series
| model1 = Pentium OverDrive Series
| model1 = Pentium OverDrive series
| model2 = Pentium MMX Series
| model2 = Pentium MMX series
| created = March 22, 1993
| produced-start = March 22, 1993
| produced-end = July 15, 1999<ref name="discontinued">{{cite web|url=http://developer.intel.com/design/pcn/Processors/D0000777.pdf|title=Product Change Notification #777|date=February 9, 1999|publisher=Intel|archive-url=https://web.archive.org/web/20000127045353/http://developer.intel.com/design/pcn/Processors/D0000777.pdf|archive-date=January 27, 2000|url-status=dead|access-date=October 14, 2019}}</ref>{{better source needed|date=October 2019}}<!-- Note that this is for the P55C model, it's unclear if Tillamook was discontinued here as well or not. -->
| cores-nothread = 1
| cores = 1
| transistors-nostep = 3.1M 0.8 [[800 nanometer|µm]]
| transistors-nostep1 = 3.2M 0.6 [[600 nanometer|µm]]
| transistors = 3.1M 0.8 [[800 nanometer|μm]] (P5)
| transistors-nostep2 = 3.3M 350 [[350 nanometer|nm]]
| transistors1 = 3.2M 0.6 [[600 nanometer|μm]] (P54C)
| transistors-nostep3 = 4.5M 350 [[350 nanometer|nm]]
| transistors2 = 3.3M 350 [[350 nanometer|nm]] (P54CS)
| transistors3 = 4.5M 350 [[350 nanometer|nm]] (P55C)
| clock = 60 MHz to 300 MHz
| clock = 60–300 MHz
| l1cache = 16 KB to 32 KB
| l1cache = 16–32 KiB
| fsb = 50 MHz to 66 MHz
| fsb = 50–66 MHz
| arch1 = [[P5 (microarchitecture)|P5]] [[x86]] ([[IA-32]])
| arch = [[IA-32]]
| instructions = [[MMX (instruction set)|MMX]]
| microarch = P5
| extensions = [[MMX (instruction set)|MMX]]
| sock1 = [[Socket 4]]
| sock1 = [[Socket 4]]
| sock2 = [[Socket 5]]
| sock2 = [[Socket 5]]
| sock3 = [[Socket 7]]
| sock3 = [[Socket 7]]
| predecessor = [[Intel 80486 (microarchitecture)|Intel 80486]]
| predecessor = [[i486]]
| successor = [[P6 (microarchitecture)|P6]]
| successor = [[P6 (microarchitecture)|P6]], [[Pentium II]]
| support status = Unsupported
}}
}}
{{Infobox CPU
{{Infobox CPU
| name = P6
| name = P6
| image = Intel@250nm@P6@Deschutes@Pentium II@flipchip PB 713539-001 DSCx1 polysilicon microscope stitched@5x (38025161182).jpg
| image =
| caption = Die shot of [[Pentium II|Deschutes]] core
| image_size = 150px
| image_size =
| created = November 1, 1995
| created = {{start date and age|November 1, 1995}}
| model = Celeron Series
| slowest = 150<ref>{{cite web |title=Pentium® Pro Processor at 150 MHz, 166 MHz, 180 MHz and 200 MHz |url=https://www.dexsilicium.com/Intel_PentiumPro.pdf |publisher=Intel Corporation |page=1 |date=November 1995 |archive-url=https://web.archive.org/web/20160412090026/https://www.dexsilicium.com/Intel_PentiumPro.pdf |archive-date=April 2, 2016 |url-status=dead}}</ref>
| model1 = Pentium II Series
| fastest = 1.40
| model2 = Pentium III Series
| slow-unit = MHz
| model3 = Pentium Pro Series
| fsb-slowest = 66
| model4 = Pentium II Xeon Series
| fsb-fastest = 133
| model5 = Pentium III Xeon Series
| cores-nothread = 1
| fsb-slow-unit = MHz
| fsb-fast-unit = MHz
| transistors = 7.5M [[350 nanometer|350 nm]]
| l1cache = Pentium Pro: 16 KB (8 KB I cache + 8 KB D cache)<br /> Pentium II/III: 32 KB (16 KB I cache + 16 KB D cache)
| transistors1 = 7.5M [[250 nanometer|250 nm]] (B0, B1)
| l2cache = 128 KB to 512 KB<br />256 KB to 2048 KB (Xeon)
| transistors2 = 9.5M [[250 nanometer|250 nm]] (B0, C0)
| arch = [[x86]]
| transistors3 = 19M [[250 nanometer|250 nm]] (B0)
| extensions = [[MMX (instruction set)|MMX]] (Pentium II/III)<br />[[Streaming SIMD Extensions|SSE]] (Pentium III)
| transistors4 = 28M [[180 nanometer|180 nm]] (A1, A2, B0, C0, D0)
| microarch = P6
| transistors5 = 44M [[130 nanometer|130 nm]] (A1, B1, C1, D0)
| transistors1 = 5.5M [[600 nm process|500 nm]]
| clock = 233 MHz to 1.40 GHz
| transistors2 = 7.5M [[350 nm process|350 nm]]
| l1cache = 32 KB
| transistors3 = 7.5M [[250 nm process|250 nm]] (B0, B1)
| l2cache = 128 KB to 512 KB<br>256 KB to 2048 KB (Xeon)
| transistors4 = 9.5M [[250 nm process|250 nm]] (B0, C0)
| fsb = 66 MHz to 133 MHz
| transistors5 = 19M [[250 nm process|250 nm]] (B0)
| arch1 = [[P6 (microarchitecture)|P6]] [[x86]]
| transistors6 = 28M [[180 nm process|180 nm]] (A1, A2, B0, C0, D0)
| instructions = [[MMX (instruction set)|MMX]]
| transistors7 = 44M [[130 nm process|130 nm]] (A1, B1, C1, D0)
| extensions = [[Streaming SIMD Extensions|SSE]]
| numcores = 1
| sock1 = [[Socket 370]]
| sock2 = [[Socket 479]]
| sock1 = [[Socket 8]]
| predecessor = [[P5 (microarchitecture)|P5]]
| sock2 = [[Slot 1]]
| sock3 = [[Socket 370]]
| variant = [[Pentium M (microarchitecture)|Pentium M]]
| sock4 = [[Socket 479]]
| variant1 = [[Enhanced Pentium M (microarchitecture)|Enhanced Pentium M]]
| model = Celeron Series
| successor = [[NetBurst (microarchitecture)|NetBurst]]
| model1 = Pentium II Series
| model2 = Pentium III Series
| model3 = Pentium Pro Series
| model4 = Pentium II Xeon Series
| model5 = Pentium III Xeon Series
| predecessor = [[P5 (microarchitecture)|P5]]
| variant = Pentium M
| variant1 = Enhanced Pentium M
| successor = [[NetBurst (microarchitecture)|NetBurst]], [[Pentium M]]
| support status = Unsupported
}}
}}
{{Infobox CPU
{{Infobox CPU
| name = P6 Pentium M
| name = P6 Pentium M
| image =
| image = Pentium M.jpg
| image_size = 150px
| image_size = 150px
| created = 2004
| created = March 12, 2003
| model = A100 Series
| model = A100 Series
| model1 = EP80579 Series
| model1 = EP80579 Series
| model2 = Celeron M Series
| model2 = Celeron M Series
| model3 = Pentium M Series
| model3 = Pentium M Series
| cores-nothread = 1
| cores = 1
| transistors = 77M [[130 nanometer|130 nm]] (B1, B2)
| transistors = 77M [[130 nanometer|130 nm]] (B1, B2)
| transistors1 = 144M [[90 nanometer|90 nm]] (B0, C0)
| transistors1 = 144M [[90 nanometer|90 nm]] (B0, C0)
| transistors2 = 151M [[65 nanometer|65 nm]] (C0, D0)
| transistors2 = 151M [[65 nanometer|65 nm]] (C0, D0)
| clock = 600 MHz to 2.26 GHz
| clock = 600 MHz to 2.26 GHz
| l1cache = 32KB
| l1cache = 64KB (32 KB I Cache + 32 KB D cache)
| l2cache = 512 KB to 2048 KB
| l2cache = 512 KB to 2048 KB
| fsb = 400 MHz to 533 MHz
| fsb = 400 MT/s to 533 MT/s
| arch1 = [[P6 (microarchitecture)|P6]] [[x86]]
| arch = [[x86]]
| instructions = [[MMX (instruction set)|MMX]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]]
| microarch = P6
| extensions = [[Streaming SIMD Extensions|SSE]], [[SSE2]]
| socket = [[Socket M]]
| socket = [[Socket M]]
| predecessor = [[P5 (microarchitecture)|P5]]
| predecessor = [[NetBurst (microarchitecture)|NetBurst]]
| successor = [[Enhanced Pentium M (microarchitecture)|Enhanced Pentium M]]
| successor = [[Enhanced Pentium M (microarchitecture)|Enhanced Pentium M]]
| support status = Unsupported
}}
}}
{{Infobox CPU
{{Infobox CPU
Line 626: Line 759:
| model3 = Core Duo Series
| model3 = Core Duo Series
| model4 = Xeon LV Series
| model4 = Xeon LV Series
| cores-nothread = 1-2
| cores = 1-2
| transistors = 151M [[65 nanometer|65 nm]] (C0, D0)
| transistors = 151M [[65 nanometer|65 nm]] (C0, D0)
| clock = 1.06 GHz to 2.33 GHz
| clock = 1.06 GHz to 2.33 GHz
| l1cache = 32 KB
| l1cache = 64 KB
| l2cache = 1 MB to 2 MB<br>2 MB (Xeon)
| l2cache = 1 MB to 2 MB<br />2 MB (Xeon)
| fsb = 533 MHz to 667 MHz
| fsb = 533 MT/s to 667 MT/s
| arch1 = [[P6 (microarchitecture)|P6]] [[x86]]
| arch = [[x86]]
| instructions = [[MMX (instruction set)|MMX]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]]
| microarch = P6
| extensions = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]]
| socket = [[Socket M]]
| socket = [[Socket M]]
| predecessor = [[Pentium M (microarchitecture)|Pentium M]]
| predecessor = [[Pentium M (microarchitecture)|Pentium M]]
| successor = [[Intel Core (microarchitecture)|Intel Core]]
| successor = [[Intel Core (microarchitecture)|Intel Core]]
| support status = Unsupported
}}
}}
{{Infobox CPU
{{Infobox CPU
| name = NetBurst
| name = NetBurst
| image =
| image =
| image_size = 150px
| image_size =
| created = November 20, 2000
| created = {{start date and age|November 20, 2000}}
| model = Celeron Series
| model = Celeron Series
| model1 = Celeron D Series
| model1 = Celeron D Series
Line 649: Line 783:
| model3 = Pentium D Series
| model3 = Pentium D Series
| model4 = Xeon Series
| model4 = Xeon Series
| cores = 1-2 (2-4)
| cores = 1-2 (2-4 threads with HT)
| cores1 = 2-6 (2-6) (Xeon)
| cores1 =
| transistors = 42M [[180 nanometer|180 nm]] (B2, C1, D0, E0)
| transistors = 42M [[180 nanometer|180 nm]] (B2, C1, D0, E0)
| transistors1 = 55M [[130 nanometer|130 nm]] (B0, C1, D1, M0)
| transistors1 = 55M [[130 nanometer|130 nm]] (B0, C1, D1, M0)
Line 656: Line 790:
| transistors3 = 169M [[90 nanometer|90 nm]] (M0, N0, R0)
| transistors3 = 169M [[90 nanometer|90 nm]] (M0, N0, R0)
| transistors4 = 230M [[90 nanometer|90 nm]] (A0, B0)
| transistors4 = 230M [[90 nanometer|90 nm]] (A0, B0)
| transistors5 = 188M [[65 nanometer|65 nm]] (B1, C1, D0}
| transistors5 = 188M [[65 nanometer|65 nm]] (B1, C1, D0)
| transistors6 = 376M [[65 nanometer|65 nm]] (B1, C1, D0)
| transistors6 = 376M [[65 nanometer|65 nm]] (B1, C1, D0)
| transistors7 = 1,328M [[65 nanometer|65 nm]] (B0)
| transistors7 = 1,328M [[65 nanometer|65 nm]] (B0)
| clock = 267 MHz to 3.73 GHz
| clock = 1.3&nbsp;GHz to 3.8&nbsp;GHz
| l1cache = 8 KB to 16 KB per core
| l1cache = 8 KB to 16 KB per core
| l2cache = 128 KB to 2048 KB<br>256 KB to 2048 KB (Xeon)
| l2cache = 128 KB to 2048 KB
| l3cache = 4 MB to 16 MB shared
| l3cache = 4 MB to 16 MB shared
| fsb = 400 MT/s to 1066 MT/s
| fsb = 400 MT/s to 1066 MT/s
| arch1 = [[NetBurst (microarchitecture)|NetBurst]] [[x86]]
| microarch = NetBurst
| arch = [[x86]] ([[IA-32]]), [[x86-64]] (some)
| instructions = [[MMX (instruction set)|MMX]]
| extensions = [[x86-64]], [[Intel 64]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]]&nbsp;(some)
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]]
| sock1 = [[Socket 423]]
| sock1 = [[Socket 423]]
| sock2 = [[Socket 478]]
| sock2 = [[Socket 478]]
| sock3 = [[Socket 771]]
| sock3 = [[Socket 603]]
| sock4 = [[Socket 775]]
| sock4 = [[Socket 604]]
| sock5 = [[LGA 771]]
| sock6 = [[LGA 775]]
| predecessor = [[P6 (microarchitecture)|P6]]
| predecessor = [[P6 (microarchitecture)|P6]]
| successor = [[Intel Core (microarchitecture)|Intel Core]]
| successor = [[Intel Core (microarchitecture)|Intel Core]]<br/>[[IA-64]]
}}
}}
{{Infobox CPU
{{Infobox CPU
| name = Intel Core
| name = Intel Core
| image =
| image =
| image_size = 150px
| produced-start =
| created = 2006
| produced-end =
| created = {{start date and age|June 26, 2006}}&nbsp;(Xeon)<br/>{{start date and age|July 27, 2006}}&nbsp;(Core&nbsp;2)
| model = Celeron Series
<!-- | model = Celeron Series
| model1 = Pentium Series
| model1 = Pentium Series
| model2 = Pentium Dual-Core Series
| model2 = Pentium Dual-Core Series
| model3 = Core 2 Solo Series
| model3 = Core 2 Solo series
| model4 = Core 2 Duo Series
| model4 = Core 2 Duo series
| model5 = Core 2 Quad Series
| model5 = Core 2 Quad series
| model6 = Core 2 Extreme Series
| model6 = Core 2 Extreme Series
| model7 = Xeon Series
| model7 = Xeon Series -->
| model = P6 family ([[Celeron]], [[Pentium]], Pentium Dual-Core, Core 2 range, Xeon)
| cores = 1-4 (1-4)
| cores1 = 2-6 (2-6) (Xeon)
| numcores = 1–4 (2-6 Xeon)
| transistors = 105M [[65 nanometer|65 nm]] (A1, M0)
| transistors = 105M to 582M ([[65 nanometer|65 nm]])<br/>228M to 1900M ([[45 nm]])
<!-- (A1, M0)
| transistors1 = 167M [[65 nanometer|65 nm]] (G0)
| transistors1 = 167M [[65 nanometer|65 nm]] (G0)
| transistors2 = 291M [[65 nanometer|65 nm]] (B2, E1, G0, L2)
| transistors2 = 291M [[65 nanometer|65 nm]] (B2, E1, G0, L2)
| transistors3 = 582M [[65 nanometer|65 nm]] (B3, G0)
| transistors3 = 582M [[65 nanometer|65 nm]] (B3, G0) -->
| clock = 1.06 GHz to 3.33 GHz
| slowest = 933
| fastest = 3.5
| slow-unit = MHz
| fast-unit = GHz
| size-from = [[65 nanometer|65 nm]]
| size-to = [[45 nanometer|45 nm]]
| l1cache = 64 KB per core
| l1cache = 64 KB per core
| l2cache = 1 MB to 8 MB unified
| l2cache = 0.5 to 6 MB per two cores
| l3cache = 8 MB to 16 MB shared (Xeon)
| l3cache = 8 MB to 16 MB shared (Xeon&nbsp;7400)
| fsb = 533 MT/s to 1600 MT/s
| fsb-slowest = 533
| fsb-fastest = 1600
| arch1 = [[Intel Core]] [[x86]]
| instructions = [[MMX (instruction set)|MMX]]
| fsb-slow-unit = [[Transfer (computing)|MT/s]]
| fsb-fast-unit = MT/s
| extensions = [[x86-64]], [[Intel 64]]
| arch = [[x86-64]]
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]]
| microarch = Core
| instructions = [[x86]], [[x86-64]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]] (45nm Core 2 only), [[VT-x]] (some)
| sock1 = [[Socket M]] (µPGA 478)
| sock1 = [[Socket M]] (µPGA 478)
| sock2 = [[Socket P]] (µPGA 478)
| sock2 = [[Socket P]] (µPGA 478)
| sock3 = [[Socket T]] ([[LGA 775]])
| sock3 = [[Socket T]] ([[LGA 775]])
| sock4 = [[Micro-FCBGA|FCBGA]] (µBGA 479)
| sock4 = [[Socket J]] ([[LGA 771]])
| sock5 = [[Micro-FCBGA|FCBGA]] (µBGA 965)
| sock5 = [[Socket 604]]
| sock6 = [[Micro-FCBGA|FCBGA]] (µBGA 479)
| predecessor = [[NetBurst (microarchitecture)|NetBurst]]
| sock7 = [[Micro-FCBGA|FCBGA]] (µBGA 965)
| successor = [[Penryn (microarchitecture)|Penryn (tick)]]<br>[[Nehalem (microarchitecture)|Nehalem (tock)]]
| predecessor = [[NetBurst (microarchitecture)|NetBurst]]<br/>[[Enhanced Pentium M (microarchitecture)|Enhanced Pentium M]] ([[P6 (microarchitecture)|P6]])
| successor = [[Penryn (microarchitecture)|Penryn (tick)]]<br/>(a version of Core)<br/>[[Nehalem (microarchitecture)|Nehalem (tock)]]
| support status = Unsupported
}}
}}
{{Infobox CPU
{{Infobox CPU
| name = Penryn
| name = Penryn
| image =
| image_size = 150px
| image_size = 150px
| created = 2007-2008
| created = {{start date and age|November 2007}}
| model = Celeron Series
| model = P6 Family (Celeron, Pentium, Pentium Dual-Core, Core 2 range, Xeon)
<!-- Celeron Series
| model1 = Pentium Series
| model1 = Pentium Series
| model2 = Pentium Dual-Core Series
| model2 = Pentium Dual-Core Series
Line 723: Line 871:
| model5 = Core 2 Quad Series
| model5 = Core 2 Quad Series
| model6 = Core 2 Extreme Series
| model6 = Core 2 Extreme Series
| model7 = Xeon Series
| model7 = Xeon Series -->
| cores = 1-4 (1-4)
| cores = 1-4 (2-6 Xeon)
| cores2 = 2-6 (2-6) (Xeon)
<!-- | cores2 = 2-6 (2-6) (Xeon) -->
| transistors = 228M [[45 nanometer|45 nm]] (R0)
| transistors = 228M to 820M [[45 nanometer|45 nm]]
<!-- (R0)
| transistors1 = 410M [[45 nanometer|45 nm]] (C0, E0)
| transistors1 = 410M [[45 nanometer|45 nm]] (C0, E0)
| transistors2 = 456M [[45 nanometer|45 nm]] (R0, M0, M1)
| transistors2 = 456M [[45 nanometer|45 nm]] (R0, M0, M1)
| transistors3 = 820M [[45 nanometer|45 nm]] (C0, C1, E0)
| transistors3 = 820M [[45 nanometer|45 nm]] (C0, C1, E0) -->
| clock = 1.06 GHz to 3.33 GHz
| clock = 1.06 GHz to 3.33 GHz
| l1cache = 64 KB per core
| l1cache = 64 KB per core
| l2cache = 3 MB to 12 MB unified
| l2cache = 1 MB to 12 MB unified
| l3cache = 8 MB to 16 MB shared (Xeon)
| l3cache = 8 MB to 16 MB shared (Xeon)
| fsb = 533 MT/s to 1600 MT/s
| fsb = 533 MT/s to 1600 MT/s
| arch1 = [[Intel Core]] [[x86]]
| arch = [[x86-64]]
| instructions = [[MMX (instruction set)|MMX]]
| microarch = [[Intel Core (microarchitecture)|Core]]
| extensions = [[x86-64]], [[Intel 64]]
| instructions = [[x86]], [[x86-64]]
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]]
| extensions2 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| extensions1 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| sock1 = [[Socket M]] (µPGA 478)
| sock1 = [[Socket M]] (µPGA 478)
| sock2 = [[Socket P]] (µPGA 478)
| sock2 = [[Socket P]] (µPGA 478)
| sock3 = [[Socket T]] ([[LGA 775]])
| sock3 = [[Socket T]] ([[LGA 775]])
| sock4 = [[Micro-FCBGA|FCBGA]] (µBGA 479)
| sock4 = [[Micro-FCBGA|FCBGA]] (μBGA 479)
| sock5 = [[Micro-FCBGA|FCBGA]] (µBGA 965)
| sock5 = [[Micro-FCBGA|FCBGA]] (μBGA 965)
| predecessor = [[Intel Core (microarchitecture)|Intel Core]]
| predecessor = [[Core (microarchitecture)|Core]]
| successor = [[Nehalem (microarchitecture)|Nehalem]]
| successor = [[Nehalem (microarchitecture)|Nehalem]]
|image=
| support status = Unsupported
}}
}}
{{Infobox CPU
{{Infobox CPU
| name = Nehalem
| name = Nehalem
| image =
| image =
| caption = Logo for Core i7 Bloomfield processors
| image_size = 150px
| image_size = 150px
| created = November 2008
| created = {{start date and age|November 11, 2008}}
| model = Celeron Series
| model = Pentium, Core, Core i''n'' and Xeon Series
| model1 = Pentium Series
<!-- | model1 = Pentium Series
| model2 = Core i3 Series
| model2 = Core i5 7xx Series
| model3 = Core i5 Series
| model3 = Core i7 8xx/9xx Series
| model4 = Core i7 Series
| model4 = Core i7 9xx Extreme Series
| model5 = Core i7 Extreme Series
| model5 = Xeon Series -->
| model6 = Xeon Series
| cores = 2-6 (4-8 Xeon)
| cores = 2-6 (2-12)
<!-- (2-12)
| cores1 = 6 (12) (Extreme)
| cores1 = 6 (12) (Extreme)
| cores2 = 4-8 (4-16) (Xeon)
| cores2 = 4-8 (4-16) (Xeon) -->
| transistors = 731M [[45 nanometer|45 nm ]] (C0, D0)
| transistors = 731M to 2300M [[45 nanometer|45 nm]]
<!-- (C0, D0)
| transistors1 = 774M [[45 nanometer|45 nm]] (B0, B1)
| transistors1 = 774M [[45 nanometer|45 nm]] (B0, B1)
| transistors2 = 2,300M [[45 nanometer|45 nm]] (D0)
| transistors2 = 2,300M [[45 nanometer|45 nm]] (D0) -->
| clock = 1.06 GHz to 3.33 GHz
| clock = 1.06 GHz to 3.33 GHz
| l1cache = 64KB per core
| l1cache = 64 KB per core
| l2cache = 256KB per core
| l2cache = 256 KB per core
| l3cache = 4MB to 12MB shared
| l3cache = 2 MB to 24 MB shared
| dmi = 2.50GT/s
| dmi-slowest = 2.50
| qpi = 4.80GT/s to 6.40GT/s
| qpi-slowest = 4.80
| qpi-fastest = 6.40
| gpu =
| gpu =
| arch = [[x86-64]]
| arch1 = [[Nehalem (microarchitecture)|Nehalem]] [[x86]]
| microarch = Nehalem
| extensions = [[x86-64]], [[Intel 64]]
| instructions = [[MMX (instruction set)|MMX]]
| extensions1 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| instructions = [[x86]], [[x86-64]]
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| extensions2 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| sock1 = [[LGA 1156]]
| sock1 = [[LGA 1156]]
| sock2 = [[LGA 1366]]
| sock2 = [[LGA 1366]]
| sock3 = [[LGA 1567]]
| sock3 = [[LGA 1567]]
| sock4 = [[µPGA 988]]
| sock4 = [[Socket G1|µPGA 988]]
| predecessor = [[Intel Core (microarchitecture)|Intel Core (tock)]]<br>[[Penryn (microarchitecture)|Penryn (tick)]]
| predecessor = [[Core (microarchitecture)|Core (tock)]]<br />[[Penryn (microarchitecture)|Penryn (tick)]]
| successor = [[Westmere (microarchitecture)|Westmere (tick)]]<br>[[Sandy Bridge (microarchitecture)|Sandy Bridge (tock)]]
| successor = [[Westmere (microarchitecture)|Westmere (tick)]]<br />[[Sandy Bridge|Sandy Bridge (tock)]]
|size-from=[[45 nm]]
| support status = Unsupported
}}
}}
{{Infobox CPU
{{Infobox CPU
Line 789: Line 945:
| image =
| image =
| image_size = 150px
| image_size = 150px
| created = January 7, 2010
| created = {{start date and age|January 7, 2010}}
| model = Celeron Series
| model = Core i''n'', Xeon
| cores = 2-6 (4-10 Xeon)
| model1 = Pentium Series
<!-- | cores1 = 6 (12) (Extreme)
| model2 = Core i3 Series
| model3 = Core i5 Series
| cores2 = 4-10 (4-20) (Xeon) -->
| transistors = 382M to 2600M [[32 nanometer|32nm]]
| model4 = Core i7 Series
<!-- (C2)
| model5 = Core i7 Extreme Series
| model6 = Xeon Series
| cores = 2-6 (2-12)
| cores1 = 6 (12) (Extreme)
| cores2 = 4-10 (4-20) (Xeon)
| transistors = 382M [[32 nanometer|32nm]] (C2)
| transistors1 = 1,170M [[32 nanometer|32nm]] (B1)
| transistors1 = 1,170M [[32 nanometer|32nm]] (B1)
| transistors2 = 2,600M [[32 nanometer|32nm]] (A2)
| transistors2 = 2,600M [[32 nanometer|32nm]] (A2) -->
| clock = 1.06 GHz to 3.46 GHz
| clock = 1.06 GHz to 3.46 GHz
| l1cache = 64KB per core
| l1cache = 64 KB per core
| l2cache = 256KB per core
| l2cache = 256 KB per core
| l3cache = 4MB to 30MB shared
| l3cache = 2 MB to 30 MB shared
| dmi = 2.50GT/s
| dmi-slowest = 2.50
| qpi = 4.80GT/s to 6.40GT/s
| qpi-slowest = 4.80
| qpi-fastest = 6.40
| gpu = 533 MHz to 900 MHz<br>177M [[45 nanometer|45nm]] (K0)
| gpu = 533 MHz to 900 MHz<br>177M [[45 nanometer|45nm]] (K0)
| arch = [[x86-64]]
| arch1 = [[Nehalem (microarchitecture)|Nehalem]] [[x86]]
| microarch = [[Nehalem (microarchitecture)|Nehalem]]
| instructions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]]
| extensions = [[x86-64]], [[Intel 64]]
| instructions = [[IA-32]], [[x86-64]]
| extensions = [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]]
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| extensions1 = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| extensions2 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| extensions2 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| sock1 = [[LGA 1156]]
| sock1 = [[LGA 1156]]
| sock2 = [[LGA 1366]]
| sock2 = [[LGA 1366]]
| sock3 = [[LGA 1567]]
| sock3 = [[LGA 1567]]
| sock4 = [[µPGA 988]]
| sock4 = [[rPGA988A]]
| predecessor = [[Nehalem (microarchitecture)|Nehalem]]
| predecessor = [[Nehalem (microarchitecture)|Nehalem]]
| successor = [[Sandy Bridge (microarchitecture)|Sandy Bridge]]
| successor = [[Sandy Bridge]]
| support status = Unsupported
}}
}}
{{Infobox CPU
{{Infobox CPU
| name = Sandy Bridge
| name = Sandy Bridge
| image =
| image =
| created = {{start date and age|January 9, 2011}}
| image_size = 150px
| produced-end = September 27, 2013 <ref>{{Cite web |last= Shvets |first=Gennadiy |date=September 26, 2012 |title=Intel discontinues second-generation Core i5 and i7 CPUs |url=http://www.cpu-world.com/news_2012/2012092601_Intel_discontinues_second-generation_Core_i5_and_i7_CPUs.html |access-date=2020-07-29 |website=CPU World}}</ref>
| created = January 2011
| model = Celeron Series<br />Pentium Series<br />Core i3/i5/i7/i7 Extreme Series<br />[[Intel Sandy Bridge-based Xeon microprocessors|Xeon E3/E5 Series]]
| model = Celeron Series
| cores = 1–4 (4-6 Extreme, 2-8 Xeon)
| model1 = Pentium Series
<!-- (2–8)
| model2 = Core i3 Series
| cores1 = 4–6 (8–12) (Extreme)
| model3 = Core i5 Series
| cores2 = 2–8 (4–16) (Xeon) -->
| model4 = Core i7 Series
| code = 80619 (extreme desktop)<br />80620 (server LGA1356)<br />80621 (server LGA2011)<br />80623 (desktop)<br />80627 (mobile)
| model5 = Core i7 Extreme Series
| transistors = 504M to 2.27B [[32 nanometer|32nm]]
| model6 = Xeon E3 Series
<!-- (Q0)
| model7 = Xeon E5 Series
| transistors1 = 624 M [[32 nanometer|32nm]] (J1)
| cores = 1-4 (2-8)
| transistors2 = 1,160 M [[32 nanometer|32nm]] (D2)
| cores1 = 4-6 (8-12) (Extreme)
| transistors3 = 1,270 M [[32 nanometer|32nm]] (M0, M1)
| cores2 = 2-8 (4-16) (Xeon)
| transistors = 504M [[32 nanometer|32nm]] (Q0)
| transistors4 = 2,270 M [[32 nanometer|32nm]] (C1, C2) -->
| slowest = 1.60
| transistors1 = 624M [[32 nanometer|32nm]] (J1)
| fastest = 3.60
| transistors2 = 1,160M [[32 nanometer|32nm]] (D2)
| transistors3 = 1,270M [[32 nanometer|32nm]] {M0, M1)
| l1cache = 64&nbsp;[[Kibibyte|KB]] per core
| l2cache = 256&nbsp;KB per core
| transistors4 = 2,270M [[32 nanometer|32nm]] (C1, C2)
| l3cache = 1&nbsp;MB to 8&nbsp;MB shared<br />10&nbsp;MB to 15&nbsp;MB (Extreme)<br />3&nbsp;MB to 20&nbsp;MB (Xeon)
| clock = 1.60 GHz to 3.60 GHz
| l1cache = 64KB per core
| dmi-slowest = 5.00 GT/s
| gpu = [[Intel HD Graphics|HD Graphics]]<br />650&nbsp;[[Hertz|MHz]] to 1100&nbsp;MHz<br />[[Intel HD Graphics|HD Graphics 2000]]<br />650&nbsp;[[Hertz|MHz]] to 1250&nbsp;MHz<br />[[Intel HD Graphics|HD Graphics 3000]]<br />650&nbsp;MHz to 1350&nbsp;MHz<br />[[Intel HD Graphics|HD Graphics P3000]]<br />850&nbsp;MHz to 1350&nbsp;MHz
| l2cache = 256KB per core
| arch = [[x86-64]]
| l3cache = 3MB to 8MB shared<br>10MB to 15MB (Extreme)<br>3MB to 20MB (Xeon)
| microarch = Sandy Bridge
| dmi = 5.00GT/s
| instructions = [[x86]], [[x86-64]]
| gpu = [[Intel_HD_Graphics|HD Graphics 2000]]<br>650 MHz to 1250 MHz
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]]
| gpu1 = [[Intel_HD_Graphics|HD Graphics 3000]]<br>650 MHz to 1350 MHz
| extensions1 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| gpu2 = [[Intel_HD_Graphics|HD Graphics P3000]]<br>850 MHz to 1350 MHz
| extensions2 = [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[Trusted Execution Technology|TXT]]
| arch1 = [[Sandy Bridge (microarchitecture)|Sandy Bridge]] [[x86]]
| sock1 = [[LGA 1155]] (desktops and workstations)
| instructions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]]
| extensions = [[x86-64]], [[Intel 64]]
| sock2 = [[LGA 2011]] (high-end servers)
| sock3 = [[LGA 1356]] (low-end, dual-processor servers)
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| sock4 = [[Socket G2]]
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Trusted Execution Technology|TXT]], [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| sock1 = [[LGA 1155]]
| sock5 = [[BGA-1023]]
| sock2 = [[LGA 2011]]
| sock6 = [[BGA-1224]]
| predecessor = [[Nehalem (microarchitecture)|Nehalem]] (Tock)<br />[[Westmere (microarchitecture)|Westmere]] (Tick)
| sock3 = [[rPGA988B]]
| successor = [[Ivy Bridge (microarchitecture)|Ivy Bridge]] (Tick)<br />[[Haswell (microarchitecture)|Haswell]] (Tock)
| sock4 = [[BGA-1023]]
| sock5 = [[BGA-1224]]
|sock7=[[BGA-1284]]
| support status = Unsupported
| predecessor = [[Nehalem (microarchitecture)|Nehalem (tock)]]<br>[[Westmere (microarchitecture)|Westmere (tick)]]
| successor = [[Ivy Bridge (microarchitecture)|Ivy Bridge (tick)]]<br>[[Haswell (microarchitecture)|Haswell (tock)]]
}}
}}
{{Infobox CPU
{{Infobox CPU
| name = Ivy Bridge
| name = Ivy Bridge
| image =
| image = Ivy Bridge Codename Logo.jpg
| caption = Intel's internal Ivy Bridge logo<ref>{{cite web |title=Origin of a Codename: Ivy Bridge |url=http://www.intelfreepress.com/news/origin-of-a-codename-ivy-bridge/48 |website=Intel Free Press |language=en-US |date=April 19, 2012 |access-date=January 16, 2014 |url-status=dead |archive-url=https://web.archive.org/web/20140116133839/http://www.intelfreepress.com/news/origin-of-a-codename-ivy-bridge/48 |archive-date=January 16, 2014 |df=dmy-all}}</ref>
| image_size = 150px
| image_size = 240px
| created = April 29, 2012
| produced-start = {{Start date and age|April 29, 2012}}
| model = Pentium G Series
| produced-end = {{End date and age|June 5, 2015}}
| model1 = Core i3 Series
| soldby = [[Intel]]
| model2 = Core i5 Series
| designfirm = [[Intel]]
| model3 = Core i7 Series
| manuf1 = [[Intel]]
| model4 = Xeon E3 v2 Series
| size-from = [[Intel]] [[22 nm process|22 nm]]
| cores = 2-4 (4-8)
| model = Celeron G Series
| transistors = 624M [[22 nanometer|22nm]] (L1)
| model1 = Pentium G Series
| transistors1 = 1,480M [[22 nanometer|22nm]] (E1, N0)
| model2 = Core i3 Series
| clock = 1.70 GHz to 3.80 GHz
| l1cache = 64KB per core
| model3 = Core i5 Series
| model4 = Core i7 Series
| l2cache = 256KB per core
| model5 = [[Intel Ivy Bridge–based Xeon microprocessors|Xeon E3/E5/E7 v2 Series]]
| l3cache = 3MB to 8MB shared
| cores = 2–4 (Mainstream) <br/> 2–15 (Xeon)
| cpuid = 0306A9h
| transistors = 2.104B
| code = 80637 (desktop)
| clock = 1.4 to 4.1{{nbsp}}GHz
| code1 = 80638 (mobile)
| l1cache = 64{{nbsp}}[[Kibibyte|KB]] per core
| dmi = 5.00GT/s
| l2cache = 256{{nbsp}}KB per core
| gpu = [[Intel_HD_Graphics|HD Graphics 2500]]<br>650 MHz to 1150 MHz
| l3cache = 2 to 8{{nbsp}}MB shared
| gpu1 = [[Intel_HD_Graphics|HD Graphics 4000]]<br>350 MHz to 1300 MHz
| cpuid = 0306A9h
| gpu2 = [[Intel_HD_Graphics|HD Graphics P4000]]<br>650 MHz to 1250 MHz
| code = 80633 (extreme desktop) <br/> 80634 (server LGA1356) <br/> 80635 (server E5 LGA2011) <br/> 80636 (server E7 LGA2011) <br/> 80637 (desktop) <br/> 80638 (mobile)
| arch1 = [[Sandy Bridge (microarchitecture)|Sandy Bridge]] [[x86]]
| dmi-slowest = 5.00
| instructions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]]
| gpu = [[Intel HD Graphics|HD Graphics 2500]]<br />650 to 1150 MHz<br />[[Intel HD Graphics|HD Graphics 4000]]<br />350 to 1300 MHz<br />[[Intel HD Graphics|HD Graphics P4000]]<br />650 to 1250 MHz
| extensions = [[x86-64]], [[Intel 64]]
| arch = [[x86-64]]
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| microarch = [[Sandy Bridge]]
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Trusted Execution Technology|TXT]], [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| sock1 = [[LGA 1155]]
| instructions = [[x86]], [[x86-64]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[F16C]]
| sock2 = [[rPGA988B]]
| extensions1 = [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[Trusted Execution Technology|TXT]]
| sock3 = [[BGA-1023]]
| extensions2 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| sock4 = [[BGA-1224]]
| sock1 = '''Desktop & Workstation''' {{bulleted list |[[LGA 1155]] |[[LGA 2011]] |<br>}}
| predecessor = [[Sandy Bridge (microarchitecture)|Sandy Bridge]]
| sock2 = '''Server''' {{bulleted list |[[LGA 2011]] |[[LGA 2011|LGA 2011-1]] |[[LGA 1356]] |<br>}}
| successor = [[Haswell (microarchitecture)|Haswell]]
| sock3 = '''Mobile''' {{bulleted list |[[Socket G2]] |[[BGA 1023]] |[[BGA 1224]] |[[BGA 1284]]}}
| brand1 = [[Celeron]]
| brand2 = [[Pentium]]
| brand3 = [[Intel Core|Core]]
| brand4 = [[Xeon]]
| predecessor = [[Sandy Bridge]] (Tock)
| successor = [[Haswell (microarchitecture)|Haswell]] (Tock/Architecture)
| support status = Unsupported
}}
}}
{{Infobox CPU
{{Infobox CPU
| name = Haswell
| name = Haswell
| image =
| image = Haswell Chip.jpg
| caption = A Haswell [[Wafer (electronics)|wafer]] with several [[Die (integrated circuit)|dies]], with a pin for scale
| image_size = 150px
| produced-start = {{start date and age|June 4, 2013}}
| model = Core i3 Series
| produced-end =
| model1 = Core i5 Series
| brand1 = {{unbulleted list|Core i3|Core i5|Core i7|Xeon E3 v3|Xeon E5 v3|Xeon E7 v3|Pentium|Celeron}}
| model2 = Core i7 Series
| model = {{unbulleted list|Haswell|Haswell Refresh|Haswell-E|Haswell-EP|Haswell-EX}}
| created = 2013
| numcores = {{unbulleted list|2–4&nbsp;(mainstream)|6–8&nbsp;(enthusiast)|2–18&nbsp;(Xeon)}}
| cores = 2-4
| size-from = [[22 nanometer|22 nm]] ([[FinFET|Tri-Gate]])
| cores1 = 6+ (Extreme)
| cores2 = 8+ (Xeon)
| size-to =
| l1cache = 64&nbsp;[[Kibibyte|KB]] per core
| transistors = [[22 nanometer|22 nm]] transistors
| l2cache = 256&nbsp;KB per core
| clock =
| l3cache = 2–45&nbsp;[[Mebibyte|MB]] (shared)
| l1cache =
| l4cache = 128&nbsp;MB of [[eDRAM]] (Iris Pro models only)
| l2cache =
| l3cache =
| cpuid = 0306C3h
| code = {{unbulleted list|80646 (desktop [[LGA 1150]])|80647 (mobile [[Intel Socket G3|Socket G3]])|80648 (desktop [[LGA 2011|LGA 2011-3]])|80644 (server LGA 2011-3)}}
| llcache = 35MB
| dmi =
| dmi =
| gpu = {{unbulleted list|[[Intel HD Graphics|HD Graphics]] 4200|HD Graphics 4400|HD Graphics 4600|HD Graphics 5000|Iris 5100|Iris Pro 5200}}
| gpu =
| arch1 = [[Haswell (microarchitecture)|Haswell]] [[x86]]
| arch = [[x86-64]]
| microarch = Haswell
| instructions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[FMA instruction set|FMA3]]
| extensions = [[x86-64]], [[Intel 64]]
| instructions = [[x86]], [[x86-64]]
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| extensions = [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[Trusted Execution Technology|TXT]]
| extensions1 = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[FMA instruction set|FMA3]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2#Advanced Vector Extensions 2|AVX2]], and [[Transactional Synchronization Extensions|TSX]] (disabled via [[microcode]], except for Haswell-EX)
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Advanced_Vector_Extensions_2#Advanced_Vector_Extensions_2|AVX2]], [[Trusted Execution Technology|TXT]], [[Transactional_Synchronization_Extensions|TSX]]
| extensions3 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| extensions3 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| sock1 = [[LGA 1150]]
| sock1 = [[LGA 1150]]
| sock2 = [[rPGA947]]
| sock2 = [[rPGA 947]]
| sock3 = [[BGA-1364]]
| sock3 = BGA 1364
| sock4 = BGA 1168
| predecessor = [[Sandy Bridge (microarchitecture)|Sandy Bridge (tock)]]
| sock5 = [[LGA 2011-v3]]
| predecessor2 = [[Ivy Bridge (microarchitecture)|Ivy Bridge (tick)]]
| successor = [[Broadwell (microarchitecture)|Broadwell (tick)]]
| predecessor = [[Sandy Bridge]] (Tock)<br>[[Ivy Bridge (microarchitecture)|Ivy Bridge]] ([[Tick–tock model|Tick]])
| successor2 = [[Skylake (microarchitecture)|Skylake (tock)]]
| successor = [[Broadwell (microarchitecture)|Broadwell]] (Tick/Process)<br>[[Skylake (microarchitecture)|Skylake]] (Tock)
| support status = Unsupported
}}
}}
{{Infobox CPU
{{Infobox CPU
| name = Broadwell
| name = Broadwell
| image =
| image_size =
| produced-start = {{start date and age|October 27, 2014}}
| image_size = 150px
| produced-end = November 2018<ref>{{Cite web |last=Perillo |first=Ron |date=November 9, 2017 |title=Intel Broadwell-E CPUs Officially Discontinued |url=https://www.eteknix.com/intel-broadwell-e-cpus-officially-discontinued/ |access-date=2020-07-29 |website=eTeknix}}</ref>
| model = Core i3 Series<br>Core i5 Series<br>Core i7 Series
| size-from = [[14 nanometer|14 nm]] ([[FinFET|Tri-Gate]])
| created = 2014
| cores =
| size-to =
| cpuid = 0306D4h
| transistors = [[14 nanometer|14 nm transistors]]
| code = {{Unbulleted list|80658 (mainstream desktop/mobile, Xeon E3)|80660 (Xeon E5)|80669 (Xeon E7)|80671 (enthusiast desktop)|80674 (Xeon D)|80682 (Xeon D, Hewitt Lake)}}
| clock =
| l1cache =
| model =
| brand1 = {{unbulleted list|[[Core i3]]|[[Core i5]]|[[Core i7]]|[[List of Intel Core M microprocessors|Core M]]|[[Celeron]]|[[Pentium]]|[[Xeon]]}}
| l2cache =
| numcores = {{unbulleted list|2–4&nbsp;(mainstream)|6–10&nbsp;(enthusiast)|4–24&nbsp;(Xeon)}}
| l3cache =
| llcache = 35MB
| transistors =
| l1cache = 64 [[Kibibyte|KB]] per core
| dmi =
| l2cache = 256 KB per core
| gpu =
| l3cache = 2-6 [[Mebibyte|MB]] (shared)
| arch1 = [[Haswell (microarchitecture)|Haswell]] [[x86]]
| l4cache = 128 MB of [[eDRAM]] (Iris Pro models only)
| instructions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[FMA instruction set|FMA3]]
| dmi =
| extensions = [[x86-64]], [[Intel 64]]
| gpu = {{unbulleted list|HD 5300|HD 5500|HD 5700P|HD 6000|HD 6100|HD 6200|HD 6300P|HD Graphics}}
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| arch = [[x86-64]]
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Advanced_Vector_Extensions_2#Advanced_Vector_Extensions_2|AVX2]], [[Trusted Execution Technology|TXT]], [[Transactional_Synchronization_Extensions|TSX]]
| microarch = [[Haswell (microarchitecture)|Haswell]]
| extensions3 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| extensions2 = [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[Trusted Execution Technology|TXT]]
| socket =
| instructions = [[x86]], [[x86-64]]
| predecessor = [[Haswell (microarchitecture)|Haswell]]
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2|AVX2]], [[Transactional Synchronization Extensions|TSX]], [[FMA instruction set|FMA3]]
| successor = [[Skylake (microarchitecture)|Skylake]]
| extensions3 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| socket =
| sock1 = [[LGA 1150]]
| sock2 = [[BGA 1364]]
| sock3 = [[LGA 2011-v3]]
| predecessor = {{unbulleted list|[[Haswell (microarchitecture)|Haswell]] (Tock/Architecture)|[[Haswell (microarchitecture)#Haswell Refresh|Haswell Refresh]] (Optimization)}}
| successor = [[Skylake (microarchitecture)|Skylake]] (Tock/Architecture)
| support status = Unsupported
}}
}}
{{Infobox CPU
{{Infobox CPU
| name = Skylake
| name = Skylake
| image = Intel_CPU_Core_i7_6700K_Skylake_perspective.jpg
| image =
| caption = Intel Core i7-6700K with four physical cores
| image_size = 150px
<!----------------- General Info ----------------->
| model = Core i3 Series<br>Core i5 Series<br>Core i7 Series
| produced-start = {{Start date and age|August 5, 2015}}
| created = expected 2015-2016
| produced-end = {{End date and age|March 4, 2019}} (desktop processors)
| cores =
| soldby = [[Intel]]
| transistors = [[14 nanometer|14 nm]] transistors
| designfirm = [[Intel]]
| clock =
| manuf1 = [[Intel]]
| l1cache =
| cpuid = 0406e3h, 0506e3h
| l2cache =
| code = {{Unbulleted list|80662 (mainstream and mobile Xeon E3)|80673 (enthusiast and server)}}
| l3cache =
<!-------------------- Cache --------------------->
| llcache =
| l1cache = 64{{nbsp}}KB per core
| dmi =
| l2cache = 256{{nbsp}}KB per core <br /> (1{{nbsp}}MB per core for Skylake-X)
| gpu =
| l3cache = Up to 2{{nbsp}}MB per core <br /> (1.375{{nbsp}}MB per core for Skylake-X)
| arch1 = Skylake [[x86]]
| l4cache = 128{{nbsp}}MB of [[eDRAM]] (on select models)
| instructions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[FMA instruction set|FMA3]]
<!------- Architecture and classification -------->
| extensions = [[x86-64]], [[Intel 64]]
| application =
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| size-from = [[14 nm process|14&nbsp;nm]] bulk silicon 3D transistors ([[FinFET|Tri-Gate]])
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Advanced_Vector_Extensions_2#Advanced_Vector_Extensions_2|AVX2]], [[Trusted Execution Technology|TXT]], [[Transactional Synchronization Extensions|TSX]]
| microarch = Skylake
| extensions3 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| arch = [[x86-64]]
| socket =
| extensions = [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[Intel MPX|MPX]], [[Trusted Execution Technology|TXT]], [[Software Guard Extensions|SGX]]<ref name=i7-6700k>{{cite web|url=https://ark.intel.com/products/88195/Intel-Core-i7-6700K-Processor-8M-Cache-up-to-4_20-GHz|title=Intel Core i7-6700K Processor (8M Cache, up to 4.20 GHz)|website=Ark.intel.com|access-date=January 24, 2018}}</ref>
| predecessor = [[Haswell (microarchitecture)|Haswell (tock)]]<br>[[Broadwell (microarchitecture)|Broadwell (tick)]]
| extensions1 = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Intel ADX|ADX]]
| successor = [[Cannonlake|Cannonlake (tick)]]
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2|AVX2]], [[AVX-512]] (SkyLake-SP, SkyLake-W & SkyLake-X<ref name=tomshardware_purley>[http://www.tomshardware.com/news/intel-xeon-skylake-purley-cpu,31980.html Tom's Hardware: Skylake Xeon Platforms Spotted, Purley Makes A Quiet Splash At Computex]. June 3, 2016</ref>), [[Transactional Synchronization Extensions|TSX]], [[FMA instruction set|FMA3]]
| extensions3 = [[VT-x]], [[VT-d]]
| instructions = [[x86-64]] ([[Intel 64]])
| sock1 = '''Desktop''' {{bulleted list |[[LGA 1151]] |[[LGA 2066]] |<br>}}
| sock2 = '''Server & Workstation''' {{bulleted list |[[LGA 3647]] |[[LGA 2066]] |<br>}}
| sock3 = '''Mobile''' {{bulleted list |BGA 1168 |BGA 1356 |BGA 1515 |BGA 1440<ref>{{cite web |last1=Cutress |first1=Ian |date=August 5, 2015 |title=The Intel Skylake Mobile and Desktop Launch, with Architecture Analysis |url=http://www.anandtech.com/show/9582/intel-skylake-mobile-desktop-launch-architecture-analysis/4 |website=AnandTech |language=en-US |access-date=September 18, 2015}}</ref>}}
<!----------- Physical specifications ------------>
| numcores = 2–28
| clock = Up to 4.5&nbsp;GHz
<!--------- Products, models, variants ----------->
| brand1 = {{unbulleted list|Core i3|Core i5|Core i7|Core i9|Core m3|Core m5|Core m7|Xeon|Celeron|Pentium}}
<!------------------ History ------------------->
| predecessor = [[Broadwell (microarchitecture)|Broadwell]] (Tick/Process)
| successor = {{ubl|[[Kaby Lake]] (Optimization)|[[Cascade Lake (microprocessor)|Cascade Lake-SP]] (Skylake-SP)|[[Palm Cove (microarchitecture)|Palm Cove]] (Process)}}
| support status = Client: Legacy support for iGPU <br /> Xeon E3: Legacy support for iGPU<br />Other Xeon: supported
}}
}}
{{Infobox CPU
{{Infobox CPU
| name = Cannonlake
| name = Cannon Lake
| created = {{Start date and age|May 15, 2018}}
| model = Core i3 Series<br>Core i5 Series<br>Core i7 Series
| produced-end = {{End date and age|February 28, 2020}}
| created = 2016
| soldby = [[Intel]]
| cores =
| designfirm = [[Intel]]
| transistors = [[10 nanometer|10 nm transistors]]
| manuf1 = [[Intel]]
| clock =
| size-from = [[Intel]] [[10 nanometer|10 nm]] ([[FinFET|tri-gate]]) transistors
| l1cache =
| clock = 3.2{{nbsp}}GHz
| l2cache =
| l1cache = 64{{nbsp}}KB per core
| l3cache =
| l2cache = 256{{nbsp}}KB per core
| llcache =
| l3cache = 2{{nbsp}}MB per core
| dmi =
| arch = [[x86-64]]
| gpu =
| instructions = [[x86-64]], [[Intel 64]]
| arch1 = [[Skylake (microarchitecture)|Skylake]] [[x86]]
| extensions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[FMA instruction set|FMA3]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2#Advanced Vector Extensions 2|AVX2]], [[AVX-512]], [[Intel SHA extensions|SHA]],<ref name=":0">{{cite web |last=Kirsch |first=Nathan |date=February 21, 2016 |title=Intel Cannonlake Added To LLVM's Clang – AVX-512 |url=http://www.legitreviews.com/intel-cannonlake-added-to-llvms-clang_179210 |work=Legit Reviews |access-date=October 23, 2016 |archive-url=https://web.archive.org/web/20161023135525/http://www.legitreviews.com/intel-cannonlake-added-to-llvms-clang_179210 |archive-date=2016-10-23 |url-status=dead}}</ref> [[Trusted Execution Technology|TXT]], [[Transactional Synchronization Extensions|TSX]], [[Software Guard Extensions|SGX]], [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| instructions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[FMA instruction set|FMA3]]
| numcores = 2
| extensions = [[x86-64]], [[Intel 64]]
| gpu = Factory disabled
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| sock1 = BGA 1440
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Advanced_Vector_Extensions_2#Advanced_Vector_Extensions_2|AVX2]], [[Trusted Execution Technology|TXT]], [[Transactional_Synchronization_Extensions|TSX]]
| extensions3 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| brand1 = [[Intel Core|Core]]
| predecessor = Desktop: [[Coffee Lake]] (2nd optimization)<br>[[Kaby Lake Refresh]] (2nd optimization)
| socket =
| successor = [[Ice Lake (microprocessor)|Ice Lake]] (architecture)
| predecessor = [[Skylake (microarchitecture)|Skylake]]
| microarch = [[Palm Cove (microarchitecture)|Palm Cove]]
| successor =
| support status = Legacy support for iGPU
}}
{{Infobox CPU
| name = Apple A11 Bionic
| image = Apple A11.jpg
| caption =
| produced-start = September 12, 2017
| produced-end = present
| slowest =
| slow-unit =
| fastest = 2.39 GHz
| fast-unit =
| size-from = 10 nm
| size-to =
| soldby =
| designfirm = [[Apple Inc.]]
| manuf1 = [[TSMC]]
| arch = [[ARM architecture#64/32-bit architecture|A64]]
| microarch = [[ARMv8-A|ARMv8&#8209;A]] compatible
| code = APL1W72
| numcores = 6
| core1 = Monsoon
| core2 = Mistral
| l1cache =32 KB instruction, 32 KB data
| l2cache =8 MB
| l3cache =none
| application = Mobile
| gpu = Apple-designed 3 core
| predecessor = [[Apple A10 Fusion]]
| successor =
| variant =
| product1 = test1
}}
}}
|}
|}

Latest revision as of 09:00, 28 March 2023

Testing sandbox version

[edit]

{{Infobox CPU/sandbox}}

MOS Technology 6502
A MOS 6502 processor in a DIP-40 plastic package. The four-digit date code indicates it was made in the 45th week of 1985
General information
Launched1975; 50 years ago (1975)
Common manufacturer(s)
Performance
Max. CPU clock rate1 MHz to 2 MHz
Data width8
Address width16
Architecture and classification
Instruction setMOS 6502
Instructions56
Physical specifications
Package(s)
Infobox CPU/testcases
An Intel A80286-8 processor with a gray ceramic heat spreader
General information
LaunchedFebruary 1982
Discontinued1991[1]
Common manufacturer(s)
Performance
Max. CPU clock rate4 MHz to 25 MHz
FSB speeds4 MHz to 25 MHz
Data width16 bits
Address width24 bits
Architecture and classification
Technology node1.5 µm[2]
Instruction setx86-16 (with MMU)
Physical specifications
Transistors
Co-processorIntel 80287
Package(s)
Socket(s)
  • PGA68
  • PLCC-68
  • LCC-68
History
Predecessor8086, 8088 (while 80186 was contemporary)
SuccessorIntel 80386
Support status
Unsupported
Pentium (i586)
General information
LaunchedMarch 22, 1993
DiscontinuedJuly 15, 1999[4][better source needed]
Performance
Max. CPU clock rate60–300 MHz
FSB speeds50–66 MHz
Cache
L1 cache16–32 KiB
Architecture and classification
MicroarchitectureP5
Instruction setIA-32
Extensions
Physical specifications
Transistors
  • 3.1M 0.8 μm (P5)
  • 3.2M 0.6 μm (P54C)
  • 3.3M 350 nm (P54CS)
  • 4.5M 350 nm (P55C)
Cores
  • 1
Socket(s)
Products, models, variants
Model(s)
  • Pentium series
  • Pentium OverDrive series
  • Pentium MMX series
History
Predecessori486
SuccessorP6, Pentium II
Support status
Unsupported
P6
Die shot of Deschutes core
General information
LaunchedNovember 1, 1995; 29 years ago (November 1, 1995)
Performance
Max. CPU clock rate150[5] MHz to 1.40 GHz
FSB speeds66 MHz to 133 MHz
Cache
L1 cachePentium Pro: 16 KB (8 KB I cache + 8 KB D cache)
Pentium II/III: 32 KB (16 KB I cache + 16 KB D cache)
L2 cache128 KB to 512 KB
256 KB to 2048 KB (Xeon)
Architecture and classification
MicroarchitectureP6
Instruction setx86
Extensions
  • MMX (Pentium II/III)
    SSE (Pentium III)
Physical specifications
Transistors
Cores
  • 1
Socket(s)
Products, models, variants
Model(s)
  • Celeron Series
  • Pentium II Series
  • Pentium III Series
  • Pentium Pro Series
  • Pentium II Xeon Series
  • Pentium III Xeon Series
Variant(s)
  • Pentium M
  • Enhanced Pentium M
History
PredecessorP5
SuccessorNetBurst, Pentium M
Support status
Unsupported
P6 Pentium M
General information
LaunchedMarch 12, 2003
Performance
Max. CPU clock rate600 MHz to 2.26 GHz
FSB speeds400 MT/s to 533 MT/s
Cache
L1 cache64KB (32 KB I Cache + 32 KB D cache)
L2 cache512 KB to 2048 KB
Architecture and classification
MicroarchitectureP6
Instruction setx86
Extensions
Physical specifications
Transistors
Cores
  • 1
Socket(s)
Products, models, variants
Model(s)
  • A100 Series
  • EP80579 Series
  • Celeron M Series
  • Pentium M Series
History
PredecessorNetBurst
SuccessorEnhanced Pentium M
Support status
Unsupported
P6 Enhanced Pentium M
General information
Launched2006
Performance
Max. CPU clock rate1.06 GHz to 2.33 GHz
FSB speeds533 MT/s to 667 MT/s
Cache
L1 cache64 KB
L2 cache1 MB to 2 MB
2 MB (Xeon)
Architecture and classification
MicroarchitectureP6
Instruction setx86
Extensions
Physical specifications
Transistors
Cores
  • 1-2
Socket(s)
Products, models, variants
Model(s)
  • Celeron M Series
  • Pentium Dual-Core Series
  • Core Solo Series
  • Core Duo Series
  • Xeon LV Series
History
PredecessorPentium M
SuccessorIntel Core
Support status
Unsupported
NetBurst
General information
LaunchedNovember 20, 2000; 24 years ago (November 20, 2000)
Performance
Max. CPU clock rate1.3 GHz to 3.8 GHz
FSB speeds400 MT/s to 1066 MT/s
Cache
L1 cache8 KB to 16 KB per core
L2 cache128 KB to 2048 KB
L3 cache4 MB to 16 MB shared
Architecture and classification
MicroarchitectureNetBurst
Instruction setx86 (IA-32), x86-64 (some)
Extensions
Physical specifications
Transistors
Cores
  • 1-2 (2-4 threads with HT)
Socket(s)
Products, models, variants
Model(s)
  • Celeron Series
  • Celeron D Series
  • Pentium 4 Series
  • Pentium D Series
  • Xeon Series
History
PredecessorP6
SuccessorIntel Core
IA-64
Intel Core
General information
LaunchedJune 26, 2006; 18 years ago (June 26, 2006) (Xeon)
July 27, 2006; 18 years ago (July 27, 2006) (Core 2)
Performance
Max. CPU clock rate933 MHz to 3.5 GHz
FSB speeds533 MT/s to 1600 MT/s
Cache
L1 cache64 KB per core
L2 cache0.5 to 6 MB per two cores
L3 cache8 MB to 16 MB shared (Xeon 7400)
Architecture and classification
Technology node65 nm to 45 nm
MicroarchitectureCore
Instruction setx86-64
Instructionsx86, x86-64
Extensions
Physical specifications
Transistors
Cores
  • 1–4 (2-6 Xeon)
Socket(s)
Products, models, variants
Model(s)
History
PredecessorNetBurst
Enhanced Pentium M (P6)
SuccessorPenryn (tick)
(a version of Core)
Nehalem (tock)
Support status
Unsupported
Penryn
General information
LaunchedNovember 2007; 17 years ago (November 2007)
Performance
Max. CPU clock rate1.06 GHz to 3.33 GHz
FSB speeds533 MT/s to 1600 MT/s
Cache
L1 cache64 KB per core
L2 cache1 MB to 12 MB unified
L3 cache8 MB to 16 MB shared (Xeon)
Architecture and classification
MicroarchitectureCore
Instruction setx86-64
Instructionsx86, x86-64
Extensions
Physical specifications
Transistors
Cores
  • 1-4 (2-6 Xeon)
Socket(s)
Products, models, variants
Model(s)
  • P6 Family (Celeron, Pentium, Pentium Dual-Core, Core 2 range, Xeon)
History
PredecessorCore
SuccessorNehalem
Support status
Unsupported
Nehalem
General information
LaunchedNovember 11, 2008; 16 years ago (November 11, 2008)
Performance
Max. CPU clock rate1.06 GHz to 3.33 GHz
QPI speeds4.80 GT/s to 6.40 GT/s
DMI speeds2.50 GT/s
Cache
L1 cache64 KB per core
L2 cache256 KB per core
L3 cache2 MB to 24 MB shared
Architecture and classification
Technology node45 nm
MicroarchitectureNehalem
Instruction setx86-64
Instructionsx86, x86-64
Extensions
Physical specifications
Transistors
Cores
  • 2-6 (4-8 Xeon)
Socket(s)
Products, models, variants
Model(s)
  • Pentium, Core, Core in and Xeon Series
History
PredecessorCore (tock)
Penryn (tick)
SuccessorWestmere (tick)
Sandy Bridge (tock)
Support status
Unsupported
Westmere
General information
LaunchedJanuary 7, 2010; 14 years ago (January 7, 2010)
Performance
Max. CPU clock rate1.06 GHz to 3.46 GHz
QPI speeds4.80 GT/s to 6.40 GT/s
DMI speeds2.50 GT/s
Cache
L1 cache64 KB per core
L2 cache256 KB per core
L3 cache2 MB to 30 MB shared
Architecture and classification
MicroarchitectureNehalem
Instruction setx86-64
InstructionsIA-32, x86-64
Extensions
Physical specifications
Transistors
Cores
  • 2-6 (4-10 Xeon)
GPU(s)533 MHz to 900 MHz
177M 45nm (K0)
Socket(s)
Products, models, variants
Model(s)
  • Core in, Xeon
History
PredecessorNehalem
SuccessorSandy Bridge
Support status
Unsupported
Sandy Bridge
General information
LaunchedJanuary 9, 2011; 13 years ago (January 9, 2011)
DiscontinuedSeptember 27, 2013 [6]
Product code80619 (extreme desktop)
80620 (server LGA1356)
80621 (server LGA2011)
80623 (desktop)
80627 (mobile)
Performance
Max. CPU clock rate1.60 GHz to 3.60 GHz
DMI speeds5.00 GT/s GT/s
Cache
L1 cache64 KB per core
L2 cache256 KB per core
L3 cache1 MB to 8 MB shared
10 MB to 15 MB (Extreme)
3 MB to 20 MB (Xeon)
Architecture and classification
MicroarchitectureSandy Bridge
Instruction setx86-64
Instructionsx86, x86-64
Extensions
Physical specifications
Transistors
Cores
  • 1–4 (4-6 Extreme, 2-8 Xeon)
GPU(s)HD Graphics
650 MHz to 1100 MHz
HD Graphics 2000
650 MHz to 1250 MHz
HD Graphics 3000
650 MHz to 1350 MHz
HD Graphics P3000
850 MHz to 1350 MHz
Socket(s)
Products, models, variants
Model(s)
History
PredecessorNehalem (Tock)
Westmere (Tick)
SuccessorIvy Bridge (Tick)
Haswell (Tock)
Support status
Unsupported
Ivy Bridge
Intel's internal Ivy Bridge logo[7]
General information
LaunchedApril 29, 2012; 12 years ago (April 29, 2012)
DiscontinuedJune 5, 2015; 9 years ago (June 5, 2015)
Marketed byIntel
Designed byIntel
Common manufacturer(s)
CPUID code0306A9h
Product code80633 (extreme desktop)
80634 (server LGA1356)
80635 (server E5 LGA2011)
80636 (server E7 LGA2011)
80637 (desktop)
80638 (mobile)
Performance
Max. CPU clock rate1.4 to 4.1 GHz
DMI speeds5.00 GT/s
Cache
L1 cache64 KB per core
L2 cache256 KB per core
L3 cache2 to 8 MB shared
Architecture and classification
Technology nodeIntel 22 nm
MicroarchitectureSandy Bridge
Instruction setx86-64
Instructionsx86, x86-64
Extensions
Physical specifications
Transistors
  • 2.104B
Cores
  • 2–4 (Mainstream)
    2–15 (Xeon)
GPU(s)HD Graphics 2500
650 to 1150 MHz
HD Graphics 4000
350 to 1300 MHz
HD Graphics P4000
650 to 1250 MHz
Socket(s)
Products, models, variants
Model(s)
Brand name(s)
History
PredecessorSandy Bridge (Tock)
SuccessorHaswell (Tock/Architecture)
Support status
Unsupported
Haswell
A Haswell wafer with several dies, with a pin for scale
General information
LaunchedJune 4, 2013; 11 years ago (June 4, 2013)
CPUID code0306C3h
Product code
Cache
L1 cache64 KB per core
L2 cache256 KB per core
L3 cache2–45 MB (shared)
L4 cache128 MB of eDRAM (Iris Pro models only)
Architecture and classification
Technology node22 nm (Tri-Gate)
MicroarchitectureHaswell
Instruction setx86-64
Instructionsx86, x86-64
Extensions
Physical specifications
Cores
    • 2–4 (mainstream)
    • 6–8 (enthusiast)
    • 2–18 (Xeon)
GPU(s)
  • HD Graphics 4200
  • HD Graphics 4400
  • HD Graphics 4600
  • HD Graphics 5000
  • Iris 5100
  • Iris Pro 5200
Socket(s)
Products, models, variants
Model(s)
    • Haswell
    • Haswell Refresh
    • Haswell-E
    • Haswell-EP
    • Haswell-EX
Brand name(s)
    • Core i3
    • Core i5
    • Core i7
    • Xeon E3 v3
    • Xeon E5 v3
    • Xeon E7 v3
    • Pentium
    • Celeron
History
PredecessorSandy Bridge (Tock)
Ivy Bridge (Tick)
SuccessorBroadwell (Tick/Process)
Skylake (Tock)
Support status
Unsupported
Broadwell
General information
LaunchedOctober 27, 2014; 10 years ago (October 27, 2014)
DiscontinuedNovember 2018[8]
CPUID code0306D4h
Product code
  • 80658 (mainstream desktop/mobile, Xeon E3)
  • 80660 (Xeon E5)
  • 80669 (Xeon E7)
  • 80671 (enthusiast desktop)
  • 80674 (Xeon D)
  • 80682 (Xeon D, Hewitt Lake)
Cache
L1 cache64 KB per core
L2 cache256 KB per core
L3 cache2-6 MB (shared)
L4 cache128 MB of eDRAM (Iris Pro models only)
Architecture and classification
Technology node14 nm (Tri-Gate)
MicroarchitectureHaswell
Instruction setx86-64
Instructionsx86, x86-64
Extensions
Physical specifications
Cores
    • 2–4 (mainstream)
    • 6–10 (enthusiast)
    • 4–24 (Xeon)
GPU(s)
  • HD 5300
  • HD 5500
  • HD 5700P
  • HD 6000
  • HD 6100
  • HD 6200
  • HD 6300P
  • HD Graphics
Socket(s)
Products, models, variants
Brand name(s)
History
Predecessor
SuccessorSkylake (Tock/Architecture)
Support status
Unsupported
Skylake
Intel Core i7-6700K with four physical cores
General information
LaunchedAugust 5, 2015; 9 years ago (August 5, 2015)
DiscontinuedMarch 4, 2019; 5 years ago (March 4, 2019) (desktop processors)
Marketed byIntel
Designed byIntel
Common manufacturer(s)
CPUID code0406e3h, 0506e3h
Product code
  • 80662 (mainstream and mobile Xeon E3)
  • 80673 (enthusiast and server)
Performance
Max. CPU clock rateUp to 4.5 GHz
Cache
L1 cache64 KB per core
L2 cache256 KB per core
(1 MB per core for Skylake-X)
L3 cacheUp to 2 MB per core
(1.375 MB per core for Skylake-X)
L4 cache128 MB of eDRAM (on select models)
Architecture and classification
Technology node14 nm bulk silicon 3D transistors (Tri-Gate)
MicroarchitectureSkylake
Instruction setx86-64
Instructionsx86-64 (Intel 64)
Extensions
Physical specifications
Cores
  • 2–28
Socket(s)
Products, models, variants
Brand name(s)
    • Core i3
    • Core i5
    • Core i7
    • Core i9
    • Core m3
    • Core m5
    • Core m7
    • Xeon
    • Celeron
    • Pentium
History
PredecessorBroadwell (Tick/Process)
Successor
Support status
Client: Legacy support for iGPU
Xeon E3: Legacy support for iGPU
Other Xeon: supported
Cannon Lake
General information
LaunchedMay 15, 2018; 6 years ago (May 15, 2018)
DiscontinuedFebruary 28, 2020; 4 years ago (February 28, 2020)
Marketed byIntel
Designed byIntel
Common manufacturer(s)
Performance
Max. CPU clock rate3.2 GHz
Cache
L1 cache64 KB per core
L2 cache256 KB per core
L3 cache2 MB per core
Architecture and classification
Technology nodeIntel 10 nm (tri-gate) transistors
MicroarchitecturePalm Cove
Instruction setx86-64
Instructionsx86-64, Intel 64
Extensions
Physical specifications
Cores
  • 2
GPU(s)Factory disabled
Socket(s)
  • BGA 1440
Products, models, variants
Brand name(s)
History
PredecessorDesktop: Coffee Lake (2nd optimization)
Kaby Lake Refresh (2nd optimization)
SuccessorIce Lake (architecture)
Support status
Legacy support for iGPU
Apple A11 Bionic
General information
LaunchedSeptember 12, 2017
Discontinuedpresent
Designed byApple Inc.
Common manufacturer(s)
Product codeAPL1W72
Max. CPU clock rateto 2.39 GHz 
Cache
L1 cache32 KB instruction, 32 KB data
L2 cache8 MB
L3 cachenone
Architecture and classification
ApplicationMobile
Technology node10 nm
MicroarchitectureARMv8‑A compatible
Instruction setA64
Physical specifications
Cores
  • 6
GPU(s)Apple-designed 3 core
Products, models, variants
Core name(s)
  • Monsoon
  • Mistral
Product code name(s)
  • test1
History
PredecessorApple A10 Fusion

Testing main template

[edit]

{{Infobox CPU}}

Infobox CPU/testcases
An Intel A80286-8 processor with a gray ceramic heat spreader
General information
LaunchedFebruary 1982
Discontinued1991[13]
Common manufacturer
Performance
Max. CPU clock rate4 MHz to 25 MHz
FSB speeds4 MHz to 25 MHz
Data width16 bits
Address width24 bits
Architecture and classification
Technology node1.5 µm[14]
Instruction setx86-16 (with MMU)
Physical specifications
Transistors
Co-processorIntel 80287
Packages
Sockets
  • PGA68
  • PLCC-68
  • LCC-68
History
Predecessors8086, 8088 (while 80186 was contemporary)
SuccessorIntel 80386
Support status
Unsupported
Pentium (i586)
General information
LaunchedMarch 22, 1993
DiscontinuedJuly 15, 1999[4][better source needed]
Performance
Max. CPU clock rate60–300 MHz
FSB speeds50–66 MHz
Cache
L1 cache16–32 KiB
Architecture and classification
MicroarchitectureP5
Instruction setIA-32
Extensions
Physical specifications
Transistors
  • 3.1M 0.8 μm (P5)
  • 3.2M 0.6 μm (P54C)
  • 3.3M 350 nm (P54CS)
  • 4.5M 350 nm (P55C)
Cores
  • 1
Sockets
Products, models, variants
Models
  • Pentium series
  • Pentium OverDrive series
  • Pentium MMX series
History
Predecessori486
SuccessorsP6, Pentium II
Support status
Unsupported
P6
Die shot of Deschutes core
General information
LaunchedNovember 1, 1995; 29 years ago (November 1, 1995)
Performance
Max. CPU clock rate150[16] MHz to 1.40 GHz
FSB speeds66 MHz to 133 MHz
Cache
L1 cachePentium Pro: 16 KB (8 KB I cache + 8 KB D cache)
Pentium II/III: 32 KB (16 KB I cache + 16 KB D cache)
L2 cache128 KB to 512 KB
256 KB to 2048 KB (Xeon)
Architecture and classification
MicroarchitectureP6
Instruction setx86
Extensions
  • MMX (Pentium II/III)
    SSE (Pentium III)
Physical specifications
Transistors
Cores
  • 1
Sockets
Products, models, variants
Models
  • Celeron Series
  • Pentium II Series
  • Pentium III Series
  • Pentium Pro Series
  • Pentium II Xeon Series
  • Pentium III Xeon Series
Variant
  • Pentium M
  • Enhanced Pentium M
History
PredecessorP5
SuccessorsNetBurst, Pentium M
Support status
Unsupported
P6 Pentium M
General information
LaunchedMarch 12, 2003
Performance
Max. CPU clock rate600 MHz to 2.26 GHz
FSB speeds400 MT/s to 533 MT/s
Cache
L1 cache64KB (32 KB I Cache + 32 KB D cache)
L2 cache512 KB to 2048 KB
Architecture and classification
MicroarchitectureP6
Instruction setx86
Extensions
Physical specifications
Transistors
Cores
  • 1
Socket
Products, models, variants
Models
  • A100 Series
  • EP80579 Series
  • Celeron M Series
  • Pentium M Series
History
PredecessorNetBurst
SuccessorEnhanced Pentium M
Support status
Unsupported
P6 Enhanced Pentium M
General information
Launched2006
Performance
Max. CPU clock rate1.06 GHz to 2.33 GHz
FSB speeds533 MT/s to 667 MT/s
Cache
L1 cache64 KB
L2 cache1 MB to 2 MB
2 MB (Xeon)
Architecture and classification
MicroarchitectureP6
Instruction setx86
Extensions
Physical specifications
Transistors
Cores
  • 1-2
Socket
Products, models, variants
Models
  • Celeron M Series
  • Pentium Dual-Core Series
  • Core Solo Series
  • Core Duo Series
  • Xeon LV Series
History
PredecessorPentium M
SuccessorIntel Core
Support status
Unsupported
NetBurst
General information
LaunchedNovember 20, 2000; 24 years ago (November 20, 2000)
Performance
Max. CPU clock rate1.3 GHz to 3.8 GHz
FSB speeds400 MT/s to 1066 MT/s
Cache
L1 cache8 KB to 16 KB per core
L2 cache128 KB to 2048 KB
L3 cache4 MB to 16 MB shared
Architecture and classification
MicroarchitectureNetBurst
Instruction setx86 (IA-32), x86-64 (some)
Extensions
Physical specifications
Transistors
Cores
  • 1-2 (2-4 threads with HT)
Sockets
Products, models, variants
Models
  • Celeron Series
  • Celeron D Series
  • Pentium 4 Series
  • Pentium D Series
  • Xeon Series
History
PredecessorP6
SuccessorsIntel Core
IA-64
Intel Core
General information
LaunchedJune 26, 2006; 18 years ago (June 26, 2006) (Xeon)
July 27, 2006; 18 years ago (July 27, 2006) (Core 2)
Performance
Max. CPU clock rate933 MHz to 3.5 GHz
FSB speeds533 MT/s to 1600 MT/s
Cache
L1 cache64 KB per core
L2 cache0.5 to 6 MB per two cores
L3 cache8 MB to 16 MB shared (Xeon 7400)
Architecture and classification
Technology node65 nm to 45 nm
MicroarchitectureCore
Instruction setx86-64
Instructionsx86, x86-64
Extensions
Physical specifications
Transistors
Cores
  • 1–4 (2-6 Xeon)
Sockets
Products, models, variants
Model
History
PredecessorsNetBurst
Enhanced Pentium M (P6)
SuccessorsPenryn (tick)
(a version of Core)
Nehalem (tock)
Support status
Unsupported
Penryn
General information
LaunchedNovember 2007; 17 years ago (November 2007)
Performance
Max. CPU clock rate1.06 GHz to 3.33 GHz
FSB speeds533 MT/s to 1600 MT/s
Cache
L1 cache64 KB per core
L2 cache1 MB to 12 MB unified
L3 cache8 MB to 16 MB shared (Xeon)
Architecture and classification
MicroarchitectureCore
Instruction setx86-64
Instructionsx86, x86-64
Extensions
Physical specifications
Transistors
Cores
  • 1-4 (2-6 Xeon)
Sockets
Products, models, variants
Model
  • P6 Family (Celeron, Pentium, Pentium Dual-Core, Core 2 range, Xeon)
History
PredecessorCore
SuccessorNehalem
Support status
Unsupported
Nehalem
General information
LaunchedNovember 11, 2008; 16 years ago (November 11, 2008)
Performance
Max. CPU clock rate1.06 GHz to 3.33 GHz
QPI speeds4.80 GT/s to 6.40 GT/s
DMI speeds2.50 GT/s
Cache
L1 cache64 KB per core
L2 cache256 KB per core
L3 cache2 MB to 24 MB shared
Architecture and classification
Technology node45 nm
MicroarchitectureNehalem
Instruction setx86-64
Instructionsx86, x86-64
Extensions
Physical specifications
Transistors
Cores
  • 2-6 (4-8 Xeon)
Sockets
Products, models, variants
Model
  • Pentium, Core, Core in and Xeon Series
History
PredecessorsCore (tock)
Penryn (tick)
SuccessorsWestmere (tick)
Sandy Bridge (tock)
Support status
Unsupported
Westmere
General information
LaunchedJanuary 7, 2010; 14 years ago (January 7, 2010)
Performance
Max. CPU clock rate1.06 GHz to 3.46 GHz
QPI speeds4.80 GT/s to 6.40 GT/s
DMI speeds2.50 GT/s
Cache
L1 cache64 KB per core
L2 cache256 KB per core
L3 cache2 MB to 30 MB shared
Architecture and classification
MicroarchitectureNehalem
Instruction setx86-64
InstructionsIA-32, x86-64
Extensions
Physical specifications
Transistors
Cores
  • 2-6 (4-10 Xeon)
GPUs533 MHz to 900 MHz
177M 45nm (K0)
Sockets
Products, models, variants
Model
  • Core in, Xeon
History
PredecessorNehalem
SuccessorSandy Bridge
Support status
Unsupported
Sandy Bridge
General information
LaunchedJanuary 9, 2011; 13 years ago (January 9, 2011)
DiscontinuedSeptember 27, 2013 [17]
Product code80619 (extreme desktop)
80620 (server LGA1356)
80621 (server LGA2011)
80623 (desktop)
80627 (mobile)
Performance
Max. CPU clock rate1.60 GHz to 3.60 GHz
DMI speeds5.00 GT/s GT/s
Cache
L1 cache64 KB per core
L2 cache256 KB per core
L3 cache1 MB to 8 MB shared
10 MB to 15 MB (Extreme)
3 MB to 20 MB (Xeon)
Architecture and classification
MicroarchitectureSandy Bridge
Instruction setx86-64
Instructionsx86, x86-64
Extensions
Physical specifications
Transistors
Cores
  • 1–4 (4-6 Extreme, 2-8 Xeon)
GPUsHD Graphics
650 MHz to 1100 MHz
HD Graphics 2000
650 MHz to 1250 MHz
HD Graphics 3000
650 MHz to 1350 MHz
HD Graphics P3000
850 MHz to 1350 MHz
Sockets
Products, models, variants
Model
History
PredecessorsNehalem (Tock)
Westmere (Tick)
SuccessorsIvy Bridge (Tick)
Haswell (Tock)
Support status
Unsupported
Ivy Bridge
Intel's internal Ivy Bridge logo[18]
General information
LaunchedApril 29, 2012; 12 years ago (April 29, 2012)
DiscontinuedJune 5, 2015; 9 years ago (June 5, 2015)
Marketed byIntel
Designed byIntel
Common manufacturer
CPUID code0306A9h
Product code80633 (extreme desktop)
80634 (server LGA1356)
80635 (server E5 LGA2011)
80636 (server E7 LGA2011)
80637 (desktop)
80638 (mobile)
Performance
Max. CPU clock rate1.4 to 4.1 GHz
DMI speeds5.00 GT/s
Cache
L1 cache64 KB per core
L2 cache256 KB per core
L3 cache2 to 8 MB shared
Architecture and classification
Technology nodeIntel 22 nm
MicroarchitectureSandy Bridge
Instruction setx86-64
Instructionsx86, x86-64
Extensions
Physical specifications
Transistors
  • 2.104B
Cores
  • 2–4 (Mainstream)
    2–15 (Xeon)
GPUsHD Graphics 2500
650 to 1150 MHz
HD Graphics 4000
350 to 1300 MHz
HD Graphics P4000
650 to 1250 MHz
Sockets
Products, models, variants
Models
Brand names
History
PredecessorSandy Bridge (Tock)
SuccessorHaswell (Tock/Architecture)
Support status
Unsupported
Haswell
A Haswell wafer with several dies, with a pin for scale
General information
LaunchedJune 4, 2013; 11 years ago (June 4, 2013)
CPUID code0306C3h
Product code
Cache
L1 cache64 KB per core
L2 cache256 KB per core
L3 cache2–45 MB (shared)
L4 cache128 MB of eDRAM (Iris Pro models only)
Architecture and classification
Technology node22 nm (Tri-Gate)
MicroarchitectureHaswell
Instruction setx86-64
Instructionsx86, x86-64
Extensions
Physical specifications
Cores
    • 2–4 (mainstream)
    • 6–8 (enthusiast)
    • 2–18 (Xeon)
GPUs
  • HD Graphics 4200
  • HD Graphics 4400
  • HD Graphics 4600
  • HD Graphics 5000
  • Iris 5100
  • Iris Pro 5200
Sockets
Products, models, variants
Model
    • Haswell
    • Haswell Refresh
    • Haswell-E
    • Haswell-EP
    • Haswell-EX
Brand name
    • Core i3
    • Core i5
    • Core i7
    • Xeon E3 v3
    • Xeon E5 v3
    • Xeon E7 v3
    • Pentium
    • Celeron
History
PredecessorsSandy Bridge (Tock)
Ivy Bridge (Tick)
SuccessorsBroadwell (Tick/Process)
Skylake (Tock)
Support status
Unsupported
Broadwell
General information
LaunchedOctober 27, 2014; 10 years ago (October 27, 2014)
DiscontinuedNovember 2018[19]
CPUID code0306D4h
Product code
  • 80658 (mainstream desktop/mobile, Xeon E3)
  • 80660 (Xeon E5)
  • 80669 (Xeon E7)
  • 80671 (enthusiast desktop)
  • 80674 (Xeon D)
  • 80682 (Xeon D, Hewitt Lake)
Cache
L1 cache64 KB per core
L2 cache256 KB per core
L3 cache2-6 MB (shared)
L4 cache128 MB of eDRAM (Iris Pro models only)
Architecture and classification
Technology node14 nm (Tri-Gate)
MicroarchitectureHaswell
Instruction setx86-64
Instructionsx86, x86-64
Extensions
Physical specifications
Cores
    • 2–4 (mainstream)
    • 6–10 (enthusiast)
    • 4–24 (Xeon)
GPUs
  • HD 5300
  • HD 5500
  • HD 5700P
  • HD 6000
  • HD 6100
  • HD 6200
  • HD 6300P
  • HD Graphics
Sockets
Products, models, variants
Brand name
History
Predecessors
SuccessorSkylake (Tock/Architecture)
Support status
Unsupported
Skylake
Intel Core i7-6700K with four physical cores
General information
LaunchedAugust 5, 2015; 9 years ago (August 5, 2015)
DiscontinuedMarch 4, 2019; 5 years ago (March 4, 2019) (desktop processors)
Marketed byIntel
Designed byIntel
Common manufacturer
CPUID code0406e3h, 0506e3h
Product code
  • 80662 (mainstream and mobile Xeon E3)
  • 80673 (enthusiast and server)
Performance
Max. CPU clock rateUp to 4.5 GHz
Cache
L1 cache64 KB per core
L2 cache256 KB per core
(1 MB per core for Skylake-X)
L3 cacheUp to 2 MB per core
(1.375 MB per core for Skylake-X)
L4 cache128 MB of eDRAM (on select models)
Architecture and classification
Technology node14 nm bulk silicon 3D transistors (Tri-Gate)
MicroarchitectureSkylake
Instruction setx86-64
Instructionsx86-64 (Intel 64)
Extensions
Physical specifications
Cores
  • 2–28
Sockets
Products, models, variants
Brand name
    • Core i3
    • Core i5
    • Core i7
    • Core i9
    • Core m3
    • Core m5
    • Core m7
    • Xeon
    • Celeron
    • Pentium
History
PredecessorBroadwell (Tick/Process)
Successors
Support status
Client: Legacy support for iGPU
Xeon E3: Legacy support for iGPU
Other Xeon: supported
Cannon Lake
General information
LaunchedMay 15, 2018; 6 years ago (May 15, 2018)
DiscontinuedFebruary 28, 2020; 4 years ago (February 28, 2020)
Marketed byIntel
Designed byIntel
Common manufacturer
Performance
Max. CPU clock rate3.2 GHz
Cache
L1 cache64 KB per core
L2 cache256 KB per core
L3 cache2 MB per core
Architecture and classification
Technology nodeIntel 10 nm (tri-gate) transistors
MicroarchitecturePalm Cove
Instruction setx86-64
Instructionsx86-64, Intel 64
Extensions
Physical specifications
Cores
  • 2
GPUFactory disabled
Socket
  • BGA 1440
Products, models, variants
Brand name
History
PredecessorsDesktop: Coffee Lake (2nd optimization)
Kaby Lake Refresh (2nd optimization)
SuccessorIce Lake (architecture)
Support status
Legacy support for iGPU
  1. ^ "CPU History - The CPU Museum - Life Cycle of the CPU". cpushack.com. Archived from the original on July 20, 2021. Retrieved September 6, 2021.
  2. ^ "1.5 µm lithography process - WikiChip". en.wikichip.org. Archived from the original on September 9, 2018. Retrieved January 21, 2019.
  3. ^ Ormsby, John, "Chip Design: A Race Worth Winning", Intel Corporation, Microcomputer Solutions, July/August 1988, page 18
  4. ^ a b "Product Change Notification #777" (PDF). Intel. February 9, 1999. Archived from the original (PDF) on January 27, 2000. Retrieved October 14, 2019.
  5. ^ "Pentium® Pro Processor at 150 MHz, 166 MHz, 180 MHz and 200 MHz" (PDF). Intel Corporation. November 1995. p. 1. Archived from the original (PDF) on April 2, 2016. {{cite web}}: |archive-date= / |archive-url= timestamp mismatch; April 12, 2016 suggested (help)
  6. ^ Shvets, Gennadiy (September 26, 2012). "Intel discontinues second-generation Core i5 and i7 CPUs". CPU World. Retrieved 2020-07-29.
  7. ^ "Origin of a Codename: Ivy Bridge". Intel Free Press. 19 April 2012. Archived from the original on 16 January 2014. Retrieved 16 January 2014.
  8. ^ Perillo, Ron (November 9, 2017). "Intel Broadwell-E CPUs Officially Discontinued". eTeknix. Retrieved 2020-07-29.
  9. ^ a b "Intel Core i7-6700K Processor (8M Cache, up to 4.20 GHz)". Ark.intel.com. Retrieved January 24, 2018.
  10. ^ a b Tom's Hardware: Skylake Xeon Platforms Spotted, Purley Makes A Quiet Splash At Computex. June 3, 2016
  11. ^ Cutress, Ian (August 5, 2015). "The Intel Skylake Mobile and Desktop Launch, with Architecture Analysis". AnandTech. Retrieved September 18, 2015.
  12. ^ a b Kirsch, Nathan (February 21, 2016). "Intel Cannonlake Added To LLVM's Clang – AVX-512". Legit Reviews. Archived from the original on 2016-10-23. Retrieved October 23, 2016.
  13. ^ "CPU History - The CPU Museum - Life Cycle of the CPU". cpushack.com. Archived from the original on July 20, 2021. Retrieved September 6, 2021.
  14. ^ "1.5 µm lithography process - WikiChip". en.wikichip.org. Archived from the original on September 9, 2018. Retrieved January 21, 2019.
  15. ^ Ormsby, John, "Chip Design: A Race Worth Winning", Intel Corporation, Microcomputer Solutions, July/August 1988, page 18
  16. ^ "Pentium® Pro Processor at 150 MHz, 166 MHz, 180 MHz and 200 MHz" (PDF). Intel Corporation. November 1995. p. 1. Archived from the original (PDF) on April 2, 2016. {{cite web}}: |archive-date= / |archive-url= timestamp mismatch; April 12, 2016 suggested (help)
  17. ^ Shvets, Gennadiy (September 26, 2012). "Intel discontinues second-generation Core i5 and i7 CPUs". CPU World. Retrieved 2020-07-29.
  18. ^ "Origin of a Codename: Ivy Bridge". Intel Free Press. 19 April 2012. Archived from the original on 16 January 2014. Retrieved 16 January 2014.
  19. ^ Perillo, Ron (November 9, 2017). "Intel Broadwell-E CPUs Officially Discontinued". eTeknix. Retrieved 2020-07-29.
  20. ^ Cutress, Ian (August 5, 2015). "The Intel Skylake Mobile and Desktop Launch, with Architecture Analysis". AnandTech. Retrieved September 18, 2015.
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