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{{ infobox programming language
{{Infobox programming language
| name = LISA
| name = LISA
| logo =
| logo =
| paradigm =
| paradigm =
| year = 1997, last revised 2007
| year = 1997, last revised 2007
| designer = [[Vojin Zivojnovic, Stefan Pees, version 1.0]]
| designer = [[Vojin Zivojnovic, Stefan Pees, version 1.0]]
| developer =
| developer =
| latest_release_version =
| latest_release_version =
| latest_release_date =
| latest_release_date =
| latest_test_version =
| latest_test_version =
| latest_test_date =
| latest_test_date =
| typing =
| typing =
| dialects = LISA2.0, LISA+
| dialects = LISA 2.0, LISA+
| influenced_by =
| influenced_by =
| influenced =
| influenced =
| operating_system =
| operating_system =
| license =
| license =
| website =
| website = https://www.ice.rwth-aachen.de/research/tools-projects/closed-projects/lisa
}}
}}


'''LISA''' is a Language targeting the description of [[Instruction Set Architecture]]. The aim is to capture all the information required to generate [[software tools]] ([[compiler]], [[assembly language|assembler]], [[Instruction Set Simulator]], ...) and implementation hardware (in [[VHDL]] or [[Verilog]]) of a given [[microprocessor|processor]] core.
'''LISA''' (Language for Instruction Set Architectures) is a language to describe the [[instruction set architecture]] of a [[microprocessor|processor]]. LISA captures the information required to generate [[software tools]] ([[compiler]], [[assembly language|assembler]], [[instruction set simulator]], ...) and implementation hardware (in [[VHDL]] or [[Verilog]]) of a given processor.


⚫
LISA has been used to re-implement the hardware of existing processor cores, keeping the [[binary compatibility]] with the legacy version, as all [[software tools]] did already exist and legacy compiled software images could be executed on the newly created hardware. Another application has been to generate the ISS ([[instruction set simulator]]) for [[Reduced_instruction_set_computing|RISC]] processors such the [[ARM architecture]] ISSes.
⚫
'''LISA''' is not focused on the modeling of other on-chip components around the processor core itself, such as peripherals, hardware accelerators, buses and memories; Other languages such as [[SystemC]] will be used for these.


⚫
LISA' is not focused on the modeling of other on-chip components around the processor core itself, such as peripherals, hardware accelerators, buses and memories; Other languages such as [[SystemC]] can be used for these.
⚫
While the scope of the language is quite large, many industrial cases are targeting a subset of its possibility. For instance LISA have been used to re-implement the hardware of certain processor core keeping the [[binary compatibility]] with the legacy version, as all [[software tools]] did already exist and legacy compiled [[software]] images could be executed on the newly created hardware.


⚫
The language has not been yet{{As of?|date=April 2023}} standardised by [[IEEE]] or [[International Organization for Standardization|ISO]] and is currently owned by [[RWTH Aachen University]], in [[Germany]].
Another focus case has been to focus only on generating ISS ([[Instruction Set Simulator]]), most known case are the [[ARM Architecture]] ISSes.


⚫
The language has not been yet stantardised by [[IEEE]] nor [[ISO]] and is currently owned by [[RWTH Aachen]] University, in [[Germany]].

== Features ==
== History ==
== History ==


Initially developed at Institute for Integrated Signal Processing Systems (ISS) Aachen, belonging to [[RWTH Aachen]] University, in [[Germany]].
LISA was initially developed at Institute for Integrated Signal Processing Systems (ISS) Aachen, belonging to [[RWTH Aachen]] University, in [[Germany]]. The current official version from [[RWTH Aachen]] is LISA 2.0. The language is still in evolution to cover research on processors, including [[Reconfigurable computing]] (in LISA 3.0), [[multi-core]], [[parallel programming]].


⚫
One noticeable branch called LISA+ has been created for handling the modeling of peripherals such as interrupt controllers, timers, etc.<ref>[http://infocenter.arm.com] search for LISA+ Reference Language Manual</ref>
The current official version from [[RWTH Aachen]] is LISA2.0

The language is still in evolution to cover newly (and future) research on micro-computers, this includes [[Reconfigurable computing]] (in LISA3.0) , [[multi-core]], [[Parallel programming]], ...

⚫
One noticeable branch has been created for handling the modeling of peripherals (such as interrupt controller, timer, ...); Called LISA+. (see infocenter.arm.com and search for LISA+ Reference Language Manual)


== See also ==
== See also ==

* [[Alphabetical list of programming languages]]
* [[Alphabetical list of programming languages]]
* [[SystemC]]
* [[SystemC]]
* [[Verilog]]
* [[Verilog]]
* [[VHDL]]
* [[VHDL]]

⚫
== Notes ==

{{refs}}


== References ==
== References ==
{{More footnotes|date=April 2009}}
{{More footnotes|date=April 2009}}
{{Reflist}}


⚫
=== Papers ===
{{Refbegin|2}}
* V. Zivojnovic, S. Pees, Ch. Schläger, H. Meyr, ''LISA bridges gaps in high-tech languages'', Electronic Engineering Times, Oct 7, 1996
* [http://www.ice.rwth-aachen.de/fileadmin/publications/Zivojnovic96vlsi.pdf ] V. Zivojnovic, S. Pees, H. Meyr, ''LISA – machine description language and generic machine model for HW/SW co-design'', Proceedings of the IEEE Workshop on VLSI Signal Processing (San Francisco), Oct. 1996
* A. Chattopadhyay, H. Meyr and R. Leupers: ''LISA: A Uniform ADL for Embedded Processor Modeling, Implementation and Software Toolsuite Generation'' appearing in P. Mishra, N. Dutt, ''Processor Description Languages, Volume 1'', Morgan Kaufmann, 2008. {{ISBN|978-0123742872}}


=== Books ===
=== Books ===
* A. Hoffmann, H. Meyr, R. Leupers: ''Architecture Exploration for Embedded Processors with LISA'', Springer, 2010. {{ISBN|978-1441953346}}
* [[Oliver Wahlen]]: ''C Compiler Aided Design of Application-specific Instruction-set Processors Using the Machine Description Language LISA (Berichte Aus Der Electrotechnik)'', Shaker Verlag GmbH, Germany (August 13, 2004) , ISBN 3832230351
* O. Wahlen: ''C Compiler Aided Design of Application-specific Instruction-set Processors Using the Machine Description Language LISA (Berichte Aus Der Electrotechnik)'', [[Shaker Verlag]] GmbH, Germany (August 13, 2004). {{ISBN|3-8322-3035-1}}


=== Archives ===
== External links ==
== External links ==
* [https://www.ice.rwth-aachen.de/research/tools-projects/closed-projects/lisa LISA] project page at RWTH Aachen, Germany
* http://www.iss.rwth-aachen.de
* [http://www.synopsys.com/IP/ProcessorIP/asip/processor-designer/Pages/default.aspx Processor Designer] is a tool sold by [[Synopsys]] to create processors from LISA 2.0 descriptions
* http://www.arm.com


{{DEFAULTSORT:Language For Instruction Set Architecture}}
[[Category:Specification languages]]
[[Category:Specification languages]]

Latest revision as of 16:38, 21 April 2023

LISA
Designed byVojin Zivojnovic, Stefan Pees, version 1.0
First appeared1997, last revised 2007
Websitehttps://www.ice.rwth-aachen.de/research/tools-projects/closed-projects/lisa
Dialects
LISA 2.0, LISA+

LISA (Language for Instruction Set Architectures) is a language to describe the instruction set architecture of a processor. LISA captures the information required to generate software tools (compiler, assembler, instruction set simulator, ...) and implementation hardware (in VHDL or Verilog) of a given processor.

LISA has been used to re-implement the hardware of existing processor cores, keeping the binary compatibility with the legacy version, as all software tools did already exist and legacy compiled software images could be executed on the newly created hardware. Another application has been to generate the ISS (instruction set simulator) for RISC processors such the ARM architecture ISSes.

LISA' is not focused on the modeling of other on-chip components around the processor core itself, such as peripherals, hardware accelerators, buses and memories; Other languages such as SystemC can be used for these.

The language has not been yet[as of?] standardised by IEEE or ISO and is currently owned by RWTH Aachen University, in Germany.

History

[edit]

LISA was initially developed at Institute for Integrated Signal Processing Systems (ISS) Aachen, belonging to RWTH Aachen University, in Germany. The current official version from RWTH Aachen is LISA 2.0. The language is still in evolution to cover research on processors, including Reconfigurable computing (in LISA 3.0), multi-core, parallel programming.

One noticeable branch called LISA+ has been created for handling the modeling of peripherals such as interrupt controllers, timers, etc.[1]

See also

[edit]

References

[edit]
  1. ^ [1] search for LISA+ Reference Language Manual

Papers

[edit]
  • V. Zivojnovic, S. Pees, Ch. Schläger, H. Meyr, LISA bridges gaps in high-tech languages, Electronic Engineering Times, Oct 7, 1996
  • [2] V. Zivojnovic, S. Pees, H. Meyr, LISA – machine description language and generic machine model for HW/SW co-design, Proceedings of the IEEE Workshop on VLSI Signal Processing (San Francisco), Oct. 1996
  • A. Chattopadhyay, H. Meyr and R. Leupers: LISA: A Uniform ADL for Embedded Processor Modeling, Implementation and Software Toolsuite Generation appearing in P. Mishra, N. Dutt, Processor Description Languages, Volume 1, Morgan Kaufmann, 2008. ISBN 978-0123742872

Books

[edit]
  • A. Hoffmann, H. Meyr, R. Leupers: Architecture Exploration for Embedded Processors with LISA, Springer, 2010. ISBN 978-1441953346
  • O. Wahlen: C Compiler Aided Design of Application-specific Instruction-set Processors Using the Machine Description Language LISA (Berichte Aus Der Electrotechnik), Shaker Verlag GmbH, Germany (August 13, 2004). ISBN 3-8322-3035-1
[edit]
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