POWER6: Difference between revisions
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{{Short description|2007 family of multiprocessors by IBM}} |
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{{external links|date=September 2017}} |
{{external links|date=September 2017}} |
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{{Infobox CPU |
{{Infobox CPU |
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| designfirm = [[IBM]] |
| designfirm = [[IBM]] |
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| manuf1 = |
| manuf1 = |
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| arch = [[Power |
| arch = [[Power ISA]] ([[Power ISA#Power ISA v.2.05|Power ISA v.2.05]]) |
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| microarch = |
| microarch = |
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| numcores = 2 |
| numcores = 2 |
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| successor = [[POWER7]] |
| successor = [[POWER7]] |
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}} |
}} |
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{{Power |
{{POWER, PowerPC, and Power ISA}} |
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The '''POWER6''' is a [[microprocessor]] developed by [[IBM]] that implemented the [[Power |
The '''POWER6''' is a [[microprocessor]] developed by [[IBM]] that implemented the [[Power ISA#Power ISA v.2.05|Power ISA v.2.05]]. When it became available in systems in 2007, it succeeded the [[POWER5#POWER5+|POWER5+]] as IBM's flagship Power microprocessor. It is claimed to be part of the eCLipz project, said to have a goal of converging IBM's server hardware where practical (hence "ipz" in the acronym: [[IBM AS/400|iSeries]], [[pSeries]], and [[zSeries]]).<ref>{{cite web |
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|title=A Mainframe Roadmap |
|title=A Mainframe Roadmap |
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|publisher=Isham Research |
|publisher=Isham Research |
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|url=http://www.isham-research.co.uk/mainframe_2008.html |
|url=http://www.isham-research.co.uk/mainframe_2008.html |
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|archive-url=https://web.archive.org/web/20160303180019/http://www.isham-research.co.uk/mainframe_2008.html |
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|archive-date=2016-03-03 |
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}}</ref> |
}}</ref> |
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[[File:Power6 bottom.jpg|thumb|IBM Power6 CPU base]] |
[[File:Power6 bottom.jpg|thumb|IBM Power6 CPU base]] |
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[[File:Power6 ceramic base.jpg|thumb|Power6 ceramic base, contacts]] |
[[File:Power6 ceramic base.jpg|thumb|Power6 ceramic base, contacts]] |
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==History== |
==History== |
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POWER6 was described at the [[International Solid-State Circuits Conference]] (ISSCC) in February 2006, and additional details were added at the Microprocessor Forum in October 2006<ref>{{cite web|url=http://www.realworldtech.com/power6-mpf/|title=Fall Processor Forum 2006: IBM's POWER6|author=David Kanter|publisher=Real World Technologies|date=October 16, 2006}}</ref> and at the next ISSCC in February 2007. It was formally announced on May 21, 2007.<ref>{{cite press release|url=http://www-03.ibm.com/press/us/en/pressrelease/21580.wss|title=IBM Unleashes World's Fastest Chip in Powerful New Computer|publisher=[[IBM]]}}</ref> It was released on June 8, 2007 at speeds of 3.5, 4.2 and 4.7 GHz,<ref name="theregister">{{cite web |
POWER6 was described at the [[International Solid-State Circuits Conference]] (ISSCC) in February 2006, and additional details were added at the Microprocessor Forum in October 2006<ref>{{cite web|url=http://www.realworldtech.com/power6-mpf/|title=Fall Processor Forum 2006: IBM's POWER6|author=David Kanter|publisher=Real World Technologies|date=October 16, 2006}}</ref> and at the next ISSCC in February 2007. It was formally announced on May 21, 2007.<ref>{{cite press release|url=http://www-03.ibm.com/press/us/en/pressrelease/21580.wss|title=IBM Unleashes World's Fastest Chip in Powerful New Computer|publisher=[[IBM]]|archive-url=https://web.archive.org/web/20070524065531/http://www-03.ibm.com/press/us/en/pressrelease/21580.wss|archive-date=May 24, 2007}}</ref> It was released on June 8, 2007 at speeds of 3.5, 4.2 and 4.7 GHz,<ref name="theregister">{{cite web |
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|title=IBM POWER system hardware |
|title=IBM POWER system hardware |
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|publisher=IBM |
|publisher=IBM |
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|url=http://www-03.ibm.com/systems/power/hardware/ |
|url=http://www-03.ibm.com/systems/power/hardware/ |
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|access-date=2008-10-09 |
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⚫ | |||
|archive-url=https://web.archive.org/web/20081216091734/http://www-03.ibm.com/systems/power/hardware/ |
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|title=IBM's Power6 Processors to Hit 5.6GHz |
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⚫ | |||
|title=IBM thumbs nose at heat concerns, kicks Power6 to 6GHz |
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|first=Ashlee |
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|last=Vance |
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|author-link=Ashlee Vance |
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|date=2006-02-07 |
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|publisher=[[The Register]] |
|publisher=[[The Register]] |
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|url=https://www.theregister.co.uk/2006/02/07/ibm_power6_show/ |
|url=https://www.theregister.co.uk/2006/02/07/ibm_power6_show/ |
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|access-date=2006-02-07 |
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}}</ref> POWER6 reached first silicon in the middle of 2005,<ref>{{cite web |
}}</ref> POWER6 reached first silicon in the middle of 2005,<ref>{{cite web |
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|title = IBM's Power6 Gets First Silicon as Power5+ Looms |
|title = IBM's Power6 Gets First Silicon as Power5+ Looms |
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|publisher = IT Jungle |
|publisher = IT Jungle |
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|url = http://www.itjungle.com/tfh/tfh082205-story01.html |
|url = http://www.itjungle.com/tfh/tfh082205-story01.html |
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|access-date = 2005-08-22 |
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|url-status = dead |
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|archive-url = https://web.archive.org/web/20051125172125/http://www.itjungle.com/tfh/tfh082205-story01.html |
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|archive-date = 2005-11-25 |
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|df = |
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}}</ref> and was bumped to 5.0 GHz in May 2008 with the introduction of the P595.<ref>{{cite web |
}}</ref> and was bumped to 5.0 GHz in May 2008 with the introduction of the P595.<ref>{{cite web |
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|title=IBM smacks rivals with 5.0GHz Power6 beast |
|title=IBM smacks rivals with 5.0GHz Power6 beast |
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|publisher=The Register |
|publisher=The Register |
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|url=https://www.theregister.co.uk/2008/04/08/ibm_595_water/ |
|url=https://www.theregister.co.uk/2008/04/08/ibm_595_water/ |
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|access-date=2008-10-12 |
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}}</ref> |
}}</ref> |
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|publisher=Real World Technologies |
|publisher=Real World Technologies |
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|url=http://www.realworldtech.com/page.cfm?ArticleID=RWT121905001634 |
|url=http://www.realworldtech.com/page.cfm?ArticleID=RWT121905001634 |
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|access-date=2005-12-19 |
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}}</ref> |
}}</ref> |
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Each core has a 64 KB, four-way set-associative instruction cache and a 64 KB data cache of an eight-way set-associative design with a two-stage pipeline supporting two independent 32-bit reads or one 64-bit write per cycle.<ref name="informationweek">{{cite web |
Each core has a 64 KB, four-way set-associative instruction cache and a 64 KB data cache of an eight-way set-associative design with a two-stage pipeline supporting two independent 32-bit reads or one 64-bit write per cycle.<ref name="informationweek">{{cite web |
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|title=IBM Tips Power6 Processor Architecture |
|title=IBM Tips Power6 Processor Architecture |
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|date=6 February 2006 |
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|publisher=[[InformationWeek]] |
|publisher=[[InformationWeek]] |
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|url= |
|url=https://www.informationweek.com/it-life/ibm-tips-power6-processor-architecture |
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|access-date=2022-07-13 |
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}}</ref> Each core has semi-private 4 [[MiB]] unified [[L2 cache]], where the cache is assigned a specific core, but the other has a fast access to it. The two cores share a 32 MiB [[L3 cache]] which is off die, using an 80 GB/s bus.<ref name="Heise">{{cite web |
}}</ref> Each core has semi-private 4 [[MiB]] unified [[L2 cache]], where the cache is assigned a specific core, but the other has a fast access to it. The two cores share a 32 MiB [[L3 cache]] which is off die, using an 80 GB/s bus.<ref name="Heise">{{cite web |
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|title = Fall Processor Forum: Power6 at 5 GHz |
|title = Fall Processor Forum: Power6 at 5 GHz |
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|publisher = [[Heinz Heise]] |
|publisher = [[Heinz Heise]] |
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|url = http://www.heise.de/english/newsticker/news/79371 |
|url = http://www.heise.de/english/newsticker/news/79371 |
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|access-date = 2006-10-12 |
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|url-status = dead |
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|archive-url = https://web.archive.org/web/20071116200341/http://www.heise.de/english/newsticker/news/79371 |
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|archive-date = 2007-11-16 |
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|df = |
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}}</ref> |
}}</ref> |
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|title=IBM cranks dual-core Power6 beyond 4GHz |
|title=IBM cranks dual-core Power6 beyond 4GHz |
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|publisher=[[EE Times]] |
|publisher=[[EE Times]] |
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|first=Rick |
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|url=http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=KM5EMYIDNTO5GQSNDLRCKH0CJUNN2JVN?articleID=193105767 |
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|last=Merritt |
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|date=2006-10-10 |
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|url=https://www.eetimes.com/ibm-cranks-dual-core-power6-beyond-4ghz/ |
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|access-date=2022-07-13 |
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}}</ref> |
}}</ref> |
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IBM also makes use of a 5 GHz duty-cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire that is 3 |
IBM also makes use of a 5 GHz duty-cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire that is 3 μm wide and 1.2 μm thick. The POWER6 design uses dual power supplies, a logic supply in the 0.8-to-1.2 Volt range and an SRAM power supply at about 150-mV higher.<ref name="informationweek"/> |
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The thermal characteristics of POWER6 are similar to that of the [[POWER5]]. [[Frank Soltis|Dr Frank Soltis]], an IBM chief scientist, said IBM had solved power leakage problems associated with high frequency by using a combination of [[90 nanometer|90 nm]] and 65 nm parts in the POWER6 design.<ref>{{cite web |
The thermal characteristics of POWER6 are similar to that of the [[POWER5]]. [[Frank Soltis|Dr Frank Soltis]], an IBM chief scientist, said IBM had solved power leakage problems associated with high frequency by using a combination of [[90 nanometer|90 nm]] and 65 nm parts in the POWER6 design.<ref>{{cite web |
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|author=Roger Howorth |
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|title=IBM's Power6 processor to run at 4GHz in 2007 |
|title=IBM's Power6 processor to run at 4GHz in 2007 |
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|publisher=[[IT Week]] |
|publisher=[[IT Week]] |
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|url=http://www.itweek.co.uk/itweek/news/2150006/ibm-power6-processor-run-4ghz |
|url=http://www.itweek.co.uk/itweek/news/2150006/ibm-power6-processor-run-4ghz |
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|date=2006-02-08 |
|date=2006-02-08 |
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|access-date=2007-07-11 |
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|archive-url=https://web.archive.org/web/20070926233645/http://www.itweek.co.uk/itweek/news/2150006/ibm-power6-processor-run-4ghz |
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|archive-date=2007-09-26 |
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|url-status=dead |
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}}</ref> |
}}</ref> |
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===POWER6+=== |
===POWER6+=== |
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The slightly enhanced '''POWER6+''' was introduced in April 2009, but had been shipping in [[IBM Power Systems|Power 560 and 570]] systems since October 2008. It added more memory keys for secure [[Memory management (operating systems)#Partitioned allocation|memory partition]], a feature taken from IBM's [[z/Architecture|mainframe processors]].<ref>{{cite web|title=IBM Power Systems Announcement Overview|url=http://www-03.ibm.com/systems/resources/systems_power_news_20090428_annc.pdf|website=IBM| |
The slightly enhanced '''POWER6+''' was introduced in April 2009, but had been shipping in [[IBM Power Systems|Power 560 and 570]] systems since October 2008. It added more memory keys for secure [[Memory management (operating systems)#Partitioned allocation|memory partition]], a feature taken from IBM's [[z/Architecture|mainframe processors]].<ref>{{cite web|title=IBM Power Systems Announcement Overview|url=http://www-03.ibm.com/systems/resources/systems_power_news_20090428_annc.pdf|website=IBM|access-date=6 March 2018|archive-url=https://web.archive.org/web/20110513072658/http://www-03.ibm.com/systems/resources/systems_power_news_20090428_annc.pdf|archive-date=13 May 2011|date=28 April 2009|url-status=dead}}</ref> |
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== Products == |
== Products == |
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{{As of|2008}}, the range of POWER6 systems includes "Express" models (the 520, 550 and 560) and Enterprise models (the 570 and 595).<ref>http://www-03.ibm.com/systems/power/hardware/</ref> The various system models are designed to serve any sized business. |
{{As of|2008}}, the range of POWER6 systems includes "Express" models (the 520, 550 and 560) and Enterprise models (the 570 and 595).<ref>{{cite web| url = http://www-03.ibm.com/systems/power/hardware/ |title = IBM Power Systems Hardware | website = IBM | archive-url = https://web.archive.org/web/20080512205228/http://www-03.ibm.com/systems/power/hardware/ | archive-date = May 12, 2008}}</ref> The various system models are designed to serve any sized business. |
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For example, the 520 Express is marketed to small businesses while the Power 595 is marketed for large, multi-environment data centers. |
For example, the 520 Express is marketed to small businesses while the Power 595 is marketed for large, multi-environment data centers. |
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The main difference between the Express and Enterprise models is that the latter include Capacity Upgrade on Demand (CUoD) capabilities and hot-pluggable processor and memory "books". |
The main difference between the Express and Enterprise models is that the latter include Capacity Upgrade on Demand (CUoD) capabilities and hot-pluggable processor and memory "books". |
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{| class="wikitable sortable" style="text-align:center" border=1 |
{| class="wikitable sortable" style="text-align:center" border=1 |
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|+IBM POWER6 servers |
|+IBM POWER6 ([[IBM Power Systems|Power Systems]]) servers |
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! Name !! Number of sockets !! Number of cores !! CPU clock frequency |
! Name !! Number of sockets !! Number of cores !! CPU clock frequency |
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IBM also offers four POWER6 based [[blade server]]s.<ref>http://www-03.ibm.com/systems/power/hardware/blades/index.html</ref> Specifications are shown in the table below. |
IBM also offers four POWER6 based [[blade server]]s.<ref>{{cite web| url = http://www-03.ibm.com/systems/power/hardware/blades/index.html |title = IBM Power Systems Hardware - Blade Servers | website = IBM | archive-url = https://web.archive.org/web/20080521035156/http://www-03.ibm.com/systems/power/hardware/blades/index.html| archive-date = May 21, 2008}}</ref> Specifications are shown in the table below. |
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{| class="wikitable sortable" style="text-align:center" border=1 |
{| class="wikitable sortable" style="text-align:center" border=1 |
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! Name !! Number of cores !! CPU clock frequency !! Blade slots required |
! Name !! Number of cores !! CPU clock frequency !! Blade slots required |
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| BladeCenter JS12 || 2 || 3.8 GHz || 1 |
| [[BladeCenter]] JS12 || 2 || 3.8 GHz || 1 |
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|- |
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| BladeCenter JS22 || 4 || 4.0 GHz || 1 |
| BladeCenter JS22 || 4 || 4.0 GHz || 1 |
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All blades support AIX, i, and Linux. The BladeCenter S and H chassis is supported for blades running AIX, i, and Linux. The BladeCenter E, HT, and T chassis support blades running AIX and Linux but not i. |
All blades support [[AIX]], [[IBM i]], and [[Linux]]. The BladeCenter S and H chassis is supported for blades running AIX, i, and Linux. The BladeCenter E, HT, and T chassis support blades running AIX and Linux but not i. |
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At the SuperComputing 2007 (SC07) conference in Reno a new water-cooled Power 575 was revealed. The 575 is composed of 2U "nodes" each with 32 POWER6 cores at 4.7 GHz with up to 256 GB of RAM. Up to 448 cores can be installed in a single frame. |
At the SuperComputing 2007 (SC07) conference in Reno a new water-cooled Power 575 was revealed. The 575 is composed of 2U "nodes" each with 32 POWER6 cores at 4.7 GHz with up to 256 GB of RAM. Up to 448 cores can be installed in a single frame. |
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==See also== |
==See also== |
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*[[IBM |
*[[IBM Power microprocessors]] |
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*[[Power Architecture]] |
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*[[POWER7]] |
*[[POWER7]] |
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*[[IBM z10 |
*[[IBM z10|z10]], a [[Mainframe computer|mainframe]] processor sharing much technology with the POWER6. |
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== References == |
== References == |
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==External links== |
==External links== |
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*[https://web.archive.org/web/20071015162137/http://www-03.ibm.com/press/us/en/presskit/21546.wss IBM POWER6 Press Kit] |
*[https://web.archive.org/web/20071015162137/http://www-03.ibm.com/press/us/en/presskit/21546.wss IBM POWER6 Press Kit] |
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*{{cite web|url=https://www.cnet.com/tech/tech-industry/ibms-power6-gets-help-with-math-multimedia/|title=IBM's Power6 gets help with math, multimedia|website=[[CNET]]|date=October 10, 2006}} |
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*[http://australianit.news.com.au/articles/0,7204,21774602%5E15306%5E%5Enbv%5E,00.html IBM's Power6 doubles speed] |
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*{{cite |
*{{cite web|url=https://www.informationweek.com/it-life/ibm-debuts-power6-in-new-unix-server|title=IBM Debuts Power6 In New Unix Server|website=[[InformationWeek]]|date=May 21, 2007}} |
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*{{cite web|url=https://arstechnica.com/gadgets/2006/10/8034/|title=POWER6 set to carry the POWER4/POWER5/970 lineage forward?|website=[[Ars Technica]]|date=October 19, 2006}} |
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*[http://www.informationweek.com/news/showArticle.jhtml?articleID=199700552 InformationWeek report on the Power6 announcement] |
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*{{cite web|url=https://arstechnica.com/uncategorized/2007/02/8823/|title=IBM unveils POWER6 microprocessor details|website=[[Ars Technica]]|date=February 12, 2007}} |
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*[http://www.realworldtech.com/page.cfm?ArticleID=RWT121905001634 Real World Tech, Dec 19, 2005] |
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*{{cite web|url=https://arstechnica.com/gadgets/2007/05/ibms-power6-flies-the-coop-at-4-7ghz/|title=IBM's POWER6 flies the coop at 4.7GHz|website=[[Ars Technica]]|date=May 21, 2007}} |
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*[http://www.informationweek.com/showArticle.jhtml?articleID=179100699 InformationWeek, Feb 6, 2006] |
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*[http://www.cnet.com/news/ibms-power6-gets-help-with-math-multimedia/ C|Net, Oct 10, 2006] |
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*[https://web.archive.org/web/20071116200341/http://www.heise.de/english/newsticker/news/79371 Heise Online, Oct 12, 2006] |
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*[http://www.realworldtech.com/power6-mpf/ Fall Processor Forum 2006: IBM’s POWER6, Real World Tech, Oct 16, 2006] |
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*[https://arstechnica.com/news.ars/post/20061019-8034.html Arstechnica, Oct 19, 2006] |
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*[https://arstechnica.com/news.ars/post/20070212-8823.html Arstechnica, Feb 12, 2007] |
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*[https://arstechnica.com/news.ars/post/20070521-ibms-power6-flies-the-coop-at-4-7ghz.html Arstechnica, May 21, 2007] |
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=== Recommended reading === |
=== Recommended reading === |
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*{{cite journal|title=EnergyScale for IBM POWER6 microprocessor based systems|author1=H. -Y. McCreary|author2=M. A. Broyles|author3=M. S. Floyd|author4=A. J. Geissler|author5=S. P. Hartman|author6=F. L. Rawson|author7=T. J. Rosedahl|author8=J. C. Rubio|author9=M. S. Ware|journal=IBM Journal of Research and Development|volume=51|issue=6|pages=775–786|date=November 2007|doi=10.1147/rd.516.0775}} |
*{{cite journal|title=EnergyScale for IBM POWER6 microprocessor based systems|author1=H. -Y. McCreary|author2=M. A. Broyles|author3=M. S. Floyd|author4=A. J. Geissler|author5=S. P. Hartman|author6=F. L. Rawson|author7=T. J. Rosedahl|author8=J. C. Rubio|author9=M. S. Ware|journal=IBM Journal of Research and Development|volume=51|issue=6|pages=775–786|date=November 2007|doi=10.1147/rd.516.0775}} |
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*{{cite journal|title=System power management support in the IBM POWER6 microprocessor|author1=M. S. Floyd|author2=S. Ghiasi|author3=T. W. Keller|author4=K. Rajamani|author5=F. L. Rawson|author6=J. C. Rubio|author7=M. S. Ware|journal=IBM Journal of Research and Development|volume=51|issue=6|pages=733–746|date=November 2007|doi=10.1147/rd.516.0733|citeseerx=10.1.1.128.8084}} |
*{{cite journal|title=System power management support in the IBM POWER6 microprocessor|author1=M. S. Floyd|author2=S. Ghiasi|author3=T. W. Keller|author4=K. Rajamani|author5=F. L. Rawson|author6=J. C. Rubio|author7=M. S. Ware|journal=IBM Journal of Research and Development|volume=51|issue=6|pages=733–746|date=November 2007|doi=10.1147/rd.516.0733|citeseerx=10.1.1.128.8084}} |
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*{{cite journal|title=IBM POWER6 microarchitecture|author1=H. Q. Le|author2=W. J. Starke|author3=J. S. Fields|author4=F. P. |
*{{cite journal|title=IBM POWER6 microarchitecture|author1=H. Q. Le|author2=W. J. Starke|author3=J. S. Fields|author4=F. P. O'Connell|author5=D. Q. Nguyen|author6=B. J. Ronchetti|author7=W. M. Sauer|author8=E. M. Schwarz|author9=M. T. Vaden|journal=IBM Journal of Research and Development|volume=51|issue=6|pages=639–662|date=November 2007|doi=10.1147/rd.516.0639|citeseerx=10.1.1.115.6020}} |
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*{{cite journal|title=IBM POWER6 SRAM arrays|author1=D. W. Plass|author2=Y. H. Chan|journal=IBM Journal of Research and Development|volume=51|issue=6|pages=747–756|date=November 2007|doi=10.1147/rd.516.0747}} |
*{{cite journal|title=IBM POWER6 SRAM arrays|author1=D. W. Plass|author2=Y. H. Chan|journal=IBM Journal of Research and Development|volume=51|issue=6|pages=747–756|date=November 2007|doi=10.1147/rd.516.0747}} |
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*{{cite journal|title=IBM POWER6 accelerators: VMX and DFU|author1=L. Eisen|author2=J. W. Ward|author3=H. -W. Tast|author4=N. Mading|author5=J. Leenstra|author6=S. M. Mueller|author7=C. Jacobi|author8=J. Preiss|author9=E. M. Schwarz|author10=S. R. Carlough|journal=IBM Journal of Research and Development|volume=51|issue=6|pages=1–21|date=November 2007|doi=10.1147/rd.516.0663|citeseerx=10.1.1.128.3776}} |
*{{cite journal|title=IBM POWER6 accelerators: VMX and DFU|author1=L. Eisen|author2=J. W. Ward|author3=H. -W. Tast|author4=N. Mading|author5=J. Leenstra|author6=S. M. Mueller|author7=C. Jacobi|author8=J. Preiss|author9=E. M. Schwarz|author10=S. R. Carlough|journal=IBM Journal of Research and Development|volume=51|issue=6|pages=1–21|date=November 2007|doi=10.1147/rd.516.0663|citeseerx=10.1.1.128.3776}} |
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[[Category:Power microprocessors]] |
[[Category:Power microprocessors]] |
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[[Category:Computer-related introductions in 2007]] |
[[Category:Computer-related introductions in 2007]] |
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[[Category:64-bit microprocessors]] |
Latest revision as of 09:44, 16 January 2024
This article's use of external links may not follow Wikipedia's policies or guidelines. (September 2017) |
General information | |
---|---|
Launched | 2007 |
Designed by | IBM |
Performance | |
Max. CPU clock rate | 3.6 GHz to 5.0 GHz |
Cache | |
L1 cache | 64+64 KB/core |
L2 cache | 4 MB/core |
L3 cache | 32 MB/chip (off-chip) |
Architecture and classification | |
Technology node | 65 nm |
Instruction set | Power ISA (Power ISA v.2.05) |
Physical specifications | |
Cores |
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History | |
Predecessor | POWER5 |
Successor | POWER7 |
POWER, PowerPC, and Power ISA architectures |
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NXP (formerly Freescale and Motorola) |
IBM |
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IBM/Nintendo |
Other |
Related links |
Cancelled in gray, historic in italic |
The POWER6 is a microprocessor developed by IBM that implemented the Power ISA v.2.05. When it became available in systems in 2007, it succeeded the POWER5+ as IBM's flagship Power microprocessor. It is claimed to be part of the eCLipz project, said to have a goal of converging IBM's server hardware where practical (hence "ipz" in the acronym: iSeries, pSeries, and zSeries).[1]
History
[edit]POWER6 was described at the International Solid-State Circuits Conference (ISSCC) in February 2006, and additional details were added at the Microprocessor Forum in October 2006[2] and at the next ISSCC in February 2007. It was formally announced on May 21, 2007.[3] It was released on June 8, 2007 at speeds of 3.5, 4.2 and 4.7 GHz,[4] but the company has noted prototypes have reached 6 GHz.[5] POWER6 reached first silicon in the middle of 2005,[6] and was bumped to 5.0 GHz in May 2008 with the introduction of the P595.[7]
Description
[edit]The POWER6 is a dual-core processor. Each core is capable of two-way simultaneous multithreading (SMT). The POWER6 has approximately 790 million transistors and is 341 mm2 large fabricated on a 65 nm process. A notable difference from POWER5 is that the POWER6 executes instructions in-order instead of out-of-order. This change often requires software to be recompiled for optimal performance, but the POWER6 still achieves significant performance improvements over the POWER5+ even with unmodified software, according to the lead engineer on the POWER6 project.[4]
POWER6 also takes advantage of ViVA-2, Virtual Vector Architecture, which enables the combination of several POWER6 nodes to act as a single vector processor.[8]
Each core has two integer units, two binary floating-point units, an AltiVec unit, and a novel decimal floating-point unit. The binary floating-point unit incorporates "many microarchitectures, logic, circuit, latch and integration techniques to achieve [a] 6-cycle, 13-FO4 pipeline", according to a company paper.[9] Unlike the servers from IBM's competitors, the POWER6 has hardware support for IEEE 754 decimal arithmetic and includes the first decimal floating-point unit integrated in silicon. More than 50 new floating point instructions handle the decimal math and conversions between binary and decimal.[10] This feature was also added to the z10 microprocessor featured in the System z10.[8]
Each core has a 64 KB, four-way set-associative instruction cache and a 64 KB data cache of an eight-way set-associative design with a two-stage pipeline supporting two independent 32-bit reads or one 64-bit write per cycle.[9] Each core has semi-private 4 MiB unified L2 cache, where the cache is assigned a specific core, but the other has a fast access to it. The two cores share a 32 MiB L3 cache which is off die, using an 80 GB/s bus.[10]
POWER6 can connect to up to 31 other processors using two inter node links (50 GB/s), and supports up to 10 logical partitions per core (up to a limit of 254 per system). There is an interface to a service processor that monitors and adjusts performance and power according to set parameters.[11]
IBM also makes use of a 5 GHz duty-cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire that is 3 μm wide and 1.2 μm thick. The POWER6 design uses dual power supplies, a logic supply in the 0.8-to-1.2 Volt range and an SRAM power supply at about 150-mV higher.[9]
The thermal characteristics of POWER6 are similar to that of the POWER5. Dr Frank Soltis, an IBM chief scientist, said IBM had solved power leakage problems associated with high frequency by using a combination of 90 nm and 65 nm parts in the POWER6 design.[12]
POWER6+
[edit]The slightly enhanced POWER6+ was introduced in April 2009, but had been shipping in Power 560 and 570 systems since October 2008. It added more memory keys for secure memory partition, a feature taken from IBM's mainframe processors.[13]
Products
[edit]As of 2008[update], the range of POWER6 systems includes "Express" models (the 520, 550 and 560) and Enterprise models (the 570 and 595).[14] The various system models are designed to serve any sized business. For example, the 520 Express is marketed to small businesses while the Power 595 is marketed for large, multi-environment data centers. The main difference between the Express and Enterprise models is that the latter include Capacity Upgrade on Demand (CUoD) capabilities and hot-pluggable processor and memory "books".
Name | Number of sockets | Number of cores | CPU clock frequency |
---|---|---|---|
520 Express | 2 | 4 | 4.2 GHz or 4.7 GHz |
550 Express | 4 | 8 | 4.2 GHz or 5.0 GHz |
560 Express | 8 | 16 | 3.6 GHz |
570 | 8 | 16 | 4.4 GHz or 5.0 GHz |
570 | 16 | 32 | 4.2 GHz |
575 | 16 | 32 | 4.7 GHz |
595 | 32 | 64 | 4.2 GHz or 5.0 GHz |
IBM also offers four POWER6 based blade servers.[15] Specifications are shown in the table below.
Name | Number of cores | CPU clock frequency | Blade slots required |
---|---|---|---|
BladeCenter JS12 | 2 | 3.8 GHz | 1 |
BladeCenter JS22 | 4 | 4.0 GHz | 1 |
BladeCenter JS23 | 4 | 4.2 GHz | 1 |
BladeCenter JS43 | 8 | 4.2 GHz | 2 |
All blades support AIX, IBM i, and Linux. The BladeCenter S and H chassis is supported for blades running AIX, i, and Linux. The BladeCenter E, HT, and T chassis support blades running AIX and Linux but not i.
At the SuperComputing 2007 (SC07) conference in Reno a new water-cooled Power 575 was revealed. The 575 is composed of 2U "nodes" each with 32 POWER6 cores at 4.7 GHz with up to 256 GB of RAM. Up to 448 cores can be installed in a single frame.
Name | Number of cores | CPU clock frequency | Number of controllers |
---|---|---|---|
DS8700 | 2, 4 | 4.7 GHz | 1, 2 |
DS8800 | 2, 4, 8 | 5.0 GHz | 1, 2 |
See also
[edit]- IBM Power microprocessors
- POWER7
- z10, a mainframe processor sharing much technology with the POWER6.
References
[edit]- ^ "A Mainframe Roadmap". Isham Research. Archived from the original on 2016-03-03.
- ^ David Kanter (October 16, 2006). "Fall Processor Forum 2006: IBM's POWER6". Real World Technologies.
- ^ "IBM Unleashes World's Fastest Chip in Powerful New Computer" (Press release). IBM. Archived from the original on May 24, 2007.
- ^ a b "IBM POWER system hardware". IBM. Archived from the original on 2008-12-16. Retrieved 2008-10-09.
- ^ Vance, Ashlee (2006-02-07). "IBM thumbs nose at heat concerns, kicks Power6 to 6GHz". The Register. Retrieved 2006-02-07.
- ^ "IBM's Power6 Gets First Silicon as Power5+ Looms". IT Jungle. Archived from the original on 2005-11-25. Retrieved 2005-08-22.
- ^ "IBM smacks rivals with 5.0GHz Power6 beast". The Register. Retrieved 2008-10-12.
- ^ a b "An eCLipz Looms on the Horizon". Real World Technologies. Retrieved 2005-12-19.
- ^ a b c "IBM Tips Power6 Processor Architecture". InformationWeek. 6 February 2006. Retrieved 2022-07-13.
- ^ a b "Fall Processor Forum: Power6 at 5 GHz". Heinz Heise. Archived from the original on 2007-11-16. Retrieved 2006-10-12.
- ^ Merritt, Rick (2006-10-10). "IBM cranks dual-core Power6 beyond 4GHz". EE Times. Retrieved 2022-07-13.
- ^ Roger Howorth (2006-02-08). "IBM's Power6 processor to run at 4GHz in 2007". IT Week. Archived from the original on 2007-09-26. Retrieved 2007-07-11.
- ^ "IBM Power Systems Announcement Overview" (PDF). IBM. 28 April 2009. Archived from the original (PDF) on 13 May 2011. Retrieved 6 March 2018.
- ^ "IBM Power Systems Hardware". IBM. Archived from the original on May 12, 2008.
- ^ "IBM Power Systems Hardware - Blade Servers". IBM. Archived from the original on May 21, 2008.
External links
[edit]- IBM POWER6 Press Kit
- "IBM's Power6 gets help with math, multimedia". CNET. October 10, 2006.
- "IBM Debuts Power6 In New Unix Server". InformationWeek. May 21, 2007.
- "POWER6 set to carry the POWER4/POWER5/970 lineage forward?". Ars Technica. October 19, 2006.
- "IBM unveils POWER6 microprocessor details". Ars Technica. February 12, 2007.
- "IBM's POWER6 flies the coop at 4.7GHz". Ars Technica. May 21, 2007.
Recommended reading
[edit]- POWER Roadmap, IBM, Oct 2006
- M. J. Mack; W. M. Sauer; S. B. Swaney; B. G. Mealey (November 2007). "IBM POWER6 Reliability". IBM Journal of Research and Development. 51 (6): 763–774. doi:10.1147/rd.516.0763.
- R. Berridge; R. M. Averill; A. E. Barish; M. A. Bowen; P. J. Camporese; J. DiLullo; P. E. Dudley; J. Keinert; D. W. Lewis; R. D. Morel; T. Rosser; N. S. Schwartz; P. Shephard; H. H. Smith; D. Thomas; P. J. Restle; J. R. Ripley; S. L. Runyon; P. M. Williams (November 2007). "IBM POWER6 microprocessor physical design and design methodology". IBM Journal of Research and Development. 51 (6): 685–714. doi:10.1147/rd.516.0685.
- H. -Y. McCreary; M. A. Broyles; M. S. Floyd; A. J. Geissler; S. P. Hartman; F. L. Rawson; T. J. Rosedahl; J. C. Rubio; M. S. Ware (November 2007). "EnergyScale for IBM POWER6 microprocessor based systems". IBM Journal of Research and Development. 51 (6): 775–786. doi:10.1147/rd.516.0775.
- M. S. Floyd; S. Ghiasi; T. W. Keller; K. Rajamani; F. L. Rawson; J. C. Rubio; M. S. Ware (November 2007). "System power management support in the IBM POWER6 microprocessor". IBM Journal of Research and Development. 51 (6): 733–746. CiteSeerX 10.1.1.128.8084. doi:10.1147/rd.516.0733.
- H. Q. Le; W. J. Starke; J. S. Fields; F. P. O'Connell; D. Q. Nguyen; B. J. Ronchetti; W. M. Sauer; E. M. Schwarz; M. T. Vaden (November 2007). "IBM POWER6 microarchitecture". IBM Journal of Research and Development. 51 (6): 639–662. CiteSeerX 10.1.1.115.6020. doi:10.1147/rd.516.0639.
- D. W. Plass; Y. H. Chan (November 2007). "IBM POWER6 SRAM arrays". IBM Journal of Research and Development. 51 (6): 747–756. doi:10.1147/rd.516.0747.
- L. Eisen; J. W. Ward; H. -W. Tast; N. Mading; J. Leenstra; S. M. Mueller; C. Jacobi; J. Preiss; E. M. Schwarz; S. R. Carlough (November 2007). "IBM POWER6 accelerators: VMX and DFU". IBM Journal of Research and Development. 51 (6): 1–21. CiteSeerX 10.1.1.128.3776. doi:10.1147/rd.516.0663.
- "POWER: The Sixth Generation". (30 October 2006). Microprocessor Report.