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nvSRAM is a type of non-volatile random-access memory (NVRAM).^[1]^[2] nvSRAM extends the functionality of basic SRAM by adding non-volatile storage such as an EEPROM to the SRAM chip. In operation, data is written to and read from the SRAM portion with high-speed access; the data in SRAM can then be stored into or retrieved from the non-volatile storage at lower speeds when needed.

nvSRAM is one of the advanced NVRAM technologies that are fast replacing the battery-backed static random-access memory (BBSRAM), especially for applications that need battery-free solutions and long-term retention at SRAM speeds. nvSRAMs are used in a wide range of situations: networking, aerospace, and medical, among many others^[3] where the preservation of data is critical and where batteries are impractical.

nvSRAM is faster than EPROM and EEPROM solutions.^{[citation needed]}

Description

When reading and writing data, a nvSRAM acts no differently than a standard asynchronous SRAM. The attached processor or controller sees an 8-bit SRAM interface and nothing else. An added STORE operation stores data that is in an SRAM array in the non-volatile part. Cypress and Simtek nvSRAM have three ways to store data in the non-volatile area. They are:

autostore: happens automatically when the data main voltage source drops below the device's operating voltage. When this occurs, the power control is switched from V_CC to a capacitor. The capacitor will power the chip long enough to store the SRAM contents into the non-volatile part.
hardware store: the HSB (Hardware Store Busy) pin externally initiates a non-volatile hardware store operation. Using the HSB signal, which requests a non-volatile hardware STORE cycle, is optional.
software store: is initiated by a certain sequence of operations. When the defined operations are done in sequence the software store is initiated.

nvSRAM with SONOS technology

SONOS is a cross-sectional structure of MOSFET used in Non-volatile memory such as EEPROM and flash memories. nvSRAM combines the standard SRAM cells with EEPROM cells in SONOS technology^[4] to provide a fast read/write access and 20 years of data retention without power. The SRAM cells are paired one-to-one with EEPROM cells. The nvSRAMs are in the CMOS process, with the EEPROM cells having a SONOS stack to provide nonvolatile storage. When normal power is applied, the device looks and behaves in a similar manner as a standard SRAM. However, when power drops out, each cell’s contents can be stored automatically in the nonvolatile element positioned above the SRAM cell. This nonvolatile element uses standard CMOS process technology to obtain the high performance of standard SRAMs. In addition, the SONOS technology is highly reliable and supports 1 million STORE operations

The SONOS memory^[5] uses an insulating layer such as silicon nitride with traps as the charge storage layer. The traps in the nitride capture the carriers injected from the channel and retain the charge. This type of memory is also known as “Charge Trap Memory.” Since the charge storage layer is an insulator, this storage mechanism is inherently less sensitive to the tunnel oxide defects and is more robust for data retention. In SONOS, the Oxide-Nitride-Oxide(ONO) stack is engineered to maximize the charge-trapping efficiency during erase and program operations and minimize the charge loss during the retention by controlling the deposition parameters in the ONO formation.

Advantages of SONOS technology:

lower voltages required for program/erase operations compared to floating-gate MOSFET
Inherently less sensitive to the tunnel oxide defects
Robust data retention

Applications

Data logging
POS terminals/smart terminals
Terminals can store payment transaction records locally for later processing, reducing delays and intrusion vulnerability.
Motor vehicle crash boxes
Medical equipment
High-end servers
Environments where batteries for BBSRAMs are unfeasible
Remote devices where field service is unfeasible

Comparisons with other types of memories

	nvSRAM	BBSRAM	Ferroelectric RAM	Magnetoresistive random-access memory
Technique	Has non-volatile elements along with high performance SRAM	Has a lithium energy source for power when external power is off	Has a ferroelectric crystal between two electrodes to form a capacitor. The moment of atoms on application of electric field is used to store data	Similar to ferroelectric RAM, but the atoms align themselves in the direction of an external magnetic force. This effect is used to store data
Data retention	20 yrs	7 yrs, dependent on battery and ambient temperature	10 yrs	20 yrs
Endurance	Unlimited while powered	Limited to battery life	10¹⁰ to 10¹⁴ ^[6]^[7]	10⁸ ^[8]
Store mechanism	Autostore initiated when V_CC power down is detected.	Chip enable must be maintained at high logic to prevent inadvertent read/writes.	Static operation. Data is stored in the non-volatile part only.
Power up data restore	Non-volatile data is made available automatically in the SRAM.	SRAM will switch from battery to V_CC.
Substitution with SRAM	nvSRAM can be substituted for SRAM with minor board modification to add external capacitor.	Provision for battery necessitates board redesign to accommodate a bigger size for the battery	Some parts are pin-to-pin compatible with existing SRAMs.	Pin-to-pin compatible with existing SRAMs
Soldering	Standard SMT used	Reflow solder cannot be done with battery installed as batteries may explode.	Standard SMT used
Speed (best)	15–45 ns	70–100 ns	55 ns	35 ns

References

^ Ma, Yanjun; Kan, Edwin (2017). Non-logic Devices in Logic Processes. Springer. ISBN 9783319483399.
^ Xie, Yuan (2013). Emerging Memory Technologies: Design, Architecture, and Applications. Springer Science & Business Media. ISBN 9781441995513.
^ Computer organization (4th ed.). [S.l.]: McGraw-Hill. 1996. ISBN 0-07-114323-8.
^ https://www.cypress.com/file/46216/download
^ Ramkumar, Krishnaswamy; Prabhakar, Venkataraman; Geha, Sam. "Cypress SONOS Technology". infineon.com. Retrieved 30 June 2021.
^ https://www.fujitsu.com/us/Images/MB85R4001A-DS501-00005-3v0-E.pdf ^{[bare URL PDF]}
^ http://www.cypress.com/file/136476/download
^ "StackPath".

External links

[Ma_2017-1] Ma, Yanjun; Kan, Edwin (2017). Non-logic Devices in Logic Processes. Springer. ISBN 9783319483399.

[Xie_2013-2] Xie, Yuan (2013). Emerging Memory Technologies: Design, Architecture, and Applications. Springer Science & Business Media. ISBN 9781441995513.

[3] Computer organization (4th ed.). [S.l.]: McGraw-Hill. 1996. ISBN 0-07-114323-8.

[4] ttps://www.cypress.com/file/46216/download

[5] Ramkumar, Krishnaswamy; Prabhakar, Venkataraman; Geha, Sam. "Cypress SONOS Technology". infineon.com. Retrieved 30 June 2021.

[6] ttps://www.fujitsu.com/us/Images/MB85R4001A-DS501-00005-3v0-E.pdf ^{[bare URL PDF]}

[7] ttp://www.cypress.com/file/136476/download

[8] "StackPath".

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@@ Line 1: / Line 1: @@
+{{Cleanup bare URLs|date=September 2022}}
-{{lowercase}}
+[[File:LSI Logic 01-01037-07 - ZMD UL634H256SC-2356.jpg|thumb|nvSRAM [[ZMDI|ZMD]] UL634H256SC]]
-{{refimprove|date=September 2007}}
+{{lowercase title}}
+{{more citations needed|date=September 2007}}
 '''nvSRAM''' is a type of [[non-volatile random-access memory]] (NVRAM).<ref name="Ma 2017">
-{{cite book|last1=Ma|first1=Yanjun|last2=Kan|first2=Edwin|title=Non-logic Devices in Logic Processes|date=2017|publisher=Springer|isbn=9783319483399|url=https://books.google.com/books?id=1_iODgAAQBAJ&pg=PA211&dq=nvSRAM#v=onepage&q=nvSRAM|language=en}}
+{{cite book|last1=Ma|first1=Yanjun|last2=Kan|first2=Edwin|title=Non-logic Devices in Logic Processes|date=2017|publisher=Springer|isbn=9783319483399|url=https://books.google.com/books?id=1_iODgAAQBAJ&q=nvSRAM&pg=PA211|language=en}}
+</ref><ref name="Xie 2013">{{cite book|last1=Xie|first1=Yuan|title=Emerging Memory Technologies: Design, Architecture, and Applications|date=2013|publisher=Springer Science & Business Media|isbn=9781441995513|url=https://books.google.com/books?id=k8-4BAAAQBAJ&q=nvSRAM&pg=PA103|language=en}}</ref> nvSRAM extends the functionality of basic SRAM by adding non-volatile storage such as an [[EEPROM]] to the SRAM chip. In operation, data is written to and read from the SRAM portion with high-speed access; the data in SRAM can then be stored into or retrieved from the non-volatile storage at lower speeds when needed.
-</ref><ref name="Xie 2013">
-{{cite book|last1=Xie|first1=Yuan|title=Emerging Memory Technologies: Design, Architecture, and Applications|date=2013|publisher=Springer Science & Business Media|isbn=9781441995513|url=https://books.google.com/books?id=k8-4BAAAQBAJ&pg=PA103&dq=nvSRAM|language=en}}
-</ref>
-It is similar in operation to [[static random-access memory]] (SRAM).  <!-- The current market for non-volatile memory is dominated by BBSRAMs; battery-backed static random-access memory.  However, BBSRAMs are slow and suffer from [[Restriction of Hazardous Substances Directive|RoHS]] compliance issues.  nvSRAMs provide 20&nbsp;ns or lesser access times. -->
-nvSRAM is one of the advanced NVRAM technologies that is fast replacing the BBSRAMs; battery-backed static random-access memory, especially for applications that need battery free solutions and long term retention at SRAM speeds. nvSRAMs are used in a wide range of situations—networking, aerospace, and medical, among many others<ref>{{cite book|title=Computer organization.|url=https://archive.org/details/isbn_9780071143097|url-access=registration|publisher=McGraw-Hill|location=[S.l.]|isbn=0-07-114323-8|edition=4th}}</ref>—where the preservation of data is critical and where batteries are impractical.
+nvSRAM is one of the advanced NVRAM technologies that are fast replacing the battery-backed static random-access memory (BBSRAM), especially for applications that need battery-free solutions and long-term retention at SRAM speeds. nvSRAMs are used in a wide range of situations: networking, aerospace, and medical, among many others<ref>{{cite book|title=Computer organization.|year=1996|url=https://archive.org/details/isbn_9780071143097|url-access=registration|publisher=McGraw-Hill|location=[S.l.]|isbn=0-07-114323-8|edition=4th}}</ref> where the preservation of data is critical and where batteries are impractical.
+nvSRAM is faster than EPROM and EEPROM solutions.{{citation needed|date=June 2021}}
-Some products named nvSRAM are available from [[Cypress Semiconductor]], which is a combination of SRAM and [[SONOS]] based [[non-volatile memory]].<ref>http://www.electronicsweekly.com/products/2008/07/15/20229/cypress-cy14b102-2mbit-and-cy14b108-8mbit-nvsrams.htm</ref>  But they seem to have different internal structure from the memory cells in referenced books.<ref name="Ma 2017"/><ref name="Xie 2013"/>
-It is faster than EPROM and EEPROM solutions.  There are other nvSRAM products from [[Maxim Integrated]], those are essentially BBSRAMs.  They have a [[lithium battery]] built into the SRAM package.  These are faster than EPROM and EEPROM solutions.
-<!-- It is an efficient replacement for BBSRAM, [[EPROM]] or [[EEPROM]].
-It is better than BBSRAM solution because no external battery is used. -->
-(Refer to [[#External links|External links]] section.)
 ==Description==
+When reading and writing data, a nvSRAM acts no differently than a standard asynchronous SRAM. The attached processor or controller sees an [[8-bit]] SRAM interface and nothing else.  An added STORE operation stores data that is in an SRAM array in the non-volatile part.  Cypress and Simtek nvSRAM have three ways to store data in the non-volatile area.  They are:
-<!-- Unsourced image removed: [[File:nvsram.jpg]]  -->
-<!-- Deleted image removed: [[File:wiki-picture.jpg]] -->
-<!--This is the basic block diagram of a nvSRAM.  -->Externally, nvSRAM looks like standard SRAM.  However, on the inside, an nvSRAM is capable of doing more than a standard SRAM.  While SRAM can [[read-write memory|read and write]],  nvSRAM can read, write, store and recall.  The additional operations center around the non-volatile part of nvSRAM.
+# autostore: happens automatically when the data main [[voltage source]] drops below the device's operating voltage.  When this occurs, the power control is switched from [[IC power supply pin|V<sub>CC</sub>]] to a [[capacitor]]. The capacitor will power the chip long enough to store the SRAM contents into the non-volatile part.
-When reading and writing, an nvSRAM acts no differently than a standard async SRAM.  The attached processor or controller sees an [[8-bit]] SRAM interface and nothing else.  The STORE operation stores data that is in a SRAM array in the non-volatile part.  Cypress and Simtek nvSRAM have three ways to store data in the non-volatile area.  They are:
+# hardware store: the HSB (Hardware Store Busy) pin externally initiates a non-volatile hardware store operation. Using the HSB signal, which requests a non-volatile hardware STORE cycle, is optional.
+# software store: is initiated by a certain sequence of operations. When the defined operations are done in sequence the software store is initiated.
+==nvSRAM with SONOS technology==
-# autostore,
+[[File:NvSRAM-SONOS-technology.png|thumb|NvSRAM-SONOS-technology]]
-# hardware store,
+[[SONOS]] is a cross-sectional structure of [[MOSFET]] used in Non-volatile memory such as [[EEPROM]] and [[flash memories]].
-# software store.
+nvSRAM combines the standard SRAM cells with EEPROM cells in SONOS technology<ref>https://www.cypress.com/file/46216/download</ref> to provide a fast read/write access and 20 years of data retention without power. The SRAM cells are paired one-to-one with EEPROM cells. The nvSRAMs are in the CMOS process, with the EEPROM cells having a SONOS stack to provide nonvolatile storage. When normal power is applied, the device looks and behaves in a similar manner as a standard SRAM. However, when power drops out, each cell’s contents can be stored automatically in the nonvolatile element positioned above the SRAM cell. This nonvolatile element uses standard CMOS process technology to obtain the high performance of standard SRAMs. In addition, the SONOS technology is highly reliable and supports 1 million STORE operations
+The SONOS memory<ref>{{cite web |last1=Ramkumar |first1=Krishnaswamy |last2=Prabhakar |first2=Venkataraman |last3=Geha |first3=Sam |title=Cypress SONOS Technology |url=https://www.cypress.com/file/123341/download |website=infineon.com |access-date=30 June 2021}}</ref> uses an insulating layer such as silicon nitride with traps as the charge storage layer. The traps in the nitride capture the carriers injected from the channel and retain the charge. This type of memory is also known as “'''Charge Trap Memory'''.” Since the charge storage layer is an insulator, this storage mechanism is inherently less sensitive to the tunnel oxide defects and is more robust for data retention. In SONOS, the Oxide-Nitride-Oxide(ONO) stack is engineered to maximize the charge-trapping efficiency during erase and program operations and minimize the charge loss during the retention by controlling the deposition parameters in the ONO formation.
-Autostore happens automatically when the data main [[voltage source]] drops below the device's operating voltage.  When this occurs, the power control is switched from [[IC power supply pin|Vcc]] to the [[capacitor]].  The capacitor will power the chip long enough to store the SRAM contents into the non-volatile part.  The HSB (Hardware Store Busy) pin externally initiates a non-volatile hardware store operation. Using the HSB signal, which requests a non-volatile hardware STORE cycle, is optional.  Software store is initiated by a certain sequence of operations.  When the defined operations are done in sequence the software store is initiated.
+'''Advantages of SONOS technology:'''
+* lower voltages required for program/erase operations compared to [[floating-gate MOSFET]]
+* Inherently less sensitive to the tunnel oxide defects
+* Robust data retention
 ==Applications==
+* [[Data logging]]
-[[Data logging]] is one main area where nvSRAMs are needed.  [[Point of sale|POS]] terminals/smart terminals are now able to approve [[Financial transaction|payment transactions]] without having to obtain approval from a remote [[Server (computing)|server]].  Because secure data resides in the terminal, a lot of time could be saved in terms of the over-the-air verification which is slow as well as intrusion prone.
+* [[Point of sale|POS]] terminals/smart terminals
+*: Terminals can store [[Financial transaction|payment transaction]] records locally for later processing, reducing delays and intrusion vulnerability.
-[[Motor vehicle]] [[Event data recorder|crash boxes]] are another area where nvSRAMs could be employed effectively.  The vehicle state data at the time of the crash can go a long way in validating the claims and finding the reason of the crash.  This has huge financial implications in the [[insurance]] industry, and the concept of having crash boxes in passenger/[[commercial vehicle]]s could become a de facto standard in near future.  nvSRAMs with their fast [[Read-write memory|read/write]] capabilities is a good fit for this application.
+* [[Motor vehicle]] [[Event data recorder|crash boxes]]
+* [[Medical equipment]]
-Similar critical applications such as [[medical equipment]] and high end servers can use nvSRAMs to store their data.  In case of external [[Power outage|power failure]], or unforeseen calamities, nvSRAM can hold the data without external intervention (autostore feature).  Hence it would provide the flexibility of an EEPROM but at SRAM speeds.
+* High-end servers
+* Environments where batteries for BBSRAMs are unfeasible
-Applications in environments where field service is not possible/costly such as data loggers spread across geographies, routers, equipment in inhospitable conditions can use nvSRAMs, because nvSRAM does not use [[Battery (electricity)|batteries]], which have a risk of exploding/releasing harmful chemicals in harsh environments.
+* Remote devices where field service is unfeasible
-In short, nvSRAMs are suited for applications that need to store critical [[data]], but no field service.
 ==Comparisons with other types of memories==
@@ Line 52: / Line 51: @@
 |-
 ! Technique
-| Has [[Non-volatile memory|non-volatile]] elements along with high performance [[Static random-access memory|SRAM]]
+| Has [[non-volatile memory|non-volatile]] elements along with high performance [[static random-access memory|SRAM]]
-| Has a [[Button cell|lithium]] energy source for power when [[Power supply|external power]] is off
+| Has a [[button cell|lithium]] energy source for power when [[power supply|external power]] is off
-| Has a [[ferroelectric]] crystal between two [[electrode]]s to form a [[capacitor]].  The [[Magnetic_moment#Magnetic_moment_of_an_atom|moment of atoms]] on application of electric field is used to store data
+| Has a [[ferroelectric]] crystal between two [[electrode]]s to form a [[capacitor]].  The [[Magnetic moment#Magnetic moment of an atom|moment of atoms]] on application of electric field is used to store data
 | Similar to ferroelectric RAM, but the atoms align themselves in the direction of an external [[Magnetic field|magnetic force]].  This effect is used to store data
 |-
 ! Data retention
-| 20 [[Year|yrs]] || 7 yrs, dependent on battery and [[ambient temperature]] || 10 yrs || 20 yrs
+| 20 [[year|yrs]] || 7 yrs, dependent on battery and [[ambient temperature]] || 10 yrs || 20 yrs
 |-
 ! Endurance
+| Unlimited while powered || Limited to battery life || 10<sup>10</sup> to 10<sup>14</sup> <ref>https://www.fujitsu.com/us/Images/MB85R4001A-DS501-00005-3v0-E.pdf {{Bare URL PDF|date=March 2022}}</ref><ref>http://www.cypress.com/file/136476/download</ref> || 10<sup>8</sup> <ref>{{cite web | url=http://www.electronicdesign.com/industrial-automation/unleashing-mram-persistent-memory | title=StackPath }}</ref>
-| Unlimited || Limited || 10<sup>10</sup> - 10<sup>14</sup> || 10<sup>8</sup>
 |-
 ! Store mechanism
-| Autostore initiated when [[IC power supply pin|Vcc]] power down is detected
+| Autostore initiated when [[IC power supply pin|V<sub>CC</sub>]] power down is detected.
-| Chip enable must be maintained at high logic to prevent inadvertent [[Read-write memory|read/writes]]
+| Chip enable must be maintained at high logic to prevent inadvertent [[read–write memory|read/writes]].
-| rowspan="2" colspan="2" style="text-align:center;" | Static operation. Data is stored in the non-volatile part only
+| rowspan="2" colspan="2" style="text-align:center;" | Static operation. Data is stored in the non-volatile part only.
 |-
 ! Power up data restore
-| Non-volatile data is made available automatically in the SRAM
+| Non-volatile data is made available automatically in the SRAM.
-| SRAM will switch from battery to Vcc
+| SRAM will switch from battery to V<sub>CC</sub>.
 |-
 ! Substitution with SRAM
-| nvSRAM can be substituted for SRAM with minor board modification to add external capacitor
+| nvSRAM can be substituted for SRAM with minor board modification to add external capacitor.
-| Provision for [[Battery (electricity)|battery]] necessitates board redesign to accommodate bigger size for the battery
+| Provision for [[Battery (electricity)|battery]] necessitates board redesign to accommodate a bigger size for the battery
-| Some parts are pin-to-pin compatible with existing SRAMs
+| Some parts are pin-to-pin compatible with existing SRAMs.
 | Pin-to-pin compatible with existing SRAMs
 |-
 ! Soldering
 | Standard [[Surface-mount technology|SMT]] used
-| [[Reflow soldering|Reflow solder]] cannot be done with battery installed as batteries may explode
+| [[Reflow soldering|Reflow solder]] cannot be done with battery installed as batteries may explode.
 | colspan="2" style="text-align:center;" | Standard SMT used
 |-