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{{Short description|1998 microprocessor}}
{{other uses|mP 6 (disambiguation)}}
{{other uses|mP 6 (disambiguation)}}
{{lower case|mP6}}
{{lower case|mP6}}
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| size-to = 0.18 µm
| size-to = 0.18 µm
| soldby = [[Rise Technology]]
| soldby = [[Rise Technology]]
| designfirm = Rise Technology
| designfirm = Rise Technology
| manuf1 = [[TSMC]]<ref>{{cite web |url=http://alasir.com/x86ref/index2.html |title=32 BITS: SUPERSCALAR: 4.26. Rise iDragon mP6 |accessdate=3 November 2011 |archive-url=https://web.archive.org/web/20120421033425/http://alasir.com/x86ref/index2.html |archive-date=21 April 2012 |url-status=dead }}</ref>
| manuf1 = [[TSMC]]<ref>{{cite web |url=http://alasir.com/x86ref/index2.html |title=32 BITS: SUPERSCALAR: 4.26. Rise iDragon mP6 |accessdate=3 November 2011 |archive-url=https://web.archive.org/web/20120421033425/http://alasir.com/x86ref/index2.html |archive-date=21 April 2012 |url-status=dead }}</ref>
| core1 = Kirin
| core1 = Kirin
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| pack1 = [[Ball grid array|BGA-387]]
| pack1 = [[Ball grid array|BGA-387]]
| pack2 = [[Ceramic pin grid array|CGPA-296]]
| pack2 = [[Ceramic pin grid array|CGPA-296]]
| brand1 =
| brand1 =
| arch = [[x86]] ([[IA-32]])
| arch = [[x86-16]], [[IA-32]]
| microarch = 8-stage ([[Integer (computer science)|integer]])/4-stage ([[Floating point]]), triple pipelined design
| microarch = 8-stage ([[Integer (computer science)|integer]])/4-stage ([[Floating point]]), triple pipelined design
| cpuid = 00000504 (Kirin)<br />00000521 (Lynx)<ref>{{cite web |title=x86, x64 Instruction Latency, Memory Latency and CPUID dumps |url=http://www.freeweb.hu/instlatx64/ |date=22 October 2011 |accessdate=3 November 2011}}</ref>
| cpuid = 00000504 (Kirin)<br />00000521 (Lynx)<ref>{{cite web |title=x86, x64 Instruction Latency, Memory Latency and CPUID dumps |url=http://www.freeweb.hu/instlatx64/ |date=22 October 2011 |accessdate=3 November 2011}}</ref>
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| l2cache = Motherboard dependent
| l2cache = Motherboard dependent
| l3cache = none
| l3cache = none
| application =
| application =
| predecessor =
| predecessor =
| successor = Rise mP6-II
| successor = Rise mP6-II
}}
}}
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===Use===
===Use===
Announced in 1998, the chip never achieved widespread use,{{citation needed|date=August 2011}} and Rise quietly exited the market in December of the following year.
Announced in 1998, the chip never achieved widespread use,{{citation needed|date=August 2011}} and Rise quietly exited the market in December of the following year.


Like competitors [[Cyrix]] and [[Integrated Device Technology|IDT]], Rise found it was unable to compete with [[Intel]] and [[AMD]].
Like competitors [[Cyrix]] and [[Integrated Device Technology|IDT]], Rise found it was unable to compete with [[Intel]] and [[AMD]].
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==Legacy==
==Legacy==
[[File:DM&P Vortex86DX.jpg|thumb|left|110px|A Vortex86DX]]
[[File:DM&P Vortex86DX.jpg|thumb|left|110px|A Vortex86DX]]
[[Silicon Integrated Systems]] (SiS) licensed the mP6 technology, and used it in the SiS 550, a [[system-on-a-chip]] (SoC) that integrated the mP6 CPU, the north and south bridges, and sound and video on a single chip. The SiS 550 saw use in some compact PCs and in consumer devices, such as [[DVD]] players. The SiS 551 chip was also marketed by DM&P as [[Vortex86]] (M6127D).
[[Silicon Integrated Systems]] (SiS) licensed the mP6 technology, and used it in the SiS 550, a [[system-on-a-chip]] (SoC) that integrated the mP6 CPU, the north and south bridges, and sound and video on a single chip. The SiS 550 saw use in some compact PCs and in consumer devices, such as [[DVD]] players. The SiS 551 chip was also marketed by DM&P as [[Vortex86]] (M6127D).


Later DM&P took over mP6 design from SiS and continues development under [[Vortex86]] [[System-on-a-chip|SoC]] product line.
Later DM&P took over mP6 design from SiS and continues development under [[Vortex86]] [[System-on-a-chip|SoC]] product line.
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{| class="wikitable"
{| class="wikitable"
|+ The various models of the Rise mP6 with their [[Performance Rating|PR rating]], data from<ref name="CPUWorld"/><ref name="X-bitLAbs"/>
|+ The various models of the Rise mP6 with their [[Performance Rating|PR rating]], data from<ref name="CPUWorld"/><ref name="X-bitLAbs"/>
! Model number !! Frequency !! [[CPU_caches#Multi-level_caches|L1 Cache]] !! [[Front-side bus|FSB]] !! [[CPU multiplier|Mult.]] !! [[CPU core voltage|Voltage]] !! [[Thermal design power|TDP]] !! [[CPU socket|Socket]] !! Release date !! Part number(s) !! sSpec number !! Introduction price
! Model number !! Frequency !! [[CPU_caches#Multi-level_caches|L1 Cache]] !! [[Front-side bus|FSB]] !! [[CPU multiplier|Mult.]] !! [[CPU core voltage|Voltage]] !! [[Thermal design power|TDP]] !! [[CPU socket|Socket]] !! Release date !! Part number(s) !! Introduction price
|-
|-
| PR 166 || 166 [[MHz]] || 8 (data) +<br /> 8 (instructions) [[Kilobyte|KB]] || 83 [[Mhz]] || 2x || 2.75–2.85 [[Volt|V]] || 7.28 [[Watt|W]] || [[Super Socket 7]]<br />[[Ball grid array|BGA]] 387<br />[[Pin grid array|PPGA]] 296 || 13 October 1998 || MP6441RPFE4-Q || || $50
| PR 166 || 166 [[MHz]] || 8 (data) +<br /> 8 (instructions) [[Kilobyte|KB]] || 83 [[Mhz]] || 2× || 2.75–2.85 [[Volt|V]] || 7.28 [[Watt|W]] || [[Super Socket 7]]<br />[[Ball grid array|BGA]] 387<br />[[Pin grid array|PPGA]] 296 || 13 October 1998 || MP6441RPFE4-Q || $50
|-
|-
| PR 233 || 190 [[MHz]] || 8 (data) +<br /> 8 (instructions) [[Kilobyte|KB]] || 95 [[Mhz]] || 2x || 2.75–2.85 [[Volt|V]] || 8.11 [[Watt|W]] || [[Super Socket 7]]<br />[[Ball grid array|BGA]] 387<br />[[Pin grid array|PPGA]] 296 || 13 October 1998 || || ||
| PR 233 || 190 MHz || 8 (data) +<br /> 8 (instructions) KB || 95 Mhz || 2× || 2.75–2.85 V || 8.11 W || [[Super Socket 7]]<br />[[Ball grid array|BGA]] 387<br />[[Pin grid array|PPGA]] 296 || 13 October 1998 ||
|-
|-
| PR 266 || 200 [[MHz]] || 8 (data) +<br /> 8 (instructions) [[Kilobyte|KB]] || 100 [[Mhz]] || 2x || 2.75–2.85 [[Volt|V]] || 8.54 [[Watt|W]] || [[Super Socket 7]]<br />[[Ball grid array|BGA]] 387<br />[[Pin grid array|PPGA]] 296 || 13 October 1998 || MP6441DPFH4-Q<br />MP6441RPFH4-Q || || $70
| PR 266 || 200 MHz || 8 (data) +<br /> 8 (instructions) KB || 100 Mhz || 2× || 2.75–2.85 V]|| 8.54 W]|| [[Super Socket 7]]<br />[[Ball grid array|BGA]] 387<br />[[Pin grid array|PPGA]] 296 || 13 October 1998 || MP6441DPFH4-Q<br />MP6441RPFH4-Q || $70
|-
|-
| PR 333 || 240 [[MHz]] || 8 (data) +<br /> 8 (instructions) [[Kilobyte|KB]] || 95 [[Mhz]] || 2.5x || 2 [[Volt|V]] || 10.18 [[Watt|W]] || [[Super Socket 7]]<br />[[Ball grid array|BGA]] 387<br />[[Pin grid array|PPGA]] 296 || 26 May 1999<br />Samples only || MP65RPAPG5-ES || ||
| PR 333 || 240 MHz || 8 (data) +<br /> 8 (instructions) KB || 95 Mhz || 2.5× || 2 V || 10.18 W || [[Super Socket 7]]<br />[[Ball grid array|BGA]] 387<br />[[Pin grid array|PPGA]] 296 || 26 May 1999<br />Samples only || MP65RPAPG5-ES ||
|-
|-
| PR 366<ref>{{cite web |last=Shvets |first=Gennadiy |title=Rise Technology MP6 PR 366 |url=http://www.cpu-world.com/CPUs/MP6/Rise%20Technology-MP6%20PR%20366%20MHz%20-%20MP65RPAPH5-DS.html |work=CPU World |date=8 October 2011 |accessdate=1 November 2011}}</ref> || 250 [[Mhz|MHz]] || 8 (data) +<br /> 8 (instructions) [[Kilobyte|KB]] || 100 [[Mhz]] || 2.5x || 2 [[Volt|V]] || 10.72 [[Watt|W]] || [[Super Socket 7]]<br />[[Ball grid array|BGA]] 387<br />[[Pin grid array|PPGA]] 296 || 26 May 1999<br />Samples only || MP65RPAPH5-DS || ||
| PR 366<ref>{{cite web |last=Shvets |first=Gennadiy |title=Rise Technology MP6 PR 366 |url=http://www.cpu-world.com/CPUs/MP6/Rise%20Technology-MP6%20PR%20366%20MHz%20-%20MP65RPAPH5-DS.html |work=CPU World |date=8 October 2011 |accessdate=1 November 2011}}</ref> || 250 MHz || 8 (data) +<br /> 8 (instructions) KB || 100 Mhz || 2.5× || 2 |V || 10.72 W || [[Super Socket 7]]<br />[[Ball grid array|BGA]] 387<br />[[Pin grid array|PPGA]] 296 || 26 May 1999<br />Samples only || MP65RPAPH5-DS ||
|}
|}


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* [http://www.cpushack.com/2010/10/07/the-rise-of-the-vortex86-embedded-x86/ The Rise of the Vortex86: Embedded x86 Processors]
* [http://www.cpushack.com/2010/10/07/the-rise-of-the-vortex86-embedded-x86/ The Rise of the Vortex86: Embedded x86 Processors]


[[Category:Computer-related introductions in 1998]]
[[Category:Superscalar microprocessors]]
[[Category:Superscalar microprocessors]]
[[Category:X86 microprocessors|Rise]]
[[Category:X86 microprocessors|Rise]]

Latest revision as of 15:49, 20 June 2024

For other uses, see mP 6 (disambiguation).
Rise mP6
The Rise Technology mP6 microprocessor, the 387-ball BGA package mounted on a 296-pin Socket 7 PPGA adapter.
General information
Launched1998
Discontinued1999
Marketed byRise Technology
Designed byRise Technology
Common manufacturer
CPUID code00000504 (Kirin)
00000521 (Lynx)[2]
Product code6441
Performance
Max. CPU clock rate166 MHz to 250 MHz
FSB speeds83 Mhz to 100 Mhz
Cache
L1 cache16 KiB
L2 cacheMotherboard dependent
L3 cachenone
Architecture and classification
Technology node0.25 µm to 0.18 µm
Microarchitecture8-stage (integer)/4-stage (Floating point), triple pipelined design
Instruction setx86-16, IA-32
Physical specifications
Cores
  • 1
Packages
Socket
Products, models, variants
Core names
  • Kirin
  • Lynx
History
SuccessorRise mP6-II

The Rise mP6 was a superpipelined and superscalar[3] microprocessor designed by Rise Technology to compete with the Intel Pentium line.

History

[edit]

Rise Technology had spent 5 years developing a x86 compatible microprocessor,[4] and finally introduced it in November 1998 as a low-cost, low-power alternative for the Super Socket 7 platform, that allowed for higher Front-side bus speeds than the previous Socket 7 and that made it possible for other CPU manufacturers to keep competing against Intel, that had moved to the Slot 1 platform.

Design

[edit]

The mP6 made use of the MMX instruction set and had three MMX pipelines which allowed the CPU to execute up to three MMX instructions in a single cycle. Its three integer units made it possible to execute three integer instructions in a single cycle as well and the fully pipelined floating point unit could execute up to two floating-point instructions per cycle. To further improve the performance the core utilized branch prediction and a number of techniques to resolve data dependency conflicts.[3] According to Rise, the mP6 should perform almost as fast as Intel Pentium II at the same frequencies.[5]

Performance

[edit]

Despite its innovative features, the real-life performance of the mP6 proved disappointing. This was mainly due to the small L1 Cache.[5] Another reason was that the Rise mP6's PR 266 rating was based upon the old Intel Pentium MMX,[5] while its main competitors were the Intel Celeron 266, the IDT WinChip 2-266 and the AMD K6-2 266, that all delivered more performance in most benchmarks and applications.[5] The Celeron and the K6-2 actually worked at 266 MHz, and the WinChip 2's PR rating was based upon the performance of its AMD opponent.[5]

Use

[edit]

Announced in 1998, the chip never achieved widespread use,[citation needed] and Rise quietly exited the market in December of the following year.

Like competitors Cyrix and IDT, Rise found it was unable to compete with Intel and AMD.

Legacy

[edit]
A Vortex86DX

Silicon Integrated Systems (SiS) licensed the mP6 technology, and used it in the SiS 550, a system-on-a-chip (SoC) that integrated the mP6 CPU, the north and south bridges, and sound and video on a single chip. The SiS 550 saw use in some compact PCs and in consumer devices, such as DVD players. The SiS 551 chip was also marketed by DM&P as Vortex86 (M6127D).

Later DM&P took over mP6 design from SiS and continues development under Vortex86 SoC product line.

DM&P further signed an agreement with Xcore to allow them to rebrand the chip as Xcore86.[6]

mP6 data

[edit]
The various models of the Rise mP6 with their PR rating, data from[3][5]
Model number Frequency L1 Cache FSB Mult. Voltage TDP Socket Release date Part number(s) Introduction price
PR 166 166 MHz 8 (data) +
8 (instructions) KB		 83 Mhz 2× 2.75–2.85 V 7.28 W Super Socket 7
BGA 387
PPGA 296		 13 October 1998 MP6441RPFE4-Q $50
PR 233 190 MHz 8 (data) +
8 (instructions) KB		 95 Mhz 2× 2.75–2.85 V 8.11 W Super Socket 7
BGA 387
PPGA 296		 13 October 1998
PR 266 200 MHz 8 (data) +
8 (instructions) KB		 100 Mhz 2× 2.75–2.85 V] 8.54 W] Super Socket 7
BGA 387
PPGA 296		 13 October 1998 MP6441DPFH4-Q
MP6441RPFH4-Q		 $70
PR 333 240 MHz 8 (data) +
8 (instructions) KB		 95 Mhz 2.5× 2 V 10.18 W Super Socket 7
BGA 387
PPGA 296		 26 May 1999
Samples only		 MP65RPAPG5-ES
PR 366[7] 250 MHz 8 (data) +
8 (instructions) KB		 100 Mhz 2.5× V 10.72 W Super Socket 7
BGA 387
PPGA 296		 26 May 1999
Samples only		 MP65RPAPH5-DS

References

[edit]
  1. ^ "32 BITS: SUPERSCALAR: 4.26. Rise iDragon mP6". Archived from the original on 21 April 2012. Retrieved 3 November 2011.
  2. ^ "x86, x64 Instruction Latency, Memory Latency and CPUID dumps". 22 October 2011. Retrieved 3 November 2011.
  3. ^ a b c Shvets, Gennadiy (8 October 2011). "Rise Technology MP6 family". CPU World. Retrieved 1 November 2011.
  4. ^ "Rise mP6". CPU-collection.de. Retrieved 1 November 2011.
  5. ^ a b c d e f Gravrichenkov, Ilya (15 May 1999). "Rise mP6 266 Review". X-bit Laboratories. Archived from the original on 7 May 2009. Retrieved 1 November 2011.
  6. ^ Xcore Corporation Ltd. has entered into an agreement with DMP Electronics Inc. Archived 2009-04-04 at the Wayback Machine
  7. ^ Shvets, Gennadiy (8 October 2011). "Rise Technology MP6 PR 366". CPU World. Retrieved 1 November 2011.
[edit]
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