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{{short description|Electronic assembly containing multiple integrated circuits that behaves as a unit}}
{{Short description|Electronic assembly containing multiple integrated circuits that behaves as a unit}}
{{more citations needed|date=June 2013}}
{{more citations needed|date=June 2013}}
[[Image:Power5.jpg|thumb|280px|A ceramic multi-chip module containing four [[POWER5]] processor dies (center) and four 36 MB L3 cache dies (periphery).]]
[[Image:Power5.jpg|thumb|280px|A ceramic multi-chip module containing four [[POWER5]] processor dies (center) and four 36 MB L3 cache dies (periphery)]]


A '''multi-chip module''' (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or [[Lead (electronics)|"pins"]]) where multiple [[integrated circuit]]s (ICs or "chips"), semiconductor [[Die (integrated circuit)|dies]] and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC.<ref>
A '''multi-chip module''' ('''MCM''') is generically an electronic assembly (such as a package with a number of conductor terminals or [[Lead (electronics)|"pins"]]) where multiple [[integrated circuit]]s (ICs or "chips"), semiconductor [[Die (integrated circuit)|dies]] and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC.<ref>
{{cite web |url=http://electroiq.com/blog/2006/07/soc-vs-mcm-vs-sip-vs-sop/ |title=SoC vs. MCM vs SiP vs. SoP |last=Tummala |first=Rao |date=July 2006 |website=Solid State Technology |access-date=2015-08-04 |archive-url=https://web.archive.org/web/20131020045415/https://electroiq.com/blog/2006/07/soc-vs-mcm-vs-sip-vs-sop/|archive-date=2013-10-20 |url-status=dead}}</ref> Other terms for MCM packaging include "heterogeneous integration" or "[[hybrid integrated circuit]]".<ref>Don Scansen, EE Times "[https://www.eetimes.com/chiplets-a-short-history/ Chiplets: A Short History] Retrieved 26 April, 2021</ref> The advantage of using MCM packaging is it allows a manufacturer to use multiple components for modularity and/or to improve yields over a conventional monolithic IC approach.
Rao Tummala, Solid State Technology. “[http://electroiq.com/blog/2006/07/soc-vs-mcm-vs-sip-vs-sop/ SoC vs. MCM vs SiP vs. SoP].” Retrieved August 4, 2015.

</ref>
A '''Flip Chip Multi-Chip Module''' ('''FCMCM''') is a multi-chip module that uses [[flip chip]] technology. A FCMCM may have one large die and several smaller dies all on the same module.<ref>{{Cite web |title=IMAPS Advancing Microelectronics 2020 Issue 3 (Advanced SiP) |url=https://online.flippingbook.com/view/390153/12/?sharedOn= |access-date=2023-12-05 |website=FlippingBook}}</ref>
Other terms, such as "hybrid" or "[[hybrid integrated circuit]]", also refer to MCMs. The individual ICs that make up an MCM are known as '''chiplets'''.<ref>{{Cite web|url=https://en.wikichip.org/wiki/chiplet|title=Chiplet - WikiChip|website=en.wikichip.org}}</ref> Intel and AMD are using MCMs to improve performance and reduce costs, as splitting a large monolithic IC into smaller chiplets allows for easy performance improvements (easily allows for more transistors split across multiple chiplets), more ICs per wafer, and improved [[Semiconductor device fabrication#Device test|yield]], as smaller dies have a reduced risk of getting destroyed by dust particles and process variations during [[semiconductor fabrication]]. Each chiplet is physically smaller than a conventional monolithic IC die, (A monolithic IC is an [[IC package]] with a single IC).<ref>{{Cite journal|url=https://www.wired.com/story/keep-pace-moores-law-chipmakers-turn-chiplets/|title=To Keep Pace With Moore's Law, Chipmakers Turn to 'Chiplets'|journal=Wired|first=Tom|last=Simonite|date=November 6, 2018|via=www.wired.com}}</ref><ref>{{Cite web|url=https://www.engadget.com/2019/04/16/upscaled-cpu-chiplet/|title=Upscaled: This is the year of the CPU 'chiplet'|website=Engadget}}</ref> An example of MCMs in use for mainstream CPUs is [[AMD]]'s [[Zen 2]] design.


==Overview==
==Overview==
Multi-chip modules come in a variety of forms depending on the complexity and development philosophies of their designers. These can range from using pre-packaged ICs on a small [[printed circuit board]] (PCB) meant to mimic the package footprint of an existing chip package to fully custom chip packages integrating many chip dies on a high density interconnection (HDI) substrate.
Multi-chip modules come in a variety of forms depending on the complexity and development philosophies of their designers. These can range from using pre-packaged ICs on a small [[printed circuit board]] (PCB) meant to mimic the package footprint of an existing chip package to fully custom chip packages integrating many chip dies on a high density interconnection (HDI) substrate. The final assembled MCM substrate may be done in one of the following ways:


⚫
* The substrate is a multi-layer laminated [[printed circuit board]] (PCB), such as those used in AMD's [[Zen 2]] processors.
Multi-Chip Module packaging is an important facet of modern electronic miniaturization and micro-electronic systems. MCMs are classified according to the technology used to create the HDI substrate.
⚫
* The substrate is built on ceramic, such as [[low temperature co-fired ceramic]]
⚫
* The ICs are deposited on the base substrate using [[Thin Film]] technology.


The ICs that make up the MCM package may be:
⚫
* MCM-L – laminated MCM. The substrate is a multi-layer laminated [[printed circuit board]] (PCB).
* ICs that can perform most, if not all of the functions of a component of a computer, such as the CPU. Examples of this include implementations of IBM's [[POWER5]] and Intel's [[Core 2 Quad]]. Multiple copies of the same IC are used to build the final product. In the case of POWER5, multiple POWER5 processors and their associated off-die L3 cache are used to build the final package. With the Core 2 Quad, effectively two Core 2 Duo dies were packaged together.
⚫
* MCM-D – deposited MCM. The modules are deposited on the base substrate using thin film technology.
* ICs that perform only some of the functions, or "Intellectual Property Blocks" ("IP Blocks"), of a component in a computer. These are known as [[chiplet]]s.<ref>Samuel K. Moore, IEEE Spectrum "[https://spectrum.ieee.org/intels-view-of-the-chiplet-revolution Intel's View of the Chiplet Revolution]" Retrieved 26 April, 2021</ref><ref>Semi Engineering "[https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/chiplets/ Chiplets]" Retrieved 26 April, 2021</ref> An example of this are the processing ICs and I/O IC of AMD's [[Zen 2]]-based processors.
⚫
* MCM-C – ceramic substrate MCMs, such as [[low temperature co-fired ceramic]] (LTCC)


The PCB that interconnects the chiplets is known as an [[interposer]]. This is often either organic (PCB, used in AMD's [[Zen 2]] microarchitecture) or be made of silicon (as in [[High Bandwidth Memory]])<ref>https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/2-5d-ic/</ref> Both have their advantages and limitations.<ref>https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/2-5d-ic/interposers/</ref>
An [[interposer]] connects the ICs. This is often either organic (a laminated circuit board that contains carbon, hence ''organic'') or is made of silicon (as in [[High Bandwidth Memory]]).<ref>{{cite web|url=https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/2-5d-ic/ |title=2.5D - Semiconductor Engineering |publisher=Semiengineering.com |date= |accessdate=2022-05-13}}</ref> Each has advantages and limitations. Using interposers to connect several ICs instead of connecting several monolithic ICs in separate packages reduces the power needed to transmit signals between ICs, increases the number of transmission channels, and reduces delays caused by resistance and capacitance (RC delays).<ref>{{cite web|url=https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/2-5d-ic/interposers/|title = Interposers}}</ref> However, communication between chiplets consumes more power and has higher latency than components within monolithic ICs.<ref>Dr. Ian Cutress, AnandTech "[https://www.anandtech.com/show/16021/intel-moving-to-chiplets-client-20-for-7nm Intel Moving to Chiplets: 'Client 2.0' for 7nm]"</ref>


==Chip stack MCMs==
==Chip stack MCMs==
Line 23: Line 25:
A relatively new development in MCM technology is the so-called "chip-stack" package.<ref>{{cite web |url=http://www.fudzilla.com/26786-intel-migrates-to-desktop-multi-chip-module-mcm-with-14nm-br |author=Jon Worrel |date=15 April 2012 |title=Intel migrates to desktop Multi-Chip Modules (MCMs) with 14nm Broadwell |work=Fudzilla }}</ref> Certain ICs, memories in particular, have very similar or identical pinouts when used multiple times within systems. A carefully designed substrate can allow these dies to be stacked in a vertical configuration making the resultant MCM's footprint much smaller (albeit at the cost of a thicker or taller chip). Since area is more often at a premium in miniature electronics designs, the chip-stack is an attractive option in many applications such as cell phones and [[personal digital assistant]]s (PDAs). With the use of a [[3D integrated circuit]] and a thinning process, as many as ten dies can be stacked to create a high capacity SD memory card.<ref>Richard Chirgwin, The Register. “[https://www.theregister.co.uk/2013/04/02/hmc_publishes_3d_chip_spec/ Memory vendors pile on '3D' stacking standard].” April 2, 2013. February 5, 2016.</ref> This technique can also be used for [[High Bandwidth Memory]].
A relatively new development in MCM technology is the so-called "chip-stack" package.<ref>{{cite web |url=http://www.fudzilla.com/26786-intel-migrates-to-desktop-multi-chip-module-mcm-with-14nm-br |author=Jon Worrel |date=15 April 2012 |title=Intel migrates to desktop Multi-Chip Modules (MCMs) with 14nm Broadwell |work=Fudzilla }}</ref> Certain ICs, memories in particular, have very similar or identical pinouts when used multiple times within systems. A carefully designed substrate can allow these dies to be stacked in a vertical configuration making the resultant MCM's footprint much smaller (albeit at the cost of a thicker or taller chip). Since area is more often at a premium in miniature electronics designs, the chip-stack is an attractive option in many applications such as cell phones and [[personal digital assistant]]s (PDAs). With the use of a [[3D integrated circuit]] and a thinning process, as many as ten dies can be stacked to create a high capacity SD memory card.<ref>Richard Chirgwin, The Register. “[https://www.theregister.co.uk/2013/04/02/hmc_publishes_3d_chip_spec/ Memory vendors pile on '3D' stacking standard].” April 2, 2013. February 5, 2016.</ref> This technique can also be used for [[High Bandwidth Memory]].


The possible way to increasing the performance of data transfer in the Chip stack is use Wireless [[Network on a chip | Networks on Chip]] (WiNoC).<ref>Slyusar V. I., Slyusar D.V. Pyramidal design of nanoantennas array. // VIII International Conference on Antenna Theory and Techniques (ICATT’11). - Kyiv, Ukraine. - National Technical University of Ukraine “Kyiv Polytechnic Institute”. - September 20 - 23, 2011. - Pp. 140 - 142. [https://slyusar.kiev.ua/ICATT_2011_Slyusar2.pdf]</ref>
The possible way to increasing the performance of data transfer in the Chip stack is use Wireless [[Network on a chip|Networks on Chip]] (WiNoC).<ref>Slyusar V. I., Slyusar D.V. Pyramidal design of nanoantennas array. // VIII International Conference on Antenna Theory and Techniques (ICATT’11). - Kyiv, Ukraine. - National Technical University of Ukraine “Kyiv Polytechnic Institute”. - September 20–23, 2011. - Pp. 140 - 142. [https://slyusar.kiev.ua/ICATT_2011_Slyusar2.pdf]</ref>


==Examples of multi-chip technologies==
== Examples of multi-chip packages ==
*[[IBM]] [[Bubble memory]] MCMs (1970s)
* [[IBM]] [[Bubble memory]] MCMs (1970s)
*[[IBM 3081]] mainframe's thermal conduction module (1980s)
* [[IBM 3081]] mainframe's thermal conduction module (1980s)
*Superconducting Multichip modules (1990s)<ref>{{Cite book |doi = 10.1109/MCMC.1992.201478|isbn = 0-8186-2725-5|chapter = High-performance MCM interconnection circuits and fluxoelectronics|title = Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92|year = 1992|last1 = Ghoshal|first1 = U.|last2 = Van Duzer|first2 = T.|pages = 175–178}}</ref><ref>{{Cite journal |doi = 10.1063/1.108652|bibcode = 1993ApPhL..62.1435B|title = Multichip module using multilayer YBa2Cu3O7−δinterconnects|year = 1993|last1 = Burns|first1 = M. J.|last2 = Char|first2 = K.|last3 = Cole|first3 = B. F.|last4 = Ruby|first4 = W. S.|last5 = Sachtjen|first5 = S. A.|journal = Applied Physics Letters|volume = 62|issue = 12|pages = 1435–1437}}</ref>
* Superconducting Multichip modules (1990s)<ref>{{Cite book |doi = 10.1109/MCMC.1992.201478|isbn = 0-8186-2725-5|chapter = High-performance MCM interconnection circuits and fluxoelectronics|title = Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92|year = 1992|last1 = Ghoshal|first1 = U.|last2 = Van Duzer|first2 = T.|pages = 175–178|s2cid = 109329843}}</ref><ref>{{Cite journal |doi = 10.1063/1.108652|bibcode = 1993ApPhL..62.1435B|title = Multichip module using multilayer YBa2Cu3O7−δinterconnects|year = 1993|last1 = Burns|first1 = M. J.|last2 = Char|first2 = K.|last3 = Cole|first3 = B. F.|last4 = Ruby|first4 = W. S.|last5 = Sachtjen|first5 = S. A.|journal = Applied Physics Letters|volume = 62|issue = 12|pages = 1435–1437}}</ref>
*[[Intel]] [[Pentium Pro]], [[Pentium D]] Presler, [[Xeon]] Dempsey and Clovertown, [[Core 2 Quad]] (Kentsfield, Penryn-QC and Yorkfield), [[Clarkdale (microprocessor)|Clarkdale]], [[Arrandale]], and [[Haswell (microarchitecture)|Haswell-H]]
* [[Intel]] [[Pentium Pro]], [[Pentium II OverDrive]], [[Pentium D]] Presler, [[Xeon]] Dempsey, Clovertown, Harpertown and Tigerton, [[Core 2 Quad]] (Kentsfield, Penryn-QC and Yorkfield), [[Clarkdale (microprocessor)|Clarkdale]], [[Arrandale]], [[Kaby Lake-G]], and models with [[Crystalwell]] (those with the GT3e or GT4e graphics)
*[[SD card|Micro-SD cards]] and [[Sony]] [[Memory Stick|memory stick]]s
* [[SD card|SD cards]], [[micro SD|Micro-SD cards]] and [[Sony]] [[Memory Stick|memory stick]]s
*[[Xenos (graphics chip)|Xenos]], a [[Graphics processing unit|GPU]] designed by [[ATI Technologies]] for the [[Xbox 360]], with [[eDRAM]]
* [[eMMC]], [[eUFS]], and [[NVMe]] with single-package solution
* [[Xenos (graphics chip)|Xenos]], a [[Graphics processing unit|GPU]] designed by [[ATI Technologies]] for the [[Xbox 360]], with [[eDRAM]]
*[[POWER2]], [[POWER4]], [[POWER5]] and [[POWER7]] from [[IBM]]
* [[POWER2]], [[POWER4]], [[POWER5]], [[POWER7]], [[POWER8]], and [[Power10]] from [[IBM]]
*[[IBM z196]]
* [[IBM z196]]
*Nintendo's [[Wii U]] has its CPU, [[GPU]], and onboard VRAM (integrated into the GPU) on one MCM.<ref>Satoru Iwata, Iwata Asks. “[http://iwataasks.nintendo.com/interviews/#/wiiu/console/0/0 Changes in Television].” Retrieved August 4, 2015.</ref>
* Nintendo's [[Wii U]] [[Espresso (microprocessor)]] has its CPU, [[GPU]], and onboard VRAM (integrated into the GPU) on one MCM.<ref>Satoru Iwata, Iwata Asks. “[http://iwataasks.nintendo.com/interviews/#/wiiu/console/0/0 Changes in Television].” Retrieved August 4, 2015.</ref>
*[[VIA Nano]] QuadCore<ref>{{Cite web|url=https://www.anandtech.com/show/4332/vias-quadcore-nano-gets-bigger|title=VIA's QuadCore: Nano Gets Bigger|last=Shimpi|first=Anand Lal|website=www.anandtech.com|access-date=2020-04-10}}</ref>
* [[VIA Nano]] QuadCore<ref>{{cite web|url=https://www.anandtech.com/show/4332/vias-quadcore-nano-gets-bigger|title=VIA's QuadCore: Nano Gets Bigger|last=Shimpi|first=Anand Lal|website=www.anandtech.com|access-date=2020-04-10}}</ref>
*Flash and RAM memory combined on a [[Package on package|PoP]] by [[Micron Technology|Micron]]
* Flash and RAM memory combined on a [[Package on package|PoP]] by [[Micron Technology|Micron]]
*[[Samsung]] MCP solutions combining mobile [[DRAM]] and [[Flash memory#NAND flash|NAND]] storage.<ref>{{cite web|title=MCP (Multichip Package) {{!}} Samsung Semiconductor|url=http://www.samsung.com/semiconductor/mcp/|website=www.samsung.com|language=en}}</ref><ref>{{cite web|title=NAND based MCP {{!}} Samsung Memory Link|url=https://memorylink.samsung.com/ecomobile/mem/ecomobile/product/productOverview.do?topMenu=P&subMenu=mcp&partSetNo=MCP&partSetLabel=NAND%20based%20MCP|website=samsung.com}}</ref><ref>{{cite web|title=e-MMC based MCP {{!}} Samsung Memory Link|url=https://memorylink.samsung.com/ecomobile/mem/ecomobile/product/productOverview.do?topMenu=P&subMenu=mcp&partSetNo=eMCP&partSetLabel=e-MMC%20based%20MCP|website=samsung.com}}</ref>
* [[Samsung]] MCP solutions combining mobile [[DRAM]] and [[NAND flash|NAND]] storage.<ref>{{cite web|title=MCP (Multichip Package) &#124; Samsung Semiconductor|url=http://www.samsung.com/semiconductor/mcp/|website=www.samsung.com|language=en}}</ref><ref>{{cite web|title=NAND based MCP &#124; Samsung Memory Link|url=https://memorylink.samsung.com/ecomobile/mem/ecomobile/product/productOverview.do?topMenu=P&subMenu=mcp&partSetNo=MCP&partSetLabel=NAND%20based%20MCP|website=samsung.com}}</ref><ref>{{cite web|title=e-MMC based MCP &#124; Samsung Memory Link|url=https://memorylink.samsung.com/ecomobile/mem/ecomobile/product/productOverview.do?topMenu=P&subMenu=mcp&partSetNo=eMCP&partSetLabel=e-MMC%20based%20MCP|website=samsung.com}}</ref>
*AMD [[Ryzen Threadripper]] and [[Epyc]] CPUs based on [[Zen (microarchitecture)|Zen]] or [[Zen+]] architecture are MCMs of two or four chips<ref>{{Cite web|url=https://www.anandtech.com/show/11697/the-amd-ryzen-threadripper-1950x-and-1920x-review|title=The AMD Ryzen Threadripper 1950X and 1920X Review: CPUs on Steroids|last=Cutress|first=Ian|website=www.anandtech.com|access-date=2020-04-10}}</ref> ([[Ryzen]] based on Zen or Zen+ is not MCM and consist of one chip)
* AMD [[Ryzen|Ryzen Threadripper]] and [[Epyc]] CPUs based on [[Zen (microarchitecture)|Zen]] or [[Zen+]] architecture are MCMs of two or four chips<ref>{{cite web|url=https://www.anandtech.com/show/11697/the-amd-ryzen-threadripper-1950x-and-1920x-review|title=The AMD Ryzen Threadripper 1950X and 1920X Review: CPUs on Steroids|last=Cutress|first=Ian|website=www.anandtech.com|access-date=2020-04-10}}</ref> ([[Ryzen]] based on Zen or Zen+ is not MCM and consist of one chip)
*AMD [[Ryzen]], Ryzen Threadripper and Epyc CPUs based on [[Zen 2]] architecture are MCMs of one, two, four<ref>{{Cite web|url=https://hothardware.com/news/amd-ryzen-threadripper-3960x-3970x-zen-2-delidding|title=AMD Ryzen Threadripper 3960X, 3970X Meet Scalpel For Zen 2 Delidding Operation|last=Lilly|first=Paul|date=2019-12-17|website=HotHardware|language=en-us|access-date=2020-04-10}}</ref> or eight chips containing CPU cores and one bigger I/O chip<ref>{{Cite web|url=https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome|title=AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome|last=Cutress|first=Ian|website=www.anandtech.com|access-date=2020-04-10}}</ref>
* AMD's non-[[AMD Accelerated Processing Unit|APU]] [[Ryzen]], Ryzen Threadripper and Epyc CPUs based on the [[Zen 2]] or [[Zen 3]] architecture are MCMs of one, two, four<ref>{{cite web|url=https://hothardware.com/news/amd-ryzen-threadripper-3960x-3970x-zen-2-delidding|title=AMD Ryzen Threadripper 3960X, 3970X Meet Scalpel For Zen 2 Delidding Operation|last=Lilly|first=Paul|date=2019-12-17|website=HotHardware|language=en-us|access-date=2020-04-10}}</ref> or eight chips containing CPU cores and one bigger I/O chip<ref>{{cite web|url=https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome|title=AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome|last=Cutress|first=Ian|website=www.anandtech.com|access-date=2020-04-10}}</ref>
* [[AMD Instinct]] MI series GPUs based on [[CDNA 2]] architecture are MCMs of one or two graphics compute die (GCD) chips.
* AMD [[Radeon RX 7000 series]] GPUs based on [[RDNA 3]] architecture are MCMs with one GCD and up to six memory cache die (MCD) chips.
* [[Intel Xe#Ponte Vecchio|Intel Xe Ponte Vecchio]] GPUs
* Intel [[Meteor Lake]] CPUs
* Any other processor with [[High Bandwidth Memory]]
* Apple [[Apple silicon|M series]] with CPU and memory
* Intel [[Lunar Lake]] with CPU and memory


==3D multi-chip modules==
==3D multi-chip modules==
Line 46: Line 56:
==See also==
==See also==
* [[System in package]] (SIP)
* [[System in package]] (SIP)
* [[System on a chip]] (SoC)
* [[Hybrid integrated circuit]]
* [[Hybrid integrated circuit]]
* [[Advanced packaging (semiconductors)]]
* [[Chip carrier]] Chip packaging and package types list
* [[Chip carrier]] Chip packaging and package types list
* [[Single Chip Module]] (SCM)
* [[Single Chip Module]] (SCM)
* [[UFS Multi Chip Package]] (uMCP)


==References==
==References==
{{reflist}}
{{Reflist}}


== External links==
== External links==
Line 59: Line 72:


{{System on a chip}}
{{System on a chip}}
{{Authority control}}

[[Category:Chip carriers]]
[[Category:Chip carriers]]
[[Category:Modularity]]
[[Category:Modularity]]

Latest revision as of 14:16, 14 November 2024

A ceramic multi-chip module containing four POWER5 processor dies (center) and four 36 MB L3 cache dies (periphery)

A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or "pins") where multiple integrated circuits (ICs or "chips"), semiconductor dies and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC.[1] Other terms for MCM packaging include "heterogeneous integration" or "hybrid integrated circuit".[2] The advantage of using MCM packaging is it allows a manufacturer to use multiple components for modularity and/or to improve yields over a conventional monolithic IC approach.

A Flip Chip Multi-Chip Module (FCMCM) is a multi-chip module that uses flip chip technology. A FCMCM may have one large die and several smaller dies all on the same module.[3]

Overview

[edit]

Multi-chip modules come in a variety of forms depending on the complexity and development philosophies of their designers. These can range from using pre-packaged ICs on a small printed circuit board (PCB) meant to mimic the package footprint of an existing chip package to fully custom chip packages integrating many chip dies on a high density interconnection (HDI) substrate. The final assembled MCM substrate may be done in one of the following ways:

The ICs that make up the MCM package may be:

  • ICs that can perform most, if not all of the functions of a component of a computer, such as the CPU. Examples of this include implementations of IBM's POWER5 and Intel's Core 2 Quad. Multiple copies of the same IC are used to build the final product. In the case of POWER5, multiple POWER5 processors and their associated off-die L3 cache are used to build the final package. With the Core 2 Quad, effectively two Core 2 Duo dies were packaged together.
  • ICs that perform only some of the functions, or "Intellectual Property Blocks" ("IP Blocks"), of a component in a computer. These are known as chiplets.[4][5] An example of this are the processing ICs and I/O IC of AMD's Zen 2-based processors.

An interposer connects the ICs. This is often either organic (a laminated circuit board that contains carbon, hence organic) or is made of silicon (as in High Bandwidth Memory).[6] Each has advantages and limitations. Using interposers to connect several ICs instead of connecting several monolithic ICs in separate packages reduces the power needed to transmit signals between ICs, increases the number of transmission channels, and reduces delays caused by resistance and capacitance (RC delays).[7] However, communication between chiplets consumes more power and has higher latency than components within monolithic ICs.[8]

Chip stack MCMs

[edit]
Wireless NoC on 3D integrated circuit

A relatively new development in MCM technology is the so-called "chip-stack" package.[9] Certain ICs, memories in particular, have very similar or identical pinouts when used multiple times within systems. A carefully designed substrate can allow these dies to be stacked in a vertical configuration making the resultant MCM's footprint much smaller (albeit at the cost of a thicker or taller chip). Since area is more often at a premium in miniature electronics designs, the chip-stack is an attractive option in many applications such as cell phones and personal digital assistants (PDAs). With the use of a 3D integrated circuit and a thinning process, as many as ten dies can be stacked to create a high capacity SD memory card.[10] This technique can also be used for High Bandwidth Memory.

The possible way to increasing the performance of data transfer in the Chip stack is use Wireless Networks on Chip (WiNoC).[11]

Examples of multi-chip packages

[edit]

3D multi-chip modules

[edit]
Main articles: 3D integrated circuit and Package on package

See also

[edit]

References

[edit]
  1. ^ Tummala, Rao (July 2006). "SoC vs. MCM vs SiP vs. SoP". Solid State Technology. Archived from the original on 2013-10-20. Retrieved 2015-08-04.
  2. ^ Don Scansen, EE Times "Chiplets: A Short History Retrieved 26 April, 2021
  3. ^ "IMAPS Advancing Microelectronics 2020 Issue 3 (Advanced SiP)". FlippingBook. Retrieved 2023-12-05.
  4. ^ Samuel K. Moore, IEEE Spectrum "Intel's View of the Chiplet Revolution" Retrieved 26 April, 2021
  5. ^ Semi Engineering "Chiplets" Retrieved 26 April, 2021
  6. ^ "2.5D - Semiconductor Engineering". Semiengineering.com. Retrieved 2022-05-13.
  7. ^ "Interposers".
  8. ^ Dr. Ian Cutress, AnandTech "Intel Moving to Chiplets: 'Client 2.0' for 7nm"
  9. ^ Jon Worrel (15 April 2012). "Intel migrates to desktop Multi-Chip Modules (MCMs) with 14nm Broadwell". Fudzilla.
  10. ^ Richard Chirgwin, The Register. “Memory vendors pile on '3D' stacking standard.” April 2, 2013. February 5, 2016.
  11. ^ Slyusar V. I., Slyusar D.V. Pyramidal design of nanoantennas array. // VIII International Conference on Antenna Theory and Techniques (ICATT’11). - Kyiv, Ukraine. - National Technical University of Ukraine “Kyiv Polytechnic Institute”. - September 20–23, 2011. - Pp. 140 - 142. [1]
  12. ^ Ghoshal, U.; Van Duzer, T. (1992). "High-performance MCM interconnection circuits and fluxoelectronics". Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92. pp. 175–178. doi:10.1109/MCMC.1992.201478. ISBN 0-8186-2725-5. S2CID 109329843.
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