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Magnetoresistive random-access memory (MRAM) is a type of non-volatile random-access memory which stores data in magnetic domains.^[1] Developed in the mid-1980s, proponents have argued that magnetoresistive RAM will eventually surpass competing technologies to become a dominant or even universal memory.^[2] Currently, memory technologies in use such as flash RAM and DRAM have practical advantages that have so far kept MRAM in a niche role in the market.

Description

Simplified structure of an MRAM cell^[3]

Unlike conventional RAM chip technologies, data in MRAM is not stored as electric charge or current flows, but by magnetic storage elements. The elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. This configuration is known as a magnetic tunnel junction (MTJ) and is the simplest structure for an MRAM bit. A memory device is built from a grid of such "cells".

The simplest method of reading is accomplished by measuring the electrical resistance of the cell. A particular cell is (typically) selected by powering an associated transistor that switches current from a supply line through the cell to ground. Because of tunnel magnetoresistance, the electrical resistance of the cell changes with the relative orientation of the magnetization in the two plates. By measuring the resulting current, the resistance inside any particular cell can be determined, and from this the magnetization polarity of the writable plate. Typically if the two plates have the same magnetization alignment (low resistance state) this is considered to mean "1", while if the alignment is antiparallel the resistance will be higher (high resistance state) and this means "0".

Data is written to the cells using a variety of means. In the simplest "classic" design, each cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created at the junction, which the writable plate picks up. This pattern of operation is similar to magnetic-core memory, a system commonly used in the 1960s.

However, due to process and material variations, an array of memory cells has a distribution of switching fields with a deviation σ. Therefore, to program all the bits in a large array with the same current, the applied field needs to be larger than the mean "selected" switching field by greater than 6σ. In addition,the applied field must be kept below a maximum value. Thus, this "conventional" MRAM must keep these two distributions well-separated. As a result, there is a narrow operating window for programming fields; and only inside this window, can all the bits be programmed without errors or disturbs. In 2005, a "Savtchenko switching" relying on the unique behavior of a synthetic antiferromagnet (SAF) free layer is applied to solve this problem.^[4] The SAF layer is formed from two ferromagnetic layers separated by a nonmagnetic coupling spacer layer. For a synthetic antiferromagnet having some net anisotropy Hk in each layer, there exists a critical spin flop field Hsw at which the two antiparallel layer magnetizations will rotate (flop) to be orthogonal to the applied field H with each layer scissoring slightly in the direction of H. Therefore, if only a single line current is applied (half-selected bits), the 45° field angle cannot switch the state. Below the toggling transition, there are no disturbs all the way up to the highest fields.

This approach still requires a fairly substantial current to generate the field, however, which makes it less interesting for low-power uses, one of MRAM's primary disadvantages. Additionally, as the device is scaled down in size, there comes a time when the induced field overlaps adjacent cells over a small area, leading to potential false writes. This problem, the half-select (or write disturb) problem, appears to set a fairly large minimal size for this type of cell. One experimental solution to this problem was to use circular domains written and read using the giant magnetoresistive effect, but it appears that this line of research is no longer active.

A newer technique, spin-transfer torque (STT) or spin-transfer switching, uses spin-aligned ("polarized") electrons to directly torque the domains. Specifically, if the electrons flowing into a layer have to change their spin, this will develop a torque that will be transferred to the nearby layer. This lowers the amount of current needed to write the cells, making it about the same as the read process.^{[citation needed]} There are concerns that the "classic" type of MRAM cell will have difficulty at high densities because of the amount of current needed during writes, a problem that STT avoids. For this reason, the STT proponents expect the technique to be used for devices of 65 nm and smaller.^[5] The downside is the need to maintain the spin coherence. Overall, the STT requires much less write current than conventional or toggle MRAM. Research in this field indicates that STT current can be reduced up to 50 times by using a new composite structure.^[6] However, higher-speed operation still requires higher current.^[7]

Other potential arrangements include "vertical transport MRAM" (VMRAM), which uses current through a vertical column to change magnetic orientation, a geometric arrangement that reduces the write disturb problem and so can be used at higher density.^[8]

A review article^[9] provides the details of materials and challenges associated with MRAM in the perpendicular geometry. The authors describe a new term called "Pentalemma", which represents a conflict in five different requirements such as write current, stability of the bits, readability, read/write speed and the process integration with CMOS. The selection of materials and the design of MRAM to fulfill those requirements are discussed.

Comparison with other systems

Density

The main determinant of a memory system's cost is the density of the components used to make it up. Smaller components, and fewer of them, mean that more "cells" can be packed onto a single chip, which in turn means more can be produced at once from a single silicon wafer. This improves yield, which is directly related to cost.

DRAM uses a small capacitor as a memory element, wires to carry current to and from it, and a transistor to control it – referred to as a "1T1C" cell. This makes DRAM the highest-density RAM currently available, and thus the least expensive, which is why it is used for the majority of RAM found in computers.

MRAM is physically similar to DRAM in makeup, and often does require a transistor for the write operation (though not strictly necessary). The scaling of transistors to higher density necessarily leads to lower available current, which could limit MRAM performance at advanced nodes.

Power consumption

Since the capacitors used in DRAM lose their charge over time, memory assemblies that use DRAM must refresh all the cells in their chips several times a second, reading each one and re-writing its contents. As DRAM cells decrease in size it is necessary to refresh the cells more often, resulting in greater power consumption.

In contrast, MRAM never requires a refresh. This means that not only does it retain its memory with the power turned off but also there is no constant power-draw. While the read process in theory requires more power than the same process in a DRAM, in practice the difference appears to be very close to zero. However, the write process requires more power to overcome the existing field stored in the junction, varying from three to eight times the power required during reading.^[10]^[11] Although the exact amount of power savings depends on the nature of the work — more frequent writing will require more power – in general MRAM proponents expect much lower power consumption (up to 99% less) compared to DRAM. STT-based MRAMs eliminate the difference between reading and writing, further reducing power requirements.

It is also worth comparing MRAM with another common memory system — flash RAM. Like MRAM, flash does not lose its memory when power is removed, which makes it very common in applications requiring persistent storage. When used for reading, flash and MRAM are very similar in power requirements. However, flash is re-written using a large pulse of voltage (about 10 V) that is stored up over time in a charge pump, which is both power-hungry and time-consuming. In addition, the current pulse physically degrades the flash cells, which means flash can only be written to some finite number of times before it must be replaced.

In contrast, MRAM requires only slightly more power to write than read, and no change in the voltage, eliminating the need for a charge pump. This leads to much faster operation, lower power consumption, and an indefinitely long lifetime.

Data retention

MRAM is often touted as being a non-volatile memory. However, the current mainstream high-capacity MRAM, spin-transfer torque memory, provides improved retention at the cost of higher power consumption, i.e., higher write current. In particular, the critical (minimum) write current is directly proportional to the thermal stability factor Δ.^[12] The retention is in turn proportional to exp(Δ). The retention, therefore, degrades exponentially with reduced write current.

Speed

Dynamic random-access memory (DRAM) performance is limited by the rate at which the charge stored in the cells can be drained (for reading) or stored (for writing). MRAM operation is based on measuring voltages rather than charges or currents, so there is less "settling time" needed. IBM researchers have demonstrated MRAM devices with access times on the order of 2 ns, somewhat better than even the most advanced DRAMs built on much newer processes.^[13] A team at the German Physikalisch-Technische Bundesanstalt have demonstrated MRAM devices with 1 ns settling times, better than the currently accepted theoretical limits for DRAM, although the demonstration was a single cell.^[14] The differences compared to flash are far more significant, with write speeds as much as thousands of times faster. However, these speed comparisons are not for like-for-like current. High-density memory requires small transistors with reduced current, especially when built for low standby leakage. Under such conditions, write times shorter than 30 ns may not be reached so easily. In particular, to meet solder reflow stability of 260 °C over 90 seconds, 250 ns pulses have been required.^[15] This is related to the elevated thermal stability requirement driving up the write bit error rate. In order to avoid breakdown from higher current, longer pulses are needed.

For the perpendicular STT MRAM, the switching time is largely determined by the thermal stability Δ as well as the write current.^[16] A larger Δ (better for data retention) would require a larger write current or a longer pulse. A combination of high speed and adequate retention is only possible with a sufficiently high write current.

The only current memory technology that easily competes with MRAM in terms of performance at comparable density is static random-access memory (SRAM). SRAM consists of a series of transistors arranged in a flip-flop, which will hold one of two states as long as power is applied. Since the transistors have a very low power requirement, their switching time is very low. However, since an SRAM cell consists of several transistors, typically four or six, its density is much lower than DRAM. This makes it expensive, which is why it is used only for small amounts of high-performance memory, notably the CPU cache in almost all modern central processing unit designs.

Although MRAM is not quite as fast as SRAM, it is close enough to be interesting even in this role. Given its much higher density, a CPU designer may be inclined to use MRAM to offer a much larger but somewhat slower cache, rather than a smaller but faster one. It remains to be seen how this trade-off will play out in the future.

Endurance

The endurance of MRAM is affected by write current, just like retention and speed, as well as read current. When the write current is sufficiently large for speed and retention, the probability of MTJ breakdown needs to be considered.^[17] If the read current/write current ratio is not small enough, read disturb becomes more likely, i.e., a read error occurs during one of the many switching cycles. The read disturb error rate is given by

1-\exp \left(-{\frac {t_{read}}{\tau \exp(\Delta (1-I_{read}/I_{crit})}}\right)

,

where τ is the relaxation time (1 ns) and I_crit is the critical write current.^[18] Higher endurance requires a sufficiently low $I_{read}/I_{crit}$ . However, a lower I_read also reduces read speed.^[19]

Endurance is mainly limited by the possible breakdown of the thin MgO layer.^[20]^[21]

Overall

MRAM has similar performance to SRAM, enabled by the use of sufficient write current. However, this dependence on write current also makes it a challenge to compete with the higher density comparable to mainstream DRAM and Flash. Nevertheless, some opportunities for MRAM exist where density need not be maximized. From a fundamental physics point of view, the spin-transfer torque approach to MRAM is bound to a "rectangle of death" formed by retention, endurance, speed, and power requirements, as covered above.

Design parameter level	Retention	Endurance	Speed	Power
High write current	+	− (breakdown)	+	−
Low write current	−	− (read disturb)	−	+
High Δ	+	− (breakdown)	−	− (higher current)
Low Δ	−	− (read disturb)	+	+ (lower current)

While the power-speed tradeoff is universal for electronic devices, the endurance-retention tradeoff at high current and the degradation of both at low Δ is problematic. Endurance is largely limited to 10⁸ cycles.^[22]

Alternatives to MRAM

Flash and EEPROM's limited write-cycles are a serious problem for any real RAM-like role. In addition, the high power needed to write the cells is a problem in low-power nodes, where non-volatile RAM is often used. The power also needs time to be "built up" in a device known as a charge pump, which makes writing dramatically slower than reading, often as low as 1/1000 as fast. While MRAM was certainly designed to address some of these issues, a number of other new memory devices are in production or have been proposed to address these shortcomings.

To date, the only similar system to enter widespread production is ferroelectric RAM, or F-RAM (sometimes referred to as FeRAM).

Also seeing renewed interest are silicon-oxide-nitride-oxide-silicon (SONOS) memory and ReRAM. 3D XPoint has also been in development, but is known to have a higher power budget than DRAM.^[23]

History

1955 — Magnetic-core memory had the same reading writing principle as MRAM
1984 — Arthur V. Pohm and James M. Daughton, while working for Honeywell, developed the first magnetoresistance memory devices.^[24]^[25]
1988 — European scientists (Albert Fert and Peter Grünberg) discovered the "giant magnetoresistive effect" in thin-film structures.^[26]
1989 — Pohm and Daughton left Honeywell to form Nonvolatile Electronics, Inc. (later renamed to NVE Corp.) sublicensing the MRAM technology they have created.^[24]
1995 — Motorola (later to become Freescale Semiconductor, and subsequently NXP Semiconductors) initiates work on MRAM development
1996 — Spin torque transfer is proposed^[27]^[28]
1997 — Sony published the first Japan Patent Application for S.P.I.N.O.R. (Spin Polarized Injection Non-Volatile Orthogonal Read/Write RAM), a forerunner of STT RAM.^[29]
1998 — Motorola develops 256 Kb MRAM test chip.^[30]
2000 — IBM and Infineon established a joint MRAM development program.
2000 — Spintec laboratory's first Spin-Torque Transfer patent.
2002
- NVE announces technology exchange with Cypress Semiconductor.
- Toggle patent granted to Motorola^[31]
2003 — A 128 kbit MRAM chip was introduced, manufactured with a 180 nm lithographic process
2004
- June — Infineon unveiled a 16-Mbit prototype, manufactured with a 180 nm lithographic process
- September — MRAM becomes a standard product offering at Freescale.
- October — Taiwan developers of MRAM tape out 1 Mbit parts at TSMC.
- October — Micron drops MRAM, mulls other memories.
- December — TSMC, NEC and Toshiba describe novel MRAM cells.
- December — Renesas Technology promotes a high performance, high-reliability MRAM technology.
- Spintech laboratory's first observation of Thermal Assisted Switching (TAS) as MRAM approach.
- Crocus Technology is founded; the company is a developer of second-generation MRAM
2005
- January — Cypress Semiconductor samples MRAM, using NVE IP.
- March — Cypress to Sell MRAM Subsidiary.
- June — Honeywell posts data sheet for 1-Mbit rad-hard MRAM using a 150 nm lithographic process.
- August — MRAM record: memory cell runs at 2 GHz.
- November — Renesas Technology and Grandis collaborate on development of 65 nm MRAM employing spin torque transfer (STT).
- November — NVE receives an SBIR grant to research cryptographic tamper-responsive memory.^[32]
- December — Sony announced Spin-RAM, the first lab-produced spin-torque-transfer MRAM, which utilizes a spin-polarized current through the tunneling magnetoresistance layer to write data. This method consumes less power and is more scalable than conventional MRAM. With further advances in materials, this process should allow for densities higher than those possible in DRAM.
- December — Freescale Semiconductor Inc. demonstrates an MRAM that uses magnesium oxide, rather than an aluminum oxide, allowing for a thinner insulating tunnel barrier and improved bit resistance during the write cycle, thereby reducing the required write current.
- Spintec laboratory gives Crocus Technology exclusive license on its patents.
2006
- February — Toshiba and NEC announced a 16 Mbit MRAM chip with a new "power-forking" design. It achieves a transfer rate of 200 Mbit/s, with a 34 ns cycle time, the best performance of any MRAM chip. It also boasts the smallest physical size in its class — 78.5 square millimeters — and the low voltage requirement of 1.8 volts.^[33]
- July — On July 10, Austin Texas — Freescale Semiconductor begins marketing a 4-Mbit MRAM chip, which sells for approximately $25.00 per chip.^[34]^[35]
2007
- R&D moving to spin transfer torque RAM (SPRAM)
- February — Tohoku University and Hitachi developed a prototype 2-Mbit non-volatile RAM chip employing spin-transfer torque switching.^[36]
- August — "IBM, TDK Partner In Magnetic Memory Research on Spin Transfer Torque Switching" IBM and TDK to lower the cost and boost performance of MRAM to hopefully release a product to market.^[37]
- November — Toshiba applied and proved the spin-transfer torque switching with perpendicular magnetic anisotropy MTJ device.^[38]
- November — NEC develops world's fastest SRAM-compatible MRAM with operation speed of 250 MHz.^[39]
2008
- Japanese satellite, SpriteSat, to use Freescale MRAM to replace SRAM and FLASH components^[40]
- June — Samsung and Hynix become partner on STT-MRAM^[41]
- June — Freescale spins off MRAM operations as new company Everspin^[42]^[43]
- August — Scientists in Germany have developed next-generation MRAM that is said to operate as fast as fundamental performance limits allow, with write cycles under 1 nanosecond.
- November — Everspin announces BGA packages, product family from 256 Kb to 4 Mb^[44]
2009
- June — Hitachi and Tohoku University demonstrated a 32-Mbit spin-transfer torque RAM (SPRAM).^[45]
- June — Crocus Technology and Tower Semiconductor announce deal to port Crocus' MRAM process technology to Tower's manufacturing environment^[46]
- November — Everspin releases SPI MRAM product family^[47] and ships first embedded MRAM samples
2010
- April — Everspin releases 16 Mb density^[48]^[49]
- June — Hitachi and Tohoku Univ announce Multi-level SPRAM^[50]
2011
- March — PTB, Germany, announces below 500 ps (2 Gbit/s) write cycle^[51]
2012
- November — Chandler, Arizona, USA, Everspin debuts 64 Mb ST-MRAM on a 90 nm process.^[52]^[53]
- December — A team from University of California, Los Angeles presents voltage-controlled MRAM at IEEE International Electron Devices Meeting.^[54]
2013
- November — Buffalo Technology and Everspin announce a new industrial SATA III SSD that incorporates Everspin's Spin-Torque MRAM (ST-MRAM) as cache memory.^[55]
2014
- January — Researchers announce the ability to control the magnetic properties of core/shell antiferromagnetic nanoparticles using only temperature and magnetic field changes.^[56]
- October — Everspin partners with GlobalFoundries to produce ST-MRAM on 300 mm wafers.^[57]
2016
- April — Samsung's semiconductor chief Kim Ki-nam says Samsung is developing an MRAM technology that "will be ready soon".^[58]
- July — IBM and Samsung report an MRAM device capable of scaling down to 11 nm with a switching current of 7.5 microamps at 10 ns.^[59]
- August — Everspin announced it was shipping samples of the industry's first 256 Mb ST-MRAM to customers.^[60]
- October — Avalanche Technology partners with Sony Semiconductor Manufacturing to manufacture STT-MRAM on 300 mm wafers, based on "a variety of manufacturing nodes".^[61]
- December — Inston and Toshiba independently present results on voltage-controlled MRAM at International Electron Devices Meeting.^[62]
2019
- January — Everspin starts shipping samples of 28 nm 1 Gb STT-MRAM chips.^[63]
- March — Samsung commence commercial production of its first embedded STT-MRAM based on a 28 nm process.^[64]
- May — Avalanche partners with United Microelectronics Corporation to jointly develop and produce embedded MRAM based on the latter's 28 nm CMOS manufacturing process.^[65]
2020
- December — IBM announces a 14 nm MRAM node.^[66]
2021
- May — TSMC revealed a roadmap for developing the eMRAM technology at 12/14 nm node as an offering to replace eFLASH.^[67]
- November — Taiwan Semiconductor Research Institute announced the development of a SOT-MRAM device.^[68]

Applications

Possible practical application of the MRAM includes virtually every device that has some type of memory inside such as aerospace and military systems, digital cameras, notebooks, smart cards, mobile telephones, cellular base stations, personal computers, battery-backed SRAM replacement, datalogging specialty memories (black box solutions), media players, and book readers etc.

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^ "Magnetic nanoparticles breakthrough could help shrink digital storage". Gizmag.com. 8 January 2014. Retrieved 2014-01-09.
^ "Everspin and GLOBALFOUNDRIES Partner to Supply Fully Processed 300mm CMOS Wafers with Everspin's ST-MRAM Technology". GLOBALFOUNDRIES (Press release). 2014-10-27. Archived from the original on 2020-09-24. Retrieved 2020-08-22.
^ Kim, Yoo-chul (20 April 2016). "Cheil Worldwide acquires Founded". Koreatimes.co.kr. Korea Times. Retrieved 27 June 2016. 'Yes, Samsung will commercialize MRAMs and ReRAMs according to our own schedule. We are on our way and will be ready soon,' Kim told reporters.
^ "Researchers celebrate 20th anniversary of IBM's invention of Spin Torque MRAM by demonstrating scalability for the next decade — IBM Blog Research". IBM Blog Research. 2016-07-07. Retrieved 2016-07-11.
^ Strong, Scott (August 5, 1026). "Everspin Announces Sampling of Industry's First 256Mb Perpendicular Spin Torque MRAM to Customers". The SSD Review.
^ "Sony revealed as MRAM foundry for Avalanche". eeNews Analog. 2016-10-31. Retrieved 2020-08-22.
^ "IEDM: Magnetic RAM debuts as 28nm embedded NVM | EETE Analog". EE Times. Archived from the original on 2017-03-03. Retrieved 2017-03-03.
^ "Everspin starts to ship customer samples of its 28nm 1Gb STT-MRAM chips | MRAM-Info". www.mram-info.com. Retrieved 2019-12-03.
^ "Samsung Says It's Shipping 28-nm Embedded MRAM". EE Times.
^ "UMC and Avalanche Technology Partner for MRAM Development and 28nm Production". Avalanche Technology. 2018-08-06. Retrieved 2020-08-22.
^ "IBM to reveal the world's first 14nm STT-MRAM node". 2020-12-15. Retrieved 2020-12-17.
^ "TSMC shows its eMRAM technology roadmap | MRAM-Info". www.mram-info.com. Retrieved 2021-05-16.
^ Chia-nan, Lin. "Local researchers make advanced MRAM device". www.taipeitimes.com. Taipei Times. Retrieved 9 November 2021.

External links

Sbiaa, R.; Meng, H.; Piramanayagam, S. N. (2011). "Materials with perpendicular magnetic anisotropy for magnetic random access memory". Physica Status Solidi RRL. 5 (12): 413. Bibcode:2011PSSRR...5..413S. doi:10.1002/pssr.201105420. S2CID 98626346.
Butner, Richard (2001). "MRAM". IBM research.
Akerman, J. (2005). "APPLIED PHYSICS: Toward a Universal Memory". Science. 308 (5721): 508–510. doi:10.1126/science.1110549. PMID 15845842. S2CID 60577959.
Allwood, D. A.; Xiong, G.; Faulkner, C. C.; Atkinson, D.; Petit, D.; Cowburn, R. P. (2005). "Magnetic Domain-Wall Logic". Science. 309 (5741): 1688–92. Bibcode:2005Sci...309.1688A. doi:10.1126/science.1108813. PMID 16151002. S2CID 23385116.
Wired News article from February, 2006 Archived 2008-08-21 at the Wayback Machine
NEC Press Release from February, 2006
BBC news article from July, 2006
Freescale MRAM – an in-depth examination from August 2006
MRAM – The Birth of the Super Memory – An article and an interview with Freescale about their MRAM technology
Spin torque applet – An applet illustrating the principles underlying spin-torque transfer MRAM
New Speed Record for Magnetic Memories – The Future of Things article
Bhatti, Sabpreet; Sbiaa, Rachid; Hirohata, Atsufumi; Ohno, Hideo; Fukami, Shunsuke; Piramanayagam, S.N. (2017). "Spintronics based random access memory: a review". Materials Today. 20 (9): 530–548. doi:10.1016/j.mattod.2017.07.007. hdl:10356/146755.

[1] United States 4731757A, "Magnetoresistive memory including thin film storage cells having tapered ends"

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[3] Fuxi, Gan; Yang, Wang (February 9, 2015). Data Storage at the Nanoscale: Advances and Applications. CRC Press. ISBN 9789814613200 – via Google Books.

[4] Engel, B. N.; Akerman, J.; Butcher, B.; Dave, R. W.; Deherrera, M.; Durlam, M.; Grynkewich, G.; Janesky, J.; Pietambaram, S. V.; Rizzo, N. D.; Slaughter, J. M.; Smith, K.; Sun, J. J.; Tehrani, S. (2005). "A 4-Mb toggle MRAM based on a novel bit and switching method". IEEE Transactions on Magnetics. 41 (1): 132. Bibcode:2005ITM....41..132E. doi:10.1109/TMAG.2004.840847. S2CID 38616311.

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[20] "Breakdown-Limited Write Time Windows for STT-MRAM". www.linkedin.com.

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[32] "NSF Award Search: Award#0539675 - SBIR Phase I: Zero-Remanence Tamper-Responsive Cryptokey Memory". www.nsf.gov.

[NEC_PR_2006-02-07-33] "Toshiba and NEC Develop World's Fastest, Highest Density MRAM" (Press release). NEC Corporation. 2006-02-07. Retrieved 2006-07-10.

[Freescale_PR_2006-07-10-34] "Freescale Leads Industry in Commercializing MRAM Technology" (Press release). Freescale Semiconductor. 2006-07-10. Archived from the original on 2007-10-13. Retrieved 2006-07-10.

[35] Lammers, David (October 7, 2006). "MRAM debut cues memory transition". EE Times.

[Hitachi_PR_2007-02-13-36] "Prototype 2 Mbit Non-Volatile RAM Chip Employing Spin-Transfer Torque Writing Method" (Press release). Hitachi Ltd. 2007-02-13. Retrieved 2007-02-13.

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[Toshiba_PR_2007-11-6-38] "Toshiba develops new MRAM device that opens the way to giga-bits capacity" (Press release). Toshiba Corporation. 2007-11-06. Retrieved 2007-11-06.

[NEC_PR_2007-11-30-39] "NEC Develops World's Fastest SRAM-Compatible MRAM With Operation Speed of 250MHz" (Press release). NEC Corporation. 2007-11-30. Retrieved 2007-12-01.

[sciam.com-40] Greenemeier, Larry. "Japanese Satellite First to Use Magnetic Memory". Scientific American.

[41] "Samsung, Hynix partner on STT-MRAM". Archived from the original on 2008-11-12. Retrieved 2008-10-01.

[42] "Freescale launches independent company to accelerate MRAM business" (PDF) (Press release). 29 June 2008. Archived from the original (PDF) on 2012-07-26.

[43] Merced, Michael J. (June 9, 2008). "Chip Maker to Announce It Will Spin Off Memory Unit". The New York Times.

[44] LaPedus, Mark (November 13, 2008). "Freescale's MRAM spin-off rolls new devices". EE Times.

[45] Takemura, R.; Kawahara, T.; Miura, K.; Yamamoto, H.; Hayakawa, J.; Matsuzaki, N.; Ono, K.; Yamanouchi, M.; Ito, K.; Takahashi, H.; Ikeda, S. (2009). "32-mb 2t1r spram with localized bi-directional write driver and '1'/'0'dual-array equalized reference cell". 2009 Symposium on VLSI Circuits. IEEE. pp. 84–85. ISBN 978-1-4244-3307-0.

[46] "News | Crocus Technology". Archived from the original on April 22, 2010.

[47] Johnson, R Colin (November 16, 2009). "MRAM chips go serial in smart meters". EE Times.

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[57] "Everspin and GLOBALFOUNDRIES Partner to Supply Fully Processed 300mm CMOS Wafers with Everspin's ST-MRAM Technology". GLOBALFOUNDRIES (Press release). 2014-10-27. Archived from the original on 2020-09-24. Retrieved 2020-08-22.

[58] Kim, Yoo-chul (20 April 2016). "Cheil Worldwide acquires Founded". Koreatimes.co.kr. Korea Times. Retrieved 27 June 2016. 'Yes, Samsung will commercialize MRAMs and ReRAMs according to our own schedule. We are on our way and will be ready soon,' Kim told reporters.

[59] "Researchers celebrate 20th anniversary of IBM's invention of Spin Torque MRAM by demonstrating scalability for the next decade — IBM Blog Research". IBM Blog Research. 2016-07-07. Retrieved 2016-07-11.

[60] Strong, Scott (August 5, 1026). "Everspin Announces Sampling of Industry's First 256Mb Perpendicular Spin Torque MRAM to Customers". The SSD Review.

[61] "Sony revealed as MRAM foundry for Avalanche". eeNews Analog. 2016-10-31. Retrieved 2020-08-22.

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[63] "Everspin starts to ship customer samples of its 28nm 1Gb STT-MRAM chips | MRAM-Info". www.mram-info.com. Retrieved 2019-12-03.

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[66] "IBM to reveal the world's first 14nm STT-MRAM node". 2020-12-15. Retrieved 2020-12-17.

[67] "TSMC shows its eMRAM technology roadmap | MRAM-Info". www.mram-info.com. Retrieved 2021-05-16.

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@@ Line 1: / Line 1: @@
+{{Short description|Type of computer memory}}
 {{Redirect|MRAM|the Mongolian government agency|Mineral Resource Authority of Mongolia}}
-{{Use American English|date=January 2019}}{{Short description|Implementation of random access memory
+{{Use American English|date=January 2019}}{{Memory types}}
+'''Magnetoresistive random-access memory''' ('''MRAM''') is a type of [[non-volatile random-access memory]] which stores data in [[magnetic domain]]s.<ref>{{cite patent |country=United States |number=4731757A |url=https://patents.google.com/patent/US4731757A/en|title=Magnetoresistive memory including thin film storage cells having tapered ends}}</ref> Developed in the mid-1980s, proponents have argued that magnetoresistive RAM will eventually surpass competing technologies to become a dominant or even [[universal memory]].<ref>{{Cite journal | last1 = Akerman | first1 = J. | title = APPLIED PHYSICS: Toward a Universal Memory | doi = 10.1126/science.1110549 | journal = Science | volume = 308 | issue = 5721 | pages = 508–510 | year = 2005 | pmid = 15845842| s2cid = 60577959 }}</ref> Currently, memory technologies in use such as [[Flash memory|flash RAM]] and [[Dynamic random-access memory|DRAM]] have practical advantages that have so far kept MRAM in a niche role in the market.
-}}
-{{Memory types}}
-{{short description|Novel type of computer memory}}
-'''Magnetoresistive random-access memory''' ('''MRAM''') is a type of [[non-volatile random-access memory]] which stores data in [[magnetic domain]]s.<ref>{{cite patent |country=United States |number=4731757A |url=https://patents.google.com/patent/US4731757A/en|title=Magnetoresistive memory including thin film storage cells having tapered ends}}</ref> Developed in the mid-1980s, proponents have argued that magnetoresistive RAM will eventually surpass competing technologies to become a dominant or even [[universal memory]].<ref>{{Cite journal | last1 = Akerman | first1 = J. | title = APPLIED PHYSICS: Toward a Universal Memory | doi = 10.1126/science.1110549 | journal = Science | volume = 308 | issue = 5721 | pages = 508–510 | year = 2005 | pmid =  15845842| s2cid = 60577959 }}</ref> Currently, memory technologies in use such as [[Flash memory|flash RAM]] and [[Dynamic random-access memory|DRAM]] have practical advantages that have so far kept MRAM in a niche role in the market.
 ==Description==
 [[Image:MRAM-Cell-Simplified.svg|thumb|upright=1.5 |right |Simplified structure of an MRAM cell<ref>{{Cite book|url=https://books.google.com/books?id=Tlm3BgAAQBAJ&dq=for+tunnel+junctions+with+an+aluminum+oxide+tunneling+barrier,+the+maximum+difference+in+resistance&pg=PA284|title=Data Storage at the Nanoscale: Advances and Applications|first1=Gan|last1=Fuxi|first2=Wang|last2=Yang|date=February 9, 2015|publisher=CRC Press|isbn=9789814613200|via=Google Books}}</ref>]]
-Unlike conventional [[random-access memory|RAM]] chip technologies, data in MRAM is not stored as [[electric charge]] or current flows, but by [[magnetism|magnetic]] storage elements. The elements are formed from two [[Ferromagnetism|ferromagnetic]] plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. This configuration is known as a [[Tunnel magnetoresistance|magnetic tunnel junction]] and is the simplest structure for an MRAM [[bit]]. A memory device is built from a grid of such "cells".
+Unlike conventional [[random-access memory|RAM]] chip technologies, data in MRAM is not stored as [[electric charge]] or current flows, but by [[magnetism|magnetic]] storage elements. The elements are formed from two [[Ferromagnetism|ferromagnetic]] plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. This configuration is known as a [[Tunnel magnetoresistance|magnetic tunnel junction]] (MTJ) and is the simplest structure for an MRAM [[bit]]. A memory device is built from a grid of such "cells".
 The simplest method of reading is accomplished by measuring the [[Electrical resistance and conductance|electrical resistance]] of the cell. A particular cell is (typically) selected by powering an associated [[transistor]] that switches [[electric current|current]] from a supply line through the cell to ground. Because of [[tunnel magnetoresistance]], the electrical resistance of the cell changes with the relative orientation of the magnetization in the two plates. By measuring the resulting current, the resistance inside any particular cell can be determined, and from this the magnetization polarity of the writable plate. Typically if the two plates have the same magnetization alignment (low resistance state) this is considered to mean "1", while if the alignment is antiparallel the resistance will be higher (high resistance state) and this means "0".
@@ Line 14: / Line 12: @@
 Data is written to the cells using a variety of means. In the simplest "classic" design, each cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an [[Electromagnetic induction|induced magnetic field]] is created at the junction, which the writable plate picks up. This pattern of operation is similar to [[magnetic-core memory]], a system commonly used in the 1960s.
-However, due to process and material variations, an array of memory cells has a distribution of switching fields with a deviation σ. Therefore, to program all the bits in a large array with the same current, the applied field needs to be larger than the mean "selected" switching field by greater than 6σ. In addition,the applied field must be kept below a maximum value. Thus, this "conventional" MRAM must keep these two distributions well-separated. As a result, there is a narrrow operating window for programming fields; and only inside this window, can all the bits be programmed without errors or disturbs. In 2005, a "Savtchenko switching" relying on the unique behavior of a synthetic antiferromagnet (SAF) free layer is applied to solve this problem. <ref>{{Cite journal |title=A 4-Mb toggle MRAM based on a novel bit and switching method |journal=2005 IEEE International Magnetics Conference (INTERMAG)|bibcode=2005ITM....41..132E |last1=Engel |first1=B. N. |last2=Akerman |first2=J. |last3=Butcher |first3=B. |last4=Dave |first4=R. W. |last5=Deherrera |first5=M. |last6=Durlam |first6=M. |last7=Grynkewich |first7=G. |last8=Janesky |first8=J. |last9=Pietambaram |first9=S. V. |last10=Rizzo |first10=N. D. |last11=Slaughter |first11=J. M. |last12=Smith |first12=K. |last13=Sun |first13=J. J. |last14=Tehrani |first14=S. |year=2005 |volume=41 |issue=1 |page=132 |doi=10.1109/TMAG.2004.840847 |s2cid=38616311 }}</ref>The SAF layer is formed from two ferromagnetic layers separated by a nonmagnetic coupling spacer layer. For a synthetic antiferromagnet having some net anisotropy '''Hk''' in each layer, there exists a critical spin flop field '''Hsw''' at which the two antiparallel layer magnetizations will rotate (flop) to be orthogonal to the applied field '''H''' with each layer scissoring slightly in the direction of '''H'''. Therefore, if only a single line current is applied (half-selected bits), the 45° field angle cannot switch the state. Below the toggling transition, there are no disturbs all the way up to the highest fields.
+However, due to process and material variations, an array of memory cells has a distribution of switching fields with a deviation σ. Therefore, to program all the bits in a large array with the same current, the applied field needs to be larger than the mean "selected" switching field by greater than 6σ. In addition,the applied field must be kept below a maximum value. Thus, this "conventional" MRAM must keep these two distributions well-separated. As a result, there is a narrow operating window for programming fields; and only inside this window, can all the bits be programmed without errors or disturbs. In 2005, a "Savtchenko switching" relying on the unique behavior of a synthetic [[Antiferromagnetism|antiferromagnet]] (SAF) free layer is applied to solve this problem.<ref>{{Cite journal |title=A 4-Mb toggle MRAM based on a novel bit and switching method |bibcode=2005ITM....41..132E |last1=Engel |first1=B. N. |last2=Akerman |first2=J. |last3=Butcher |first3=B. |last4=Dave |first4=R. W. |last5=Deherrera |first5=M. |last6=Durlam |first6=M. |last7=Grynkewich |first7=G. |last8=Janesky |first8=J. |last9=Pietambaram |first9=S. V. |last10=Rizzo |first10=N. D. |last11=Slaughter |first11=J. M. |last12=Smith |first12=K. |last13=Sun |first13=J. J. |last14=Tehrani |first14=S. |journal=IEEE Transactions on Magnetics |year=2005 |volume=41 |issue=1 |page=132 |doi=10.1109/TMAG.2004.840847 |s2cid=38616311 }}</ref> The SAF layer is formed from two ferromagnetic layers separated by a nonmagnetic coupling spacer layer. For a synthetic antiferromagnet having some net anisotropy '''Hk''' in each layer, there exists a critical spin flop field '''Hsw''' at which the two antiparallel layer magnetizations will rotate (flop) to be orthogonal to the applied field '''H''' with each layer scissoring slightly in the direction of '''H'''. Therefore, if only a single line current is applied (half-selected bits), the 45° field angle cannot switch the state. Below the toggling transition, there are no disturbs all the way up to the highest fields.
 This approach still requires a fairly substantial current to generate the field, however, which makes it less interesting for low-power uses, one of MRAM's primary disadvantages. Additionally, as the device is scaled down in size, there comes a time when the induced field overlaps adjacent cells over a small area, leading to potential false writes. This problem, the half-select (or write disturb) problem, appears to set a fairly large minimal size for this type of cell. One experimental solution to this problem was to use circular domains written and read using the [[Giant magnetoresistance|giant magnetoresistive effect]], but it appears that this line of research is no longer active.
@@ Line 22: / Line 20: @@
 Other potential arrangements include "vertical transport MRAM" (VMRAM), which uses current through a vertical column to change magnetic orientation, a geometric arrangement that reduces the write disturb problem and so can be used at higher density.<ref>[http://www.nve-spintronics.com/mram-operation.php "How MRAM Works"].</ref>
-A review article<ref>{{Cite journal | last1 = Sbiaa | first1 = R. | last2 = Meng | first2 = H. | last3 = Piramanayagam | first3 = S. N. | doi = 10.1002/pssr.201105420 | title = Materials with perpendicular magnetic anisotropy for magnetic random access memory | journal = Physica Status Solidi RRL | volume = 5 | issue = 12 | pages = 413 | year = 2011 | bibcode = 2011PSSRR...5..413S | s2cid = 98626346 }}</ref> provides the details of materials and challenges associated with MRAM in the perpendicular geometry. The authors describe a new term called "Pentalemma", which represents a conflict in five different requirements such as write current, stability of the bits, readability, read/write speed and the process integration with CMOS. The selection of materials and the design of MRAM to fulfill those requirements are discussed.
+A review article<ref>{{Cite journal | last1 = Sbiaa | first1 = R. | last2 = Meng | first2 = H. | last3 = Piramanayagam | first3 = S. N. | doi = 10.1002/pssr.201105420 | title = Materials with perpendicular magnetic anisotropy for magnetic random access memory | journal = Physica Status Solidi RRL | volume = 5 | issue = 12 | pages = 413 | year = 2011 | bibcode = 2011PSSRR...5..413S | s2cid = 98626346 | doi-access = free }}</ref> provides the details of materials and challenges associated with MRAM in the perpendicular geometry. The authors describe a new term called "Pentalemma", which represents a conflict in five different requirements such as write current, stability of the bits, readability, read/write speed and the process integration with CMOS. The selection of materials and the design of MRAM to fulfill those requirements are discussed.
 == Comparison with other systems ==
@@ Line 47: / Line 45: @@
 [[Dynamic random-access memory]] (DRAM) performance is limited by the rate at which the charge stored in the cells can be drained (for reading) or stored (for writing). MRAM operation is based on measuring voltages rather than charges or currents, so there is less "settling time" needed. IBM researchers have demonstrated MRAM devices with access times on the order of 2&nbsp;ns, somewhat better than even the most advanced DRAMs built on much newer processes.<ref>[http://www.thic.org/pdf/Jul03/nist.skaka.030722.pdf "Past, Present and Future of MRAM"], NIST Magnetic Technology, 22 July 2003</ref> A team at the German [[Physikalisch-Technische Bundesanstalt]] have demonstrated MRAM devices with 1&nbsp;ns settling times, better than the currently accepted theoretical limits for DRAM, although the demonstration was a single cell.<ref>Kate McAlpine, [https://www.newscientist.com/channel/tech/dn14525-spin-flip-trick-points-to-fastest-ram-yet.html "Spin flip trick points to fastest RAM yet"], ''NewScientist'', 13 August 2008</ref> The differences compared to flash are far more significant, with write speeds as much as thousands of times faster. However, these speed comparisons are not for like-for-like current. High-density memory requires small transistors with reduced current, especially when built for low standby leakage. Under such conditions, write times shorter than 30&nbsp;ns may not be reached so easily. In particular, to meet solder reflow stability of 260&nbsp;°C over 90 seconds, 250&nbsp;ns pulses have been required.<ref>L. Thomas et al., S3S 2017</ref> This is related to the elevated thermal stability requirement driving up the write bit error rate. In order to avoid breakdown from higher current, longer pulses are needed.
-For the perpendicular STT MRAM, the switching time is largely determined by the thermal stability Δ as well as the write current.<ref>{{cite journal |last1=Khvalkovskiy |first1=A.V. |last2=Apalkov |first2=D. |last3=Watts |first3=S.|last4=Chepulskii |first4=R.|last5=Beach |first5=R S.|last6=Ong |first6=A.|last7=Tang |first7=X.|last8=Driskill-Smith |first8=A.|last9=Butler |first9=W.H.|last10=Visscher |first10=P.B.|last11=Lottis |first11=D.|last12=Chen |first12=E.|last13=Nikitin |first13=V.|last14=Krounbi |first14=M.|title=Basic principles of STT-MRAM cell operation in memory arrays |journal=Journal of Physics D: Applied Physics |volume=46 |issue=7 |pages=074001 |year=2013 |doi=10.1088/0022-3727/46/7/074001 |bibcode=2013JPhD...46g4001K }}</ref> A larger Δ (better for data retention) would require a larger write current or a longer pulse. A combination of high speed and adequate retention is only possible with a sufficiently high write current.
+For the perpendicular STT MRAM, the switching time is largely determined by the thermal stability Δ as well as the write current.<ref>{{cite journal |last1=Khvalkovskiy |first1=A.V. |last2=Apalkov |first2=D. |last3=Watts |first3=S.|last4=Chepulskii |first4=R.|last5=Beach |first5=R S.|last6=Ong |first6=A.|last7=Tang |first7=X.|last8=Driskill-Smith |first8=A.|last9=Butler |first9=W.H.|last10=Visscher |first10=P.B.|last11=Lottis |first11=D.|last12=Chen |first12=E.|last13=Nikitin |first13=V.|last14=Krounbi |first14=M.|title=Basic principles of STT-MRAM cell operation in memory arrays |journal=Journal of Physics D: Applied Physics |volume=46 |issue=7 |pages=074001 |year=2013 |doi=10.1088/0022-3727/46/7/074001 |bibcode=2013JPhD...46g4001K |s2cid=110519121 }}</ref> A larger Δ (better for data retention) would require a larger write current or a longer pulse. A combination of high speed and adequate retention is only possible with a sufficiently high write current.
 The only current memory technology that easily competes with MRAM in terms of performance at comparable density is [[static random-access memory]] (SRAM). SRAM consists of a series of transistors arranged in a [[flip-flop (electronics)|flip-flop]], which will hold one of two states as long as power is applied. Since the transistors have a very low power requirement, their switching time is very low. However, since an SRAM cell consists of several transistors, typically four or six, its density is much lower than DRAM. This makes it expensive, which is why it is used only for small amounts of high-performance memory, notably the [[CPU cache]] in almost all modern [[central processing unit]] designs.
@@ Line 58: / Line 56: @@
 where τ is the relaxation time (1 ns) and I<sub>crit</sub> is the critical write current.<ref>{{cite book |first1=R. |last1=Bishnoi |first2=M. |last2=Ebrahimi |first3=F. |last3=Oboril |first4=M.B. |last4=Tahoori |chapter=Read disturb fault detection in STT-MRAM |title=2014 International Test Conference |year=2014 |isbn= 978-1-4799-4722-5|pages=1–7 |doi=10.1109/TEST.2014.7035342|s2cid=7957290 }}</ref> Higher endurance requires a sufficiently low <math>I_{read}/I_{crit}</math>. However, a lower I<sub>read</sub> also reduces read speed.<ref>{{cite journal |first1=M. |last1=Chang |first2=S. |last2=Shen |first3=C. |last3=Liu |first4=C. |last4=Wu |first5=Y. |last5=Lin |first6=Y. |last6=King |first7=C. |last7=Lin |first8=H. |last8=Liao |first9=Y. |last9=Chih |first10=H. |last10=Yamauchi |title=An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory |journal=IEEE Journal of Solid-State Circuits |volume=48 |issue=3 |pages=864–877 |date=March 2013 |doi=10.1109/JSSC.2012.2235013 |bibcode=2013IJSSC..48..864C |s2cid=23020634 |url=}}</ref>
+Endurance is mainly limited by the possible breakdown of the thin MgO layer.<ref>{{Cite web|url=https://www.linkedin.com/pulse/breakdown-limited-write-time-windows-stt-mram-frederick-chen|title=Breakdown-Limited Write Time Windows for STT-MRAM|website=www.linkedin.com}}</ref><ref>J. H. Lim et al., "Investigating the Statistical-Physical Nature of MgO Dielectric Breakdown in STT-MRAM at Different Operating Conditions," IEDM 2018.</ref>
 ===Overall===
@@ Line 95: / Line 95: @@
 |}
-While the power-speed tradeoff is universal for electronic devices, the endurance-retention tradeoff at high current and the degradation of both at low Δ is problematic. Endurance is largely limited to 10<sup>8</sup> cycles.<ref>[http://www.electronicdesign.com/industrial-automation/unleashing-mram-persistent-memory].</ref>
+While the power-speed tradeoff is universal for electronic devices, the endurance-retention tradeoff at high current and the degradation of both at low Δ is problematic. Endurance is largely limited to 10<sup>8</sup> cycles.<ref>{{cite web | url=http://www.electronicdesign.com/industrial-automation/unleashing-mram-persistent-memory | title=StackPath | date=21 March 2018 }}</ref>
 ===Alternatives to MRAM===
-Flash and EEPROM's limited write-cycles are a serious problem for any real RAM-like role. In addition, the high power needed to write the cells is a problem in low-power nodes, where non-volatile RAM is often used. The power also needs time to be "built up" in a device known as a [[charge pump]], which makes writing dramatically slower than reading, often as low as 1/1000 as fast.  While MRAM was certainly designed to address some of these issues, a number of other new memory devices are in production or have been proposed to address these shortcomings.
+Flash and EEPROM's limited write-cycles are a serious problem for any real RAM-like role. In addition, the high power needed to write the cells is a problem in low-power nodes, where non-volatile RAM is often used. The power also needs time to be "built up" in a device known as a [[charge pump]], which makes writing dramatically slower than reading, often as low as 1/1000 as fast. While MRAM was certainly designed to address some of these issues, a number of other new memory devices are in production or have been proposed to address these shortcomings.
 To date, the only similar system to enter widespread production is [[ferroelectric RAM]], or F-RAM (sometimes referred to as FeRAM).
@@ Line 106: / Line 106: @@
 ==History==
 {{Prose|section|date=March 2019}}
-[[File:200mm 1 Mb MRAM - D60 Symposium - Defense Advanced Research Projects Agency - DSC05568.jpg|thumb|right|First 200mm 1 Mb MRAM wafer, fabricated by [[Motorola]], 2001]]
+[[File:200mm 1&nbsp;Mb MRAM - D60 Symposium - Defense Advanced Research Projects Agency - DSC05568.jpg|thumb|right|First 200mm 1&nbsp;Mb MRAM wafer, fabricated by [[Motorola]], 2001]]
 * 1955&nbsp;— [[Magnetic-core memory]] had the same reading writing principle as MRAM
 * 1984&nbsp;— Arthur V. Pohm and James M. Daughton, while working for [[Honeywell]], developed the first magnetoresistance memory devices.<ref name=Daughton>{{Cite web|url=https://www.nve.com/Downloads/mram.pdf|title=James Daughton, Magnetoresistive Random Access Memory (MRAM)}}</ref><ref name=everspin>{{Cite web|url=https://www.everspin.com/sites/default/files/pressdocs/JPL_MRAM_Study.pdf|title=NASA JPL, MRAM Technology Status}}</ref>
@@ Line 113: / Line 113: @@
 * 1995&nbsp;— [[Motorola]] (later to become [[Freescale Semiconductor]], and subsequently [[NXP Semiconductors]]) initiates work on MRAM development
 * 1996&nbsp;— [[Spin-transfer torque|Spin torque transfer]] is proposed<ref>{{Cite journal|last=L Berger|date=October 1996|title=Emission of spin waves by a magnetic multilayer traversed by a current|journal=Physical Review B|volume=54|pages=9353–8|doi=10.1103/physrevb.54.9353|pmid=9984672|issue=13|bibcode=1996PhRvB..54.9353B}}</ref><ref>{{Cite journal|date=October 1996|title=Current-driven excitation of magnetic multilayers|journal=Journal of Magnetism and Magnetic Materials|volume=159|issue=1–2|pages=L1–L7|doi=10.1016/0304-8853(96)00062-5| last1 = Slonczewski | first1 = J.C.|bibcode=1996JMMM..159L...1S}}</ref>
+* 1997&nbsp;— Sony published the first Japan Patent Application for S.P.I.N.O.R. (Spin Polarized Injection Non-Volatile Orthogonal Read/Write RAM), a forerunner of STT RAM.<ref>{{cite web |last1=Maiken |first1=Eric |title=Nonvolatile random access memory device |url=https://patents.google.com/patent/JP4066477B2/en?inventor=%E3%83%9E%E3%82%A4%E3%82%B1%E3%83%B3+%E3%82%A8%E3%83%AA%E3%83%83%E3%82%AF |website=patents.google.com |publisher=Japan Patent Office |access-date=20 May 2023}}</ref>
 * 1998&nbsp;— Motorola develops 256{{nbsp}}Kb MRAM test chip.<ref>{{Citation|title=Magnetic Random Access Memory Devices|date=October 2003|author=N.P. Vasil'eva|journal=Automation and Remote Control|volume=64|issue=9|pages=1369–85|doi=10.1023/a:1026039700433|s2cid=195291447}}</ref>
 * 2000&nbsp;— IBM and Infineon established a joint MRAM development program.
@@ Line 119: / Line 120: @@
 ** NVE announces technology exchange with Cypress Semiconductor.
 ** Toggle patent granted to Motorola<ref>{{cite patent|country=United States|number=6633498|title=Magnetoresistive random access memory with reduced switching field|fdate=June 18, 2002|inventor=Engel; Bradley N., Janesky; Jason Allen, Rizzo; Nicholas D.}}</ref>
-* 2003&nbsp;— A 128 kbit MRAM chip was introduced, manufactured with a 180&nbsp;nm lithographic process
+* 2003&nbsp;— A 128&nbsp;kbit MRAM chip was introduced, manufactured with a 180&nbsp;nm lithographic process
 * 2004
 ** June&nbsp;— [[Infineon]] unveiled a 16-Mbit prototype, manufactured with a 180&nbsp;nm lithographic process
 ** September&nbsp;— MRAM becomes a standard product offering at Freescale.
-** October&nbsp;— Taiwan developers of MRAM tape out 1 Mbit parts at [[TSMC]].
+** October&nbsp;— Taiwan developers of MRAM tape out 1&nbsp;Mbit parts at [[TSMC]].
 ** October&nbsp;— Micron drops MRAM, mulls other memories.
 ** December&nbsp;— TSMC, [[NEC]] and [[Toshiba]] describe novel MRAM cells.
@@ Line 136: / Line 137: @@
 ** November&nbsp;— Renesas Technology and [[Grandis (company)|Grandis]] collaborate on development of 65&nbsp;nm MRAM employing [[spin torque transfer]] (STT).
 ** November&nbsp;— NVE receives an [[SBIR]] grant to research cryptographic tamper-responsive memory.<ref>{{cite web|url=https://www.nsf.gov/awardsearch/showAward?AWD_ID=0539675|title=NSF Award Search: Award#0539675 - SBIR Phase I: Zero-Remanence Tamper-Responsive Cryptokey Memory|website=www.nsf.gov}}</ref>
-** December&nbsp;— [[Sony]] announced the first lab-produced spin-torque-transfer MRAM, which utilizes a spin-polarized current through the tunneling magnetoresistance layer to write data. This method consumes less power and is more scalable than conventional MRAM. With further advances in materials, this process should allow for densities higher than those possible in DRAM.
+** December&nbsp;— [[Sony]] announced Spin-RAM, the first lab-produced spin-torque-transfer MRAM, which utilizes a spin-polarized current through the tunneling magnetoresistance layer to write data. This method consumes less power and is more scalable than conventional MRAM. With further advances in materials, this process should allow for densities higher than those possible in DRAM.
 ** December&nbsp;— [[Freescale|Freescale Semiconductor]] Inc. demonstrates an MRAM that uses magnesium oxide, rather than an aluminum oxide, allowing for a thinner insulating tunnel barrier and improved bit resistance during the write cycle, thereby reducing the required write current.
 ** Spintec laboratory gives Crocus Technology exclusive license on its patents.
 * 2006
-** February&nbsp;— [[Toshiba]] and NEC announced a 16 Mbit MRAM chip with a new "power-forking" design.  It achieves a transfer rate of 200 Mbit/s, with a 34 ns cycle time, the best performance of any MRAM chip.  It also boasts the smallest physical size in its class&nbsp;— 78.5 square millimeters&nbsp;— and the low voltage requirement of 1.8 volts.<ref name="NEC PR 2006-02-07">{{cite press release |publisher=NEC Corporation |date=2006-02-07 |url=http://www.nec.co.jp/press/en/0602/0702.html |title=Toshiba and NEC Develop World's Fastest, Highest Density MRAM |access-date = 2006-07-10}}</ref>
+** February&nbsp;— [[Toshiba]] and NEC announced a 16&nbsp;Mbit MRAM chip with a new "power-forking" design. It achieves a transfer rate of 200&nbsp;Mbit/s, with a 34 ns cycle time, the best performance of any MRAM chip. It also boasts the smallest physical size in its class&nbsp;— 78.5 square millimeters&nbsp;— and the low voltage requirement of 1.8 volts.<ref name="NEC PR 2006-02-07">{{cite press release |publisher=NEC Corporation |date=2006-02-07 |url=http://www.nec.co.jp/press/en/0602/0702.html |title=Toshiba and NEC Develop World's Fastest, Highest Density MRAM |access-date = 2006-07-10}}</ref>
 ** July&nbsp;— On July 10, Austin Texas&nbsp;— Freescale Semiconductor begins marketing a 4-Mbit MRAM chip, which sells for approximately $25.00 per chip.<ref name="Freescale PR 2006-07-10">{{cite press release |publisher=Freescale Semiconductor |date=2006-07-10 |url=http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-newsArticle&ID=880030 |title=Freescale Leads Industry in Commercializing MRAM Technology |access-date=2006-07-10 |url-status=dead |archive-url=https://web.archive.org/web/20071013124650/http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-newsArticle&ID=880030 |archive-date=2007-10-13 }}</ref><ref>{{Cite news|url=http://eetimes.com/electronics-news/4062196/MRAM-debut-cues-memory-transition|title=MRAM debut cues memory transition|last=Lammers|first=David|date=October 7, 2006|publisher=EE Times}}</ref>
 * 2007
 ** R&D moving to [[spin-transfer torque|spin transfer torque]] RAM (SPRAM)
 ** February&nbsp;— Tohoku University and Hitachi developed a prototype 2-Mbit non-volatile RAM chip employing spin-transfer torque switching.<ref name="Hitachi PR 2007-02-13">{{cite press release |publisher=Hitachi Ltd. |date=2007-02-13 |url=http://www.hitachi.com/New/cnews/070213.html |title=Prototype 2 Mbit Non-Volatile RAM Chip Employing Spin-Transfer Torque Writing Method |access-date = 2007-02-13}}</ref>
-** August&nbsp;— "IBM, TDK Partner In Magnetic Memory Research on Spin Transfer Torque Switching" IBM and TDK to lower the cost and boost performance of MRAM to hopefully release a product to market.<ref name="IBM PR 2007-08-19">{{cite press release | publisher=IBM |date=2007-08-19|url=http://www-03.ibm.com/press/us/en/pressrelease/22180.wss |title=IBM and TDK Launch Joint Research & Development Project for Advanced MRAM |access-date = 2007-08-22}}</ref>
+** August&nbsp;— "IBM, TDK Partner In Magnetic Memory Research on Spin Transfer Torque Switching" IBM and TDK to lower the cost and boost performance of MRAM to hopefully release a product to market.<ref name="IBM PR 2007-08-19">{{cite press release | publisher=IBM |date=2007-08-19|url=http://www-03.ibm.com/press/us/en/pressrelease/22180.wss |archive-url=https://web.archive.org/web/20071013122724/http://www-03.ibm.com/press/us/en/pressrelease/22180.wss |url-status=dead |archive-date=October 13, 2007 |title=IBM and TDK Launch Joint Research & Development Project for Advanced MRAM |access-date = 2007-08-22}}</ref>
 ** November&nbsp;— Toshiba applied and proved the spin-transfer torque switching with perpendicular magnetic anisotropy MTJ device.<ref name="Toshiba PR 2007-11-6">{{cite press release |publisher=Toshiba Corporation |date=2007-11-06 |url=http://www.toshiba.co.jp/about/press/2007_11/pr0601.htm |title=Toshiba develops new MRAM device that opens the way to giga-bits capacity |access-date = 2007-11-06}}</ref>
 ** November&nbsp;— NEC develops world's fastest SRAM-compatible MRAM with operation speed of 250&nbsp;MHz.<ref name="NEC PR 2007-11-30">{{cite press release |publisher=NEC Corporation |date=2007-11-30 |url=http://www.nec.co.jp/press/en/0711/3001.html |title=NEC Develops World's Fastest SRAM-Compatible MRAM With Operation Speed of 250MHz. |access-date = 2007-12-01}}</ref>
 * 2008
 ** Japanese satellite, SpriteSat, to use Freescale MRAM to replace SRAM and FLASH components<ref name="sciam.com">{{cite web|url=https://www.scientificamerican.com/article/japanese-satellite-mram-freescale/|title=Japanese Satellite First to Use Magnetic Memory|first=Larry|last=Greenemeier|website=Scientific American}}</ref>
-** June&nbsp;— [[Samsung]] and [[Hynix]] become partner on STT-MRAM<ref>{{Cite web |url=http://www.eetasia.com/ART_8800531562_480200_NT_cf6338bb.HTM |title=Archived copy |access-date=2008-10-01 |archive-url=https://web.archive.org/web/20081112072440/http://www.eetasia.com/ART_8800531562_480200_NT_cf6338bb.HTM |archive-date=2008-11-12 |url-status=dead }}</ref>
+** June&nbsp;— [[Samsung]] and [[Hynix]] become partner on STT-MRAM<ref>{{Cite web |url=http://www.eetasia.com/ART_8800531562_480200_NT_cf6338bb.HTM |title=Samsung, Hynix partner on STT-MRAM |access-date=2008-10-01 |archive-url=https://web.archive.org/web/20081112072440/http://www.eetasia.com/ART_8800531562_480200_NT_cf6338bb.HTM |archive-date=2008-11-12 |url-status=dead }}</ref>
-** June&nbsp;— Freescale spins off MRAM operations as new company Everspin<ref>{{Cite web|url=http://everspin.com/PDF/press/2008_june9_Everspin%20Release.pdf|title=Wayback Machine<!-- Bot generated title -->|archive-url=https://web.archive.org/web/20120726215228/http://everspin.com/PDF/press/2008_june9_Everspin%20Release.pdf|archive-date=2012-07-26}}</ref><ref>{{Cite news|url=https://www.nytimes.com/2008/06/09/technology/09freescale.html?_r=3&scp=2&sq=MRAM&st=cse&oref=slogin&oref=slogin|title=Chip Maker to Announce It Will Spin Off Memory Unit|last=de la Merced|first=Michael J.|date=June 9, 2008|work=The New York Times}}</ref>
+** June&nbsp;— Freescale spins off MRAM operations as new company Everspin<ref>{{Cite press release |url=http://everspin.com/PDF/press/2008_june9_Everspin%20Release.pdf |date=29 June 2008 |title=Freescale launches independent company to accelerate MRAM business |archive-url=https://web.archive.org/web/20120726215228/http://everspin.com/PDF/press/2008_june9_Everspin%20Release.pdf|archive-date=2012-07-26}}</ref><ref>{{Cite news|url=https://www.nytimes.com/2008/06/09/technology/09freescale.html?_r=3&scp=2&sq=MRAM&st=cse&oref=slogin&oref=slogin|title=Chip Maker to Announce It Will Spin Off Memory Unit|last=de la Merced|first=Michael J.|date=June 9, 2008|work=The New York Times}}</ref>
 ** August&nbsp;— Scientists in Germany have developed next-generation MRAM that is said to operate as fast as fundamental performance limits allow, with write cycles under 1 nanosecond.
-** November&nbsp;— [[Everspin Technologies|Everspin]] announces [[Ball grid array|BGA]] packages, product family from 256Kb to 4Mb<ref>{{Cite news|url=http://eetimes.com/electronics-products/memory-products/4108834/Freescale-s-MRAM-spin-off-rolls-new-devices|title=Freescale's MRAM spin-off rolls new devices|last=LaPedus|first=Mark|date=November 13, 2008|work=EE Times}}</ref>
+** November&nbsp;— [[Everspin Technologies|Everspin]] announces [[Ball grid array|BGA]] packages, product family from 256&nbsp;Kb to 4&nbsp;Mb<ref>{{Cite news|url=http://eetimes.com/electronics-products/memory-products/4108834/Freescale-s-MRAM-spin-off-rolls-new-devices|title=Freescale's MRAM spin-off rolls new devices|last=LaPedus|first=Mark|date=November 13, 2008|work=EE Times}}</ref>
 * 2009
+** June&nbsp;— Hitachi and Tohoku University demonstrated a 32-Mbit spin-transfer torque RAM (SPRAM).<ref>{{cite conference |last1=Takemura |first1=R. |last2=Kawahara |first2=T. |last3=Miura |first3=K. |last4=Yamamoto |first4=H. |last5=Hayakawa |first5=J. |last6=Matsuzaki |first6=N. |last7=Ono |first7=K. |last8=Yamanouchi |first8=M. |last9=Ito |first9=K. |last10=Takahashi |first10=H. |last11=Ikeda |first11=S. |title=32-mb 2t1r spram with localized bi-directional write driver and '1'/'0'dual-array equalized reference cell |book-title=2009 Symposium on VLSI Circuits |publisher=IEEE |date=2009 |isbn=978-1-4244-3307-0 |pages=84–85 |url=https://ieeexplore.ieee.org/document/5205284}}</ref>
-** June&nbsp;— Hitachi and Tohoku University demonstrated a 32-Mbit spin-transfer torque RAM (SPRAM).<ref>[http://www.vlsisymposium.org/circuits/cir_abstract/8-4.htm ] {{webarchive |url=https://web.archive.org/web/20090531054904/http://www.vlsisymposium.org/circuits/cir_abstract/8-4.htm |date=May 31, 2009 }}</ref>
 ** June&nbsp;— [[Crocus Technology]] and Tower Semiconductor announce deal to port Crocus' MRAM process technology to Tower's manufacturing environment<ref>{{Cite web|url=https://crocus-technology.com/news/|archive-url=https://web.archive.org/web/20100422232721/http://www.crocus-technology.com/pr-06-18-09.html|url-status=dead|title=News &#124; Crocus Technology|archive-date=April 22, 2010}}</ref>
 ** November&nbsp;— [[Everspin Technologies|Everspin]] releases SPI MRAM product family<ref>{{Cite news|url=http://eetimes.com/electronics-news/4085891/MRAM-chips-go-serial-in-smart-meters|title=MRAM chips go serial in smart meters|last=Johnson|first=R Colin|date=November 16, 2009|work=EE Times}}</ref> and ships first embedded MRAM samples
 * 2010
-** April&nbsp;— Everspin releases 16Mb density<ref>{{Cite news|url=http://www.edn.com/blog/Practical_Chip_Design/37503-Everspin_MRAM_reaches_16_Mbits_looks_toward_embedded_use_in_SoCs.php|title=Everspin MRAM reaches 16 Mbits, looks toward embedded use in SoCs|date=April 19, 2010|publisher=EDN|author=Ron Wilson|url-status=dead|archive-url=https://archive.today/20130121230927/http://www.edn.com/blog/Practical_Chip_Design/37503-Everspin_MRAM_reaches_16_Mbits_looks_toward_embedded_use_in_SoCs.php|archive-date=January 21, 2013}}</ref><ref>{{Cite news|url=http://www.electronicsweekly.com/blogs/david-manners-semiconductor-blog/2010/04/everspin-launches-16mbit-mram.html|title=Everspin Launches 16Mbit MRAM, Volume In July|date=April 20, 2010|publisher=Electronics Weekly|author=David Manners}}</ref>
+** April&nbsp;— Everspin releases 16&nbsp;Mb density<ref>{{Cite news|url=http://www.edn.com/blog/Practical_Chip_Design/37503-Everspin_MRAM_reaches_16_Mbits_looks_toward_embedded_use_in_SoCs.php|title=Everspin MRAM reaches 16 Mbits, looks toward embedded use in SoCs|date=April 19, 2010|publisher=EDN|author=Ron Wilson|url-status=dead|archive-url=https://archive.today/20130121230927/http://www.edn.com/blog/Practical_Chip_Design/37503-Everspin_MRAM_reaches_16_Mbits_looks_toward_embedded_use_in_SoCs.php|archive-date=January 21, 2013}}</ref><ref>{{Cite news|url=http://www.electronicsweekly.com/blogs/david-manners-semiconductor-blog/2010/04/everspin-launches-16mbit-mram.html|title=Everspin Launches 16Mbit MRAM, Volume In July|date=April 20, 2010|publisher=Electronics Weekly|author=David Manners}}</ref>
 ** June&nbsp;— Hitachi and Tohoku Univ announce Multi-level SPRAM<ref>{{cite web|author=Motoyuki Ooishi|author2=Nikkei Electronics |url=http://techon.nikkeibp.co.jp/english/NEWS_EN/20100622/183658/ |title=[VLSI&#93; Hitachi, Tohoku Univ Announce Multi-level Cell SPRAM&nbsp;— Tech-On! |publisher=Techon.nikkeibp.co.jp |date=2010-06-23 |access-date=2014-01-09}}</ref>
 * 2011
-** March&nbsp;— PTB, Germany, announces below 500 ps (2Gbit/s) write cycle<ref>{{cite press release|title=Extremely fast MRAM data storage within reach|date=2011-03-08|url=http://www.ptb.de/en/aktuelles/archiv/presseinfos/pi2011/pitext/pi110308.html|publisher=PTB|access-date=2011-03-09}}</ref>
+** March&nbsp;— PTB, Germany, announces below 500 ps (2&nbsp;Gbit/s) write cycle<ref>{{cite press release|title=Extremely fast MRAM data storage within reach|date=2011-03-08|url=http://www.ptb.de/en/aktuelles/archiv/presseinfos/pi2011/pitext/pi110308.html|publisher=PTB|access-date=2011-03-09}}</ref>
 * 2012
-** November&nbsp;— Chandler, Arizona, USA, Everspin debuts 64Mb ST-MRAM on a [[90 nm process]].<ref>{{Cite news|url=http://semiaccurate.com/2012/11/16/everspin-makes-st-mram-a-reality/|title=Everspin makes ST-MRAM a reality, LSI AIS 2012: Non-volatile memory with DDR3 speeds|date=November 16, 2012|publisher=SemiAccurate.com|author=Charlie Demerjian}}</ref><ref>{{Cite web|url=http://www.everspin.com/PDF/ST-MRAM_Press_Release.pdf|archive-url=https://web.archive.org/web/20130330004801/http://everspin.com/PDF/ST-MRAM_Press_Release.pdf|url-status=dead|title=Everspin press release|archive-date=March 30, 2013}}</ref>
+** November&nbsp;— Chandler, Arizona, USA, Everspin debuts 64&nbsp;Mb ST-MRAM on a [[90 nm process]].<ref>{{Cite news|url=http://semiaccurate.com/2012/11/16/everspin-makes-st-mram-a-reality/|title=Everspin makes ST-MRAM a reality, LSI AIS 2012: Non-volatile memory with DDR3 speeds|date=November 16, 2012|publisher=SemiAccurate.com|author=Charlie Demerjian}}</ref><ref>{{Cite web|url=http://www.everspin.com/PDF/ST-MRAM_Press_Release.pdf|archive-url=https://web.archive.org/web/20130330004801/http://everspin.com/PDF/ST-MRAM_Press_Release.pdf|url-status=dead|title=Everspin press release|archive-date=March 30, 2013}}</ref>
 ** December&nbsp;— A team from [[University of California, Los Angeles]] presents voltage-controlled MRAM at IEEE [[International Electron Devices Meeting]].<ref>{{cite web|url=http://www.eetimes.com/document.asp?doc_id=1280508|website=EE Times|title=Voltage-controlled MRAM: Status, challenges and prospects}}</ref>
 * 2013
 ** November&nbsp;— [[Buffalo Technology]] and Everspin announce a new industrial SATA III SSD that incorporates Everspin's Spin-Torque MRAM (ST-MRAM) as cache memory.<ref>{{cite web|url=http://www.businesswire.com/news/home/20131118005368/en/Everspin-ST-MRAM-Incorporated-Cache-Memory-Buffalo-Memory |title=Everspin ST-MRAM Incorporated for Cache Memory Into Buffalo Memory SSD |publisher=Business Wire |date=2013-11-18 |access-date=2014-01-09}}</ref>
 * 2014
-** January&nbsp;— Researchers announce the ability to control the magnetic properties of core/shell antiferromagnetic nanoparticles using only temperature and magnetic field changes.<ref>{{cite web|url=http://www.gizmag.com/magnetic-nanoparticles-digital-storage-amf-uab/30299/ |title=Magnetic nanoparticles breakthrough could help shrink digital storage |publisher=Gizmag.com |access-date=2014-01-09}}</ref>
+** January&nbsp;— Researchers announce the ability to control the magnetic properties of core/shell antiferromagnetic [[nanoparticle]]s using only temperature and magnetic field changes.<ref>{{cite web|url=http://www.gizmag.com/magnetic-nanoparticles-digital-storage-amf-uab/30299/ |title=Magnetic nanoparticles breakthrough could help shrink digital storage |date=8 January 2014 |publisher=Gizmag.com |access-date=2014-01-09}}</ref>
-** October — Everspin partners with [[GlobalFoundries]] to produce ST-MRAM on 300 mm wafers.<ref>{{Cite web|last=jithil.g@position2.com|date=2014-10-27|title=Everspin and GLOBALFOUNDRIES Partner to Supply Fully Processed 300mm CMOS Wafers with Everspin's ST-MRAM Technology|url=https://www.globalfoundries.com/news-events/press-releases/everspin-and-globalfoundries-partner-to-supply-fully-processed-300mm-cmos-wafers-with-everspins-st-mram-technology|access-date=2020-08-22|website=GLOBALFOUNDRIES|language=en}}</ref>
+** October — Everspin partners with [[GlobalFoundries]] to produce ST-MRAM on 300&nbsp;mm wafers.<ref>{{Cite press release|date=2014-10-27|title=Everspin and GLOBALFOUNDRIES Partner to Supply Fully Processed 300mm CMOS Wafers with Everspin's ST-MRAM Technology|url=https://www.globalfoundries.com/news-events/press-releases/everspin-and-globalfoundries-partner-to-supply-fully-processed-300mm-cmos-wafers-with-everspins-st-mram-technology|access-date=2020-08-22|website=GLOBALFOUNDRIES|language=en|archive-date=2020-09-24|archive-url=https://web.archive.org/web/20200924185045/https://www.globalfoundries.com/news-events/press-releases/everspin-and-globalfoundries-partner-to-supply-fully-processed-300mm-cmos-wafers-with-everspins-st-mram-technology|url-status=dead}}</ref>
 * 2016
 ** April&nbsp;— Samsung's semiconductor chief Kim Ki-nam says Samsung is developing an MRAM technology that "will be ready soon".<ref>
-{{cite web|url=http://www.koreatimes.co.kr/www/news/tech/2016/04/133_203023.html|title=Cheil Worldwide acquires Founded|last1=Kim |first1=Yoo-chul |date=20 April 2016 |website=Koreatimes.co.kr |publisher=Korea Times |access-date=27 June 2016|quote='Yes, Samsung will commercialize MRAMs and ReRAMs according to our own schedule. We are on our way and will be ready soon,' Kim told reporters.
+{{cite web|url=https://www.koreatimes.co.kr/www/news/tech/2016/04/133_203023.html|title=Cheil Worldwide acquires Founded|last1=Kim |first1=Yoo-chul |date=20 April 2016 |website=Koreatimes.co.kr |publisher=Korea Times |access-date=27 June 2016|quote='Yes, Samsung will commercialize MRAMs and ReRAMs according to our own schedule. We are on our way and will be ready soon,' Kim told reporters.
 }}</ref>
 ** July&nbsp;— IBM and Samsung report an MRAM device capable of scaling down to 11&nbsp;nm with a switching current of 7.5 microamps at 10 ns.<ref>{{Cite web|url=https://www.ibm.com/blogs/research/2016/07/ibm-celebrates-20-years-spin-torque-mram-scaling-11-nanometers/|title=Researchers celebrate 20th anniversary of IBM's invention of Spin Torque MRAM by demonstrating scalability for the next decade&nbsp;— IBM Blog Research|date=2016-07-07|website=IBM Blog Research|language=en-US|access-date=2016-07-11}}</ref>
-** August&nbsp;— Everspin announced it was shipping samples of the industry's first 256Mb ST-MRAM to customers.<ref>{{Cite web|url=http://www.thessdreview.com/daily-news/everspin-announces-sampling-industrys-first-256mb-perpendicular-spin-torque-mram-customers-production-preparations-underway/|title=Everspin Announces Sampling of Industry's First 256Mb Perpendicular Spin Torque MRAM to Customers|last=Strong|first=Scott|date=August 5, 1026|website=The SSD Review}}</ref>
+** August&nbsp;— Everspin announced it was shipping samples of the industry's first 256&nbsp;Mb ST-MRAM to customers.<ref>{{Cite web|url=http://www.thessdreview.com/daily-news/everspin-announces-sampling-industrys-first-256mb-perpendicular-spin-torque-mram-customers-production-preparations-underway/|title=Everspin Announces Sampling of Industry's First 256Mb Perpendicular Spin Torque MRAM to Customers|last=Strong|first=Scott|date=August 5, 1026|website=The SSD Review}}</ref>
-** October&nbsp;— [[Avalanche Technology]] partners with [[Sony Semiconductor Manufacturing]] to manufacture STT-MRAM on 300 mm wafers, based on "a variety of manufacturing nodes".<ref>{{Cite web|date=2016-10-31|title=Sony revealed as MRAM foundry for Avalanche|url=https://www.eenewsanalog.com/news/sony-revealed-mram-foundry-avalanche|access-date=2020-08-22|website=eeNews Analog|language=en}}</ref>
+** October&nbsp;— [[Avalanche Technology]] partners with [[Sony Semiconductor Manufacturing]] to manufacture STT-MRAM on 300&nbsp;mm wafers, based on "a variety of manufacturing nodes".<ref>{{Cite web|date=2016-10-31|title=Sony revealed as MRAM foundry for Avalanche|url=https://www.eenewsanalog.com/news/sony-revealed-mram-foundry-avalanche|access-date=2020-08-22|website=eeNews Analog|language=en}}</ref>
-** December&nbsp;— [[Inston]] and [[Toshiba]] independently present results on voltage-controlled MRAM at [[International Electron Devices Meeting]].<ref>{{cite web|url=http://www.analog-eetimes.com/news/iedm-magnetic-ram-debuts-28nm-embedded-nvm|website=EE Times|title=Archived copy|access-date=2017-03-03|archive-url=https://web.archive.org/web/20170303130002/http://www.analog-eetimes.com/news/iedm-magnetic-ram-debuts-28nm-embedded-nvm|archive-date=2017-03-03|url-status=dead}}</ref>
+** December&nbsp;— [[Inston]] and [[Toshiba]] independently present results on voltage-controlled MRAM at [[International Electron Devices Meeting]].<ref>{{cite web|url=http://www.analog-eetimes.com/news/iedm-magnetic-ram-debuts-28nm-embedded-nvm|website=EE Times|title=IEDM: Magnetic RAM debuts as 28nm embedded NVM &#124; EETE Analog|access-date=2017-03-03|archive-url=https://web.archive.org/web/20170303130002/http://www.analog-eetimes.com/news/iedm-magnetic-ram-debuts-28nm-embedded-nvm|archive-date=2017-03-03|url-status=dead}}</ref>
 * 2019
-** January — Everspin starts shipping samples of 28&nbsp;nm 1Gb STT-MRAM chips.<ref>{{Cite web|url=https://www.mram-info.com/everspin-starts-ship-customer-samples-its-28nm-1gb-stt-mram-chips|title=Everspin starts to ship customer samples of its 28nm 1Gb STT-MRAM chips {{!}} MRAM-Info|website=www.mram-info.com|access-date=2019-12-03}}</ref>
+** January — Everspin starts shipping samples of 28&nbsp;nm 1&nbsp;Gb STT-MRAM chips.<ref>{{Cite web|url=https://www.mram-info.com/everspin-starts-ship-customer-samples-its-28nm-1gb-stt-mram-chips|title=Everspin starts to ship customer samples of its 28nm 1Gb STT-MRAM chips {{!}} MRAM-Info|website=www.mram-info.com|access-date=2019-12-03}}</ref>
-** March — Samsung commence commercial production of its first embedded STT-MRAM based on a 28 nm process.<ref>{{Cite news|title=Samsung Says It's Shipping 28-nm Embedded MRAM|work=EE Times|url=https://www.eetimes.com/samsung-says-its-shipping-28-nm-embedded-mram/}}</ref>
+** March — Samsung commence commercial production of its first embedded STT-MRAM based on a 28&nbsp;nm process.<ref>{{Cite news|title=Samsung Says It's Shipping 28-nm Embedded MRAM|work=EE Times|url=https://www.eetimes.com/samsung-says-its-shipping-28-nm-embedded-mram/}}</ref>
-** May — Avalanche partners with [[United Microelectronics Corporation]] to jointly develop and produce embedded MRAM based on the latter's 28 nm CMOS manufacturing process.<ref>{{Cite web|last=Admin|date=2018-08-06|title=UMC and Avalanche Technology Partner for MRAM Development and 28nm Production|url=http://www.avalanche-technology.com/umc-and-avalanche-technology-partner-for-mram-development-and-28nm-production/|access-date=2020-08-22|website=Avalanche Technology|language=en-US}}</ref>
+** May — Avalanche partners with [[United Microelectronics Corporation]] to jointly develop and produce embedded MRAM based on the latter's 28&nbsp;nm CMOS manufacturing process.<ref>{{Cite web|date=2018-08-06|title=UMC and Avalanche Technology Partner for MRAM Development and 28nm Production|url=http://www.avalanche-technology.com/umc-and-avalanche-technology-partner-for-mram-development-and-28nm-production/|access-date=2020-08-22|website=Avalanche Technology|language=en-US}}</ref>
 * 2020
-** December — IBM announces a 14nm MRAM node.<ref>{{Cite web|last=Admin|date=2020-12-15|title=IBM to reveal the world's first 14nm STT-MRAM node|url=https://www.mram-info.com/ibm-reveal-worlds-first-14nm-stt-mram-node|access-date=2020-12-17|language=en-US}}</ref>
+** December — IBM announces a 14&nbsp;nm MRAM node.<ref>{{Cite web|date=2020-12-15|title=IBM to reveal the world's first 14nm STT-MRAM node|url=https://www.mram-info.com/ibm-reveal-worlds-first-14nm-stt-mram-node|access-date=2020-12-17|language=en-US}}</ref>
 * 2021
-** May — [[TSMC]] revealed a [[wikt:roadmap|roadmap]] for developing the eMRAM technology at 12/14nm node as an offering to replace eFLASH.<ref>{{Cite web|title=TSMC shows its eMRAM technology roadmap {{!}} MRAM-Info|url=https://www.mram-info.com/tsmc-shows-its-emram-technology-roadmap|access-date=2021-05-16|website=www.mram-info.com}}</ref>
+** May — [[TSMC]] revealed a [[wikt:roadmap|roadmap]] for developing the eMRAM technology at 12/14&nbsp;nm node as an offering to replace eFLASH.<ref>{{Cite web|title=TSMC shows its eMRAM technology roadmap {{!}} MRAM-Info|url=https://www.mram-info.com/tsmc-shows-its-emram-technology-roadmap|access-date=2021-05-16|website=www.mram-info.com}}</ref>
 ** November — [[Taiwan Semiconductor Research Institute]] announced the development of a SOT-MRAM device.<ref>{{cite web |last1=Chia-nan |first1=Lin |title=Local researchers make advanced MRAM device |url=https://www.taipeitimes.com/News/taiwan/archives/2021/11/10/2003767639 |website=www.taipeitimes.com |publisher=Taipei Times |access-date=9 November 2021}}</ref>
 ==Applications==
-Possible practical application of the MRAM includes virtually every device  that it has some type of memory inside such as [[aerospace]] and military systems, [[digital camera]]s, [[laptop|notebooks]], [[smart card]]s, [[mobile telephone]]s, cellular base stations, [[personal computer]]s, battery-backed [[static random-access memory|SRAM]] replacement, datalogging specialty memories ([[flight data recorder|black box]] solutions), media players, and book readers etc.
+Possible practical application of the MRAM includes virtually every device that has some type of memory inside such as [[aerospace]] and military systems, [[digital camera]]s, [[laptop|notebooks]], [[smart card]]s, [[mobile telephone]]s, cellular base stations, [[personal computer]]s, battery-backed [[static random-access memory|SRAM]] replacement, datalogging specialty memories ([[flight data recorder|black box]] solutions), media players, and book readers etc.
 ==See also==
@@ Line 196: / Line 197: @@
 * Magnetic [[bubble memory]]
 * [[EEPROM]]
+* [[Everspin Technologies]] <!-- Do not add promotional links to company articles lacking substantial useful content on the topic of MRAM. The Everspin article is almost entirely MRAM content. -->
 * [[Ferroelectric RAM|F-RAM]]
 * [[Ferromagnetism]]
 * [[Magnetoresistance]]
 * [[Memristor]]
+* [[MOSFET]]
 * [[Nano-RAM|NRAM]]
 * [[nvSRAM]]
 * [[Phase-change memory]] (PRAM)
-* [[Ramtron International]]
-* [[MOSFET]]
 * [[Spin valve]]
-* [[Tunnel magnetoresistance]]
 * [[Spin-transfer torque]]
-* [[Freescale Semiconductor]]
+* [[Tunnel magnetoresistance]]
-* [[Crocus Technology]]
-* [[Everspin Technologies]]
-* [[Grandis (company)]]
 {{div col end}}
@@ Line 218: / Line 216: @@
 ==External links==
-* {{Cite journal | last1 = Sbiaa | first1 = R. | last2 = Meng | first2 = H. | last3 = Piramanayagam | first3 = S. N. | doi = 10.1002/pssr.201105420 | title = Materials with perpendicular magnetic anisotropy for magnetic random access memory | journal = Physica Status Solidi RRL | volume = 5 | issue = 12 | pages = 413 | year = 2011 | bibcode = 2011PSSRR...5..413S| s2cid = 98626346 |ref=none }}
+* {{Cite journal | last1 = Sbiaa | first1 = R. | last2 = Meng | first2 = H. | last3 = Piramanayagam | first3 = S. N. | doi = 10.1002/pssr.201105420 | title = Materials with perpendicular magnetic anisotropy for magnetic random access memory | journal = Physica Status Solidi RRL | volume = 5 | issue = 12 | pages = 413 | year = 2011 | bibcode = 2011PSSRR...5..413S| s2cid = 98626346 |ref=none | doi-access = free }}
 * {{cite web |url=http://www.research.ibm.com/thinkresearch/pages/2001/20010202_mram.shtml |work=IBM research |title=MRAM |first=Richard |last=Butner |date=2001}}
-* {{Cite journal | last1 = Akerman | first1 = J. | title = APPLIED PHYSICS: Toward a Universal Memory | doi = 10.1126/science.1110549 | journal = Science | volume = 308 | issue = 5721 | pages = 508–510 | year = 2005 | pmid =  15845842| s2cid = 60577959 |ref=none}}
+* {{Cite journal | last1 = Akerman | first1 = J. | title = APPLIED PHYSICS: Toward a Universal Memory | doi = 10.1126/science.1110549 | journal = Science | volume = 308 | issue = 5721 | pages = 508–510 | year = 2005 | pmid = 15845842| s2cid = 60577959 |ref=none}}
-* {{Cite journal | last1 = Allwood | first1 = D. A. | last2 = Xiong | first2 = G. | last3 = Faulkner | first3 = C. C. | last4 = Atkinson | first4 = D. | last5 = Petit | first5 = D. | last6 = Cowburn | first6 = R. P. | title = Magnetic Domain-Wall Logic | doi = 10.1126/science.1108813 | journal = Science | volume = 309 | issue = 5741 | pages = 1688–92 | year = 2005 | pmid =  16151002| bibcode = 2005Sci...309.1688A | s2cid = 23385116 |ref=none}}
+* {{Cite journal | last1 = Allwood | first1 = D. A. | last2 = Xiong | first2 = G. | last3 = Faulkner | first3 = C. C. | last4 = Atkinson | first4 = D. | last5 = Petit | first5 = D. | last6 = Cowburn | first6 = R. P. | title = Magnetic Domain-Wall Logic | doi = 10.1126/science.1108813 | journal = Science | volume = 309 | issue = 5741 | pages = 1688–92 | year = 2005 | pmid = 16151002| bibcode = 2005Sci...309.1688A | s2cid = 23385116 |ref=none}}
 * [https://www.wired.com/news/technology/0,70190-0.html Wired News article from February, 2006] {{Webarchive|url=https://web.archive.org/web/20080821214144/http://wired.com/news/technology/0,70190-0.html |date=2008-08-21 }}
 * [http://www.nec.co.jp/press/en/0602/0702.html NEC Press Release from February, 2006]
@@ Line 229: / Line 227: @@
 * [https://web.archive.org/web/20081020075408/http://www.bama.ua.edu/~tmewes/Java/dynamics/MagnetizationDynamics2.shtml Spin torque applet] – An applet illustrating the principles underlying spin-torque transfer MRAM
 * [https://web.archive.org/web/20080925021347/http://thefutureofthings.com/news/5401/new-speed-record-for-magnetic-memories.html New Speed Record for Magnetic Memories] – [[The Future of Things]] article
-* {{Cite journal|title=Spintronics based random access memory: a review |journal= Materials Today|year=2017|volume=20|pages=530–548|doi=10.1016/j.mattod.2017.07.007|last1=Bhatti|first1=Sabpreet|last2=Sbiaa|first2=Rachid|last3=Hirohata|first3=Atsufumi|last4=Ohno|first4=Hideo|last5=Fukami|first5=Shunsuke|last6=Piramanayagam|first6=S.N.|issue=9|doi-access=free}}
+* {{Cite journal|title=Spintronics based random access memory: a review |journal= Materials Today|year=2017|volume=20|pages=530–548|doi=10.1016/j.mattod.2017.07.007|last1=Bhatti|first1=Sabpreet|last2=Sbiaa|first2=Rachid|last3=Hirohata|first3=Atsufumi|last4=Ohno|first4=Hideo|last5=Fukami|first5=Shunsuke|last6=Piramanayagam|first6=S.N.|issue=9|doi-access=free|hdl=10356/146755|hdl-access=free}}
 {{Magnetic storage media}}
@@ Line 237: / Line 235: @@
 [[Category:Non-volatile memory]]
 [[Category:Spintronics]]
-[[Category:Emerging technologies]]