Jump to content

Parallel Thread Execution: Difference between revisions

From Wikipedia, the free encyclopedia
Browse history interactively
← Previous edit
Content deleted Content added
VisualWikitext
→See also: improved link
Added Category named "Instruction set architectures"
 
(7 intermediate revisions by 5 users not shown)
Line 1: Line 1:
{{Primary sources|date=August 2020}}
{{Primary sources|date=August 2020}}
{{short description|Low-level parallel thread execution virtual machine and instruction set architecture}}
{{short description|Low-level parallel thread execution virtual machine and instruction set architecture}}
'''Parallel Thread Execution''' ('''PTX''' or '''NVPTX'''<ref>{{cite web|url=https://llvm.org/docs/NVPTXUsage.html|title=User Guide for NVPTX Back-end — LLVM 7 documentation|website=llvm.org}}</ref>) is a low-level [[Parallel computing|parallel]] [[Thread (computing)|thread]] [[Execution (computing)|execution]] [[virtual machine]] and [[instruction set architecture]] used in [[Nvidia]]'s [[CUDA]] programming environment. The [[Nvidia CUDA Compiler|NVCC]] compiler translates code written in CUDA, a [[C++ (programming language)|C++]]-like language, into PTX instructions, and the graphics driver contains a compiler which translates the PTX instructions into a binary code<ref>{{Cite web|url=https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html#instruction-set-ref|title=CUDA Binary Utilities|last=|first=|date=|website=docs.nvidia.com|language=en-us|url-status=live|archive-url=|archive-date=|access-date=2019-10-19}}</ref> which can be run on the processing cores of [[List of Nvidia graphics processing units|Nvidia GPUs]]. The [[GNU Compiler Collection]] also has basic ability for PTX generation in the context of [[OpenMP]] offloading.<ref>{{cite web |title=nvptx |url=https://gcc.gnu.org/wiki/nvptx |website=GCC Wiki}}</ref> Inline PTX assembly can be used in CUDA.<ref>{{Cite web|url=http://docs.nvidia.com/cuda/inline-ptx-assembly/index.html|title=Inline PTX Assembly in CUDA|website=docs.nvidia.com|language=en-us|access-date=2019-11-03}}</ref>
'''Parallel Thread Execution''' ('''PTX''' or '''NVPTX'''<ref>{{cite web|url=https://llvm.org/docs/NVPTXUsage.html|title=User Guide for NVPTX Back-end – LLVM 7 documentation|website=llvm.org}}</ref>) is a low-level [[Parallel computing|parallel]] [[Thread (computing)|thread]] [[Execution (computing)|execution]] [[virtual machine]] and [[instruction set architecture]] used in [[Nvidia]]'s Compute Unified Device Architecture ([[CUDA]]) programming environment. The [[Nvidia CUDA Compiler]] (NVCC) translates code written in CUDA, a [[C++]]-like language, into PTX instructions (an [[assembly language]] represented as American Standard Code for Information Interchange ([[ASCII]]) text), and the graphics driver contains a [[compiler]] which translates PTX instructions into executable binary code,<ref>{{Cite web|url=https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html#instruction-set-ref|title=CUDA Binary Utilities|last=|first=|date=|website=docs.nvidia.com|language=en-us|archive-url=|archive-date=|access-date=2019-10-19}}</ref> which can run on the processing cores of [[List of Nvidia graphics processing units|Nvidia]] [[graphics processing unit]]s (GPUs). The [[GNU Compiler Collection]] also has basic ability to generate PTX in the context of [[OpenMP]] offloading.<ref>{{cite web |title=nvptx |url=https://gcc.gnu.org/wiki/nvptx |website=GCC Wiki}}</ref> Inline PTX assembly can be used in CUDA.<ref>{{Cite web|url=http://docs.nvidia.com/cuda/inline-ptx-assembly/index.html|title=Inline PTX Assembly in CUDA|website=docs.nvidia.com|language=en-us|access-date=2019-11-03}}</ref>


== Registers ==
== Registers ==
PTX uses an arbitrarily large register set; the output from the compiler is almost pure [[Static_single_assignment_form|single-assignment form]], with consecutive lines generally referring to consecutive registers. Programs start with declarations of the form
PTX uses an arbitrarily large [[processor register]] set; the output from the compiler is almost pure [[static single-assignment form]], with consecutive lines generally referring to consecutive registers. Programs start with declarations of the form
<syntaxhighlight lang="asm">
<syntaxhighlight lang="ptx">
.reg .u32 %r<335>; // declare 335 registers %r0, %r1, ..., %r334 of type unsigned 32-bit integer
.reg .u32 %r<335>; // declare 335 registers %r0, %r1, ..., %r334 of type unsigned 32-bit integer
</syntaxhighlight>
</syntaxhighlight>


It is a three-argument assembly language, and almost all instructions explicitly list the data type (in terms of sign and width) on which they operate. Register names are preceded with a % character and constants are literal, e.g.:
It is a three-argument assembly language, and almost all instructions explicitly list the data type (in sign and width) on which they operate. Register names are preceded with a % character and constants are literal, e.g.:
<syntaxhighlight lang="asm">
<syntaxhighlight lang="ptx">
shr.u64 %rd14, %rd12, 32; // shift right an unsigned 64-bit integer from %rd12 by 32 positions, result in %rd14
shr.u64 %rd14, %rd12, 32; // shift right an unsigned 64-bit integer from %rd12 by 32 positions, result in %rd14
cvt.u64.u32 %rd142, %r112; // convert an unsigned 32-bit integer to 64-bit
cvt.u64.u32 %rd142, %r112; // convert an unsigned 32-bit integer to 64-bit
Line 16: Line 16:


There are predicate registers, but compiled code in shader model 1.0 uses these only in conjunction with branch commands; the conditional branch is
There are predicate registers, but compiled code in shader model 1.0 uses these only in conjunction with branch commands; the conditional branch is
<syntaxhighlight lang="asm">
<syntaxhighlight lang="ptx">
@%p14 bra $label; // branch to $label
@%p14 bra $label; // branch to $label
</syntaxhighlight>
</syntaxhighlight>


The <code>setp.cc.type</code> instruction sets a predicate register to the result of comparing two registers of appropriate type, there is also a <code>set</code> instruction, where <syntaxhighlight lang="asm" inline>set.le.u32.u64 %r101, %rd12, %rd28</syntaxhighlight> sets the 32-bit register <code>%r101</code> to <code>0xffffffff</code> if the 64-bit register <code>%rd12</code> is less than or equal to the 64-bit register <code>%rd28</code>. Otherwise <code>%r101</code> is set to <code>0x00000000</code>.
The <code>setp.cc.type</code> instruction sets a predicate register to the result of comparing two registers of appropriate type, there is also a <code>set</code> instruction, where <syntaxhighlight lang="ptx" inline>set.le.u32.u64 %r101, %rd12, %rd28</syntaxhighlight> sets the 32-bit register <code>%r101</code> to <code>0xffffffff</code> if the 64-bit register <code>%rd12</code> is less than or equal to the 64-bit register <code>%rd28</code>. Otherwise <code>%r101</code> is set to <code>0x00000000</code>.


There are a few predefined identifiers that denote pseudoregisters. Among others, <code>%tid, %ntid, %ctaid</code>, and <code>%nctaid</code> contain, respectively, thread indices, block dimensions, block indices, and grid dimensions.<ref name="ptx-isa">{{cite web|url=http://developer.download.nvidia.com/compute/cuda/3_1/toolkit/docs/ptx_isa_2.3.pdf|title=PTX ISA Version 2.3|publisher=}}</ref>
There are a few predefined identifiers that denote pseudoregisters. Among others, <code>%tid, %ntid, %ctaid</code>, and <code>%nctaid</code> contain, respectively, thread indices, block dimensions, block indices, and grid dimensions.<ref name="ptx-isa">{{cite web|url=http://developer.download.nvidia.com/compute/cuda/3_1/toolkit/docs/ptx_isa_2.3.pdf|title=PTX ISA Version 2.3|publisher=}}</ref>
Line 27: Line 27:
Load (<code>ld</code>) and store (<code>st</code>) commands refer to one of several distinct state spaces (memory banks), e.g. <code>ld.param</code>.
Load (<code>ld</code>) and store (<code>st</code>) commands refer to one of several distinct state spaces (memory banks), e.g. <code>ld.param</code>.
There are eight state spaces:<ref name="ptx-isa"/>
There are eight state spaces:<ref name="ptx-isa"/>
* <code>.reg</code> : registers
; <code>.reg</code> : registers
* <code>.sreg</code> : special, read-only, platform-specific registers
; <code>.sreg</code> : special, read-only, platform-specific registers
* <code>.const</code> : shared, read-only memory
; <code>.const</code> : shared, read-only memory
* <code>.global</code> : global memory, shared by all threads
; <code>.global</code> : global memory, shared by all threads
* <code>.local</code> : local memory, private to each thread
; <code>.local</code> : local memory, private to each thread
* <code>.param</code> : parameters passed to the kernel
; <code>.param</code> : parameters passed to the kernel
* <code>.shared</code> : memory shared between threads in a block
; <code>.shared</code> : memory shared between threads in a block
* <code>.tex</code> : global texture memory (deprecated)
; <code>.tex</code> : global texture memory (deprecated)


Shared memory is declared in the PTX file via lines at the start of the form:
Shared memory is declared in the PTX file via lines at the start of the form:
<syntaxhighlight lang="nasm">
<syntaxhighlight lang="ptx">
.shared .align 8 .b8 pbatch_cache[15744]; // define 15,744 bytes, aligned to an 8-byte boundary
.shared .align 8 .b8 pbatch_cache[15744]; // define 15,744 bytes, aligned to an 8-byte boundary
</syntaxhighlight>
</syntaxhighlight>
Line 44: Line 44:
-->
-->


Writing kernels in PTX requires explicitly registering PTX modules via the CUDA Driver API, typically more cumbersome than using the CUDA Runtime API and Nvidia's CUDA compiler, nvcc. The GPU Ocelot project provided an API to register PTX modules alongside CUDA Runtime API kernel invocations, though the GPU Ocelot is no longer actively maintained.<ref>{{cite web|url=https://github.com/gtcasl/gpuocelot|title=GPUOCelot: A dynamic compilation framework for PTX|last=|first=|date=|website=github.com|url-status=live|archive-url=|archive-date=|access-date=}}</ref>
Writing kernels in PTX requires explicitly registering PTX modules via the CUDA Driver API, typically more cumbersome than using the CUDA Runtime API and Nvidia's CUDA compiler, nvcc. The GPU Ocelot project provided an API to register PTX modules alongside CUDA Runtime API kernel invocations, though the GPU Ocelot is no longer actively maintained.<ref>{{cite web|url=https://github.com/gtcasl/gpuocelot|title=GPUOCelot: A dynamic compilation framework for PTX|last=|first=|date=7 November 2022|website=github.com|archive-url=|archive-date=|access-date=}}</ref>


==See also==
==See also==
Line 57: Line 57:


[[Category:Nvidia]]
[[Category:Nvidia]]
[[Category:Instruction set architectures]]

Latest revision as of 12:34, 27 December 2024

Parallel Thread Execution (PTX or NVPTX[1]) is a low-level parallel thread execution virtual machine and instruction set architecture used in Nvidia's Compute Unified Device Architecture (CUDA) programming environment. The Nvidia CUDA Compiler (NVCC) translates code written in CUDA, a C++-like language, into PTX instructions (an assembly language represented as American Standard Code for Information Interchange (ASCII) text), and the graphics driver contains a compiler which translates PTX instructions into executable binary code,[2] which can run on the processing cores of Nvidia graphics processing units (GPUs). The GNU Compiler Collection also has basic ability to generate PTX in the context of OpenMP offloading.[3] Inline PTX assembly can be used in CUDA.[4]

Registers

[edit]

PTX uses an arbitrarily large processor register set; the output from the compiler is almost pure static single-assignment form, with consecutive lines generally referring to consecutive registers. Programs start with declarations of the form 

.reg .u32 %r<335>;            // declare 335 registers %r0, %r1, ..., %r334 of type unsigned 32-bit integer

It is a three-argument assembly language, and almost all instructions explicitly list the data type (in sign and width) on which they operate. Register names are preceded with a % character and constants are literal, e.g.: 

shr.u64 %rd14, %rd12, 32;     // shift right an unsigned 64-bit integer from %rd12 by 32 positions, result in %rd14
cvt.u64.u32 %rd142, %r112;    // convert an unsigned 32-bit integer to 64-bit

There are predicate registers, but compiled code in shader model 1.0 uses these only in conjunction with branch commands; the conditional branch is 

@%p14 bra $label;             // branch to $label

The setp.cc.type instruction sets a predicate register to the result of comparing two registers of appropriate type, there is also a set instruction, where set.le.u32.u64 %r101, %rd12, %rd28 sets the 32-bit register %r101 to 0xffffffff if the 64-bit register %rd12 is less than or equal to the 64-bit register %rd28. Otherwise %r101 is set to 0x00000000.

There are a few predefined identifiers that denote pseudoregisters. Among others, %tid, %ntid, %ctaid, and %nctaid contain, respectively, thread indices, block dimensions, block indices, and grid dimensions.[5]

State spaces

[edit]

Load (ld) and store (st) commands refer to one of several distinct state spaces (memory banks), e.g. ld.param. There are eight state spaces:[5]

.reg
registers
.sreg
special, read-only, platform-specific registers
.const
shared, read-only memory
.global
global memory, shared by all threads
.local
local memory, private to each thread
.param
parameters passed to the kernel
.shared
memory shared between threads in a block
.tex
global texture memory (deprecated)

Shared memory is declared in the PTX file via lines at the start of the form: 

.shared .align 8 .b8 pbatch_cache[15744]; // define 15,744 bytes, aligned to an 8-byte boundary

Writing kernels in PTX requires explicitly registering PTX modules via the CUDA Driver API, typically more cumbersome than using the CUDA Runtime API and Nvidia's CUDA compiler, nvcc. The GPU Ocelot project provided an API to register PTX modules alongside CUDA Runtime API kernel invocations, though the GPU Ocelot is no longer actively maintained.[6]

See also

[edit]

References

[edit]
  1. ^ "User Guide for NVPTX Back-end – LLVM 7 documentation". llvm.org.
  2. ^ "CUDA Binary Utilities". docs.nvidia.com. Retrieved 2019-10-19.
  3. ^ "nvptx". GCC Wiki.
  4. ^ "Inline PTX Assembly in CUDA". docs.nvidia.com. Retrieved 2019-11-03.
  5. ^ a b "PTX ISA Version 2.3" (PDF).
  6. ^ "GPUOCelot: A dynamic compilation framework for PTX". github.com. 7 November 2022.
[edit]
Retrieved from "https://en.wikipedia.org/enwiki/w/index.php?title=Parallel_Thread_Execution&oldid=1265545450"