AMD APU

AMD APU

Release date	2011
Codename	Fusion Desna Ontario Zacate Llano Hondo Trinity Weatherford Richland Kaveri Kabini Temash IGP Wrestler WinterPark BeaverCreek
Models	Desktop E2 Series Desktop A4 Series Desktop A6 Series Desktop A8 Series Desktop A10 Series Notebook A, E and C Series
Cores	2 to 4
Transistors	1,178M 32 nm (Llano) 1,303M 32 nm (Trinity) 1,3M 32 nm (Richland) 2,41M 28 nm (Kaveri)
API support
DirectX	Direct3D 11
OpenCL	1.2
OpenGL	4.1+

The AMD Accelerated Processing Unit, formerly known as Fusion, is a series of microprocessors from AMD designed to act as a CPU and graphics accelerator (GPU) on a single chip.

AMD announced the first generation APUs, Llano for high-performance and Brazos for low-power devices in January 2011. The second-generation Trinity for high-performance and Brazos-2 for low-power devices were announced in June 2012. The third-generation Kaveri for high performance devices was launched in January 2014, while Kabini and Temash for low-power devices were announced in summer 2013.

The Sony PlayStation 4 and Microsoft Xbox One eighth generation video game consoles both use semi-custom third-generation low-power APUs.

History

The AMD Fusion project started in 2006 with the aim of developing a system on a chip that combined a CPU with a GPU on a single die. The acquisition of graphics chipset manufacturer ATI by AMD was a key step toward realising such a vision. The project reportedly required three internal iterations of the Fusion concept to create a product deemed worthy of release. Reasons contributing to the delay of the project include the technical difficulties of combining a CPU and GPU on the same die at a 45 nm process, and conflicting views on what the role of the CPU and GPU should be within the project.

The first generation desktop and laptop APU, codenamed Llano, was announced on January 4, 2011 at the 2011 CES show in Las Vegas and released shortly after. It featured K10 CPU cores and a Radeon HD 6000-series GPU on the same die on the FM1 socket. An APU for low-power devices was announced as the Brazos platform, based on the Bobcat microarchitecture and a Radeon HD 6000-series GPU on the same die.

At a conference in January 2012, corporate fellow Phil Rogers announced that AMD would re-brand the Fusion platform as the Heterogeneous Systems Architecture (HSA), stating that "it's only fitting that the name of this evolving architecture and platform be representative of the entire, technical community that is leading the way in this very important area of technology and programming development." However, it was later revealed that AMD had been the subject of a trademark infringement lawsuit by the Swiss company Arctic, who used the name "Fusion" for a line of power supplies.

The second generation desktop and laptop APU, codenamed Trinity was announced at AMD's Financial Analyst Day 2010 and released in October 2012. It featured Piledriver CPU cores and Radeon HD 7000 Series GPU cores on the FM2 socket. AMD released a new APU based on the Piledriver microarchitecture on March 12, 2013 for Laptops/Mobile and on June 4, 2013 for desktops under the codename Richland. The second generation APU for low-power devices, Brazos 2.0, remained on the Bobcat microarchitecture but integrated a Radeon HD 7000-series GPU core onto the die.

Semi-custom chips were introduced in the Microsoft Xbox One and Sony PlayStation 4 video games consoles.

A third generation of the technology was released on 14 January 2014, featuring greater integration between the CPU and GPU. The desktop and laptop variant is codenamed Kaveri, based on Steamroller architecture, while the low-power variants, codenamed Kabini and Temash, are based on Jaguar architecture.

Heterogeneous System Architecture

Heterogeneous System Architecture (HSA) is a set of features that define a system architecture which intends to facilitate heterogeneous computing, i.e. operation of systems that contain CPUs and other co-processing units, currently GPUs and potentially DSPs or ASICs or some combination of different types of co-processors. The system architecture allows any accelerator, for instance, graphics processor, to operate in the same memory space as the system's CPU.

Heterogeneous System Architecture is being developed by the HSA Foundation, an industry consortium founded by AMD, ARM Holdings, Imagination Technologies, MediaTek, Qualcomm, Samsung and Texas Instruments. Another goal is to ease the programming for such systems.

To be HSA-compliant, processors must meet certain requirements, including:

• the ability to access pageable system memory
• the ability to share pointers to make zero-copy memory operations possible
• the ability to maintain cache coherency for system memory with CPUs, and so on.

Heterogeneous systems are widely used in mobile devices, because it allows for a much more power efficient computing. HSA allows programs to use the graphics processor for floating point calculations without separate memory or scheduling.

HSA, for interoperability and to ease various aspects of programming:

• is ISA-agnostic for both CPUs and accelerators
• supports high-level programming languages

So far, the HSA specifications describe:

• HSA Intermediate Layer (HSAIL)
  • virtual instruction set for parallel programs
  • similar to LLVM IR and OpenCL SPIR
  • finalized to a specific instruction set by a JIT compiler
  • make late decisions on which core(s) should run a task
  • explicitly parallel
  • supports exceptions, virtual functions and other high-level features
  • syscall methods (I/O, printf, etc.)
  • debugging support
• HSA memory model
  • compatible with C++11, OpenCL, Java and .NET memory models
  • relaxed consistency
  • designed to support both managed languages (e.g. Java) and unmanaged languages (e.g. C)
  • will make it much easier to develop 3rd party compilers for a wide range of heterogeneous products programmed in Fotran, C++, C++ AMP, Java, et al.
• HSA dispatcher and run-time
  • designed to enable heterogeneous task queueing: a work queue per core, distribution of work into queues, load balancing by work stealing
  • any core can schedule work for any other, including itself
  • significant reduction of overhead of scheduling work for a core

AMD HSA implementation

Type	HSA Feature	First Implemented	Notes
Optimized Platform	GPU Compute C++ Support	2012 Trinity APUs	Support OpenCL C++ directions and Microsoft’s C++ AMP language extension. This eases programming of both CPU and GPU working together to process support parallel workloads.
	HSA-aware MMU		GPU can access the entire system memory through the translation services and page fault management of the HSA MMU.
	Shared Power Management		CPU and GPU now share the power budget. Priority goes to the processor most suited to the current tasks.
Architectural Integration	Unified Address Space for CPU and GPU	2014 PlayStation 4, Kaveri APUs	CPU and GPU now access the memory with the same address space. Pointers can now be freely passed between CPU and GPU.
	Fully coherent memory between CPU & GPU		GPU can now access and cache data from coherent memory regions in the system memory, and also reference the data from CPU's cache. Cache coherency is maintained.
	GPU uses pageable system memory via CPU pointers		GPU can take advantage of the shared virtual memory between CPU and GPU, and pageable system memory can now be referenced directly by the GPU, instead of being copied or pinned before accessing.
System Integration	GPU compute context switch	2015 Carrizo APU	Compute tasks on GPU can be context switched, allowing a multi-tasking environment and also faster interpretation between applications, compute and graphics.
	GPU graphics pre-emption		Long-running graphics tasks can be pre-empted so processes have low latency access to the GPU.
	Quality of Service		In addition to context switch and pre-emption, hardware resources can be either equalized or prioritized among multiple users and applications.

APU-branded platforms

AMD APUs have a unique architecture: they have AMD CPU modules, cache, and a discrete-class graphics processor all on the same die, using the same bus. This architecture allows for the use of graphics accelerators, such as OpenCL, with the integrated graphics processor. The goal is to create a "fully integrated" APU, which, according to AMD will eventually feature 'heterogeneous cores' capable of processing both CPU and GPU work automatically, depending on the workload requirement.

Llano (2011)

• "Stars" (K10) CPU cores
• Integrated Evergreen/VLIW5-based GPU (branded Radeon HD 6000 Series)
• Northbridge
• PCIe
• DDR3 memory controller to arbitrate between coherent and non-coherent memory requests. The physical memory is partitioned between the GPU (up to 512 MB) and the CPU (the remainder).
• UVD
• Display Controller

The first generation APU, released in June 2011, was used in both desktops and laptops. It was based on the K10 architecture and built on a 32 nm process featuring two to four CPU cores on a TDP of 65-100 W, and integrated graphics based on the Radeon HD6000 Series with support for DirectX 11, OpenGL 4.2 and OpenCL 1.2. In performance comparisons against the similarly priced Intel Core i3-2105, the Llano APU was criticised for its poor CPU performance and praised for its better GPU performance. AMD was also criticised for abandoning Socket FM1 after one generation.

Bobcat architecture (2011): Ontario, Zacate, Desna, Hondo

Main article: Bobcat (microarchitecture)

• Bobcat CPU
• Integrated Evergreen/VLIW5-based GPU (branded Radeon HD 6000 Series and Radeon HD 7000 Series)
• Northbridge
• PCIe support.
• DDR3 memory controller to arbitrate between coherent and non-coherent memory requests. The physical memory is partitioned between the GPU (up to 512 MB) and the CPU (the remainder).
• UVD
• Display Controller

The AMD Brazos platform was introduced on January 4, 2011 targeting the subnotebook, netbook and low power small form factor markets. It features the 9-watt AMD C-Series APU (codename: Ontario) for netbooks and low power devices as well as the 18-watt AMD E-Series APU (codename: Zacate) for mainstream and value notebooks, all-in-ones and small form factor desktops. Both APUs feature one or two Bobcat x86 cores and a Radeon Evergreen Series GPU with full DirectX11, DirectCompute and OpenCL support including UVD3 video acceleration for HD video including 1080p.

AMD expanded the Brazos platform on June 5, 2011 with the announcement of the 5.9-watt AMD Z-Series APU (codename: Desna) designed for the Tablet market. The Desna APU is based on the 9-watt Ontario APU, energy savings were achieved by lowering the CPU, GPU and north bridge voltages, reducing the idle clocks of the CPU and GPU as well as introducing a hardware thermal control mode. A bidirectional turbo core mode was also introduced.

AMD announced the Brazos-T platform on October 9, 2012. It comprises the 4.5-watt AMD Z-Series APU (codename: Hondo) and the A55T Fusion Controller Hub (FCH), designed for the tablet computer market. The Hondo APU is a redesign of the Desna APU. AMD lowered energy use by optimizing the APU and FCH for tablet computers.

The Deccan platform including Krishna and Wichita APUs were cancelled in 2011. AMD originally planned to release them in the second half 2012.

Piledriver architecture (2012): Trinity and Richland

• Piledriver CPU cores
• On-die Northern Islands/VLIW4-based GPU (branded Radeon HD 7000 and 8000 Series)
• Unified Northbridge includes AMD Turbo Core 3.0, which enables automatic bi-directional power management between CPU modules and GPU. Power to the CPU and GPU is controlled automatically by changing the clock rate depending on the load. For example, for a non-overclocked A10-5800K APU the CPU frequency can change from 1.4 GHz to 4.2 GHz, and the GPU frequency can change from 304 MHz to 800 MHz. In addition, CC6 mode is capable of powering down individual CPU cores, while PC6 mode is able to lower the power on the entire rail."
• AMD HD Media Accelerator - includes AMD Perfect Picture HD, AMD Quick Stream technology, and AMD Steady Video technology.
• HDMI, DisplayPort 1.2, DVI Controllers

Trinity

The first iteration of the second generation platform, released in October 2012, brought improvements to CPU and GPU performance to both desktops and laptops. The platform features 2 to 4 Piledriver CPU cores built on a 32 nm process with a TDP between 65 W and 100 W, and a GPU based on the Radeon HD7000 Series with support for DirectX 11, OpenGL 4.2, and OpenCL 1.2. The Trinity APU was praised for the improvements to CPU performance compared to the Llano APU.

Richland

• "Enhanced Piledriver" CPU cores
• Temperature Smart Turbo Core technology. An advancement of the existing Turbo Core technology, which allows internal software to adjust the CPU and GPU clock speed to maximise performance within the constrains of the Thermal design power of the APU.
• New low-power consumption CPUs with only 45 W TDP

The release of this second iteration of this generation was 12 March 2013 for mobile parts and 5 June 2013 for desktop parts.

Jaguar architecture (2013): Kabini and Temash

Main article: Jaguar (microarchitecture)

• Jaguar CPU cores
• AMD Radeon R3 graphics
• Socket AM1 support

In January 2013 the Jaguar-based Kabini and Temash APUs were unveiled as the successors of the Bobcat-based Ontario, Zacate and Hondo APUs. The Kabini APU is aimed at the low-power, subnotebook, netbook, ultra-thin and small form factor markets, the Temash APU is aimed at the tablet, ultra-low power and small form factor markets. The two to four Jaguar cores of the Kabini and Temash APUs feature numerous architectural improvements regarding power requirement and performance, such as support for newer x86-instructions, a higher IPC count, a CC6 power state mode and clock gating. Kabini and Temash are AMD's first, and also the first ever quad-core x86 based SoCs. The integrated Fusion Controller Hubs (FCH) for Kabini and Temash are codenamed "Yangtze" and "Salton" respectively. The Yangtze FCH features support for two USB 3.0 ports, two SATA 6 Gbit/s ports, as well as the xHCI 1.0 and SD/SDIO 3.0 protocols for SD-card support. Both chips feature DirectX 11.1-compliant GCN-based graphics as well as numerous heterogeneous system architecture (HSA) improvements. They were fabricated at a 28 nm process in an FT3 BGA package by TSMC, and were released on May 23, 2013.

The PlayStation 4 and Xbox One, were revealed to both be powered by 8-core semi-custom Jaguar-derived APUs.

ARM server SoCs (2013): Seattle

A Cortex-A57-based 64-bit server solution SoC will be launched in the second half of 2014 and codenamed "Seattle". They will feature 8 or 16 core variants, with an expected clockspeed over 2 GHz, and will reportedly deliver up to four times the performance of current Opteron X processors. These ARM processors will incorporate SeaMicro freedom fabric on die, offering up to 10 Gbit/s bandwidth, for server usage; additionally, each ARM processor will support up to 64 GB DRAM.

Steamroller architecture (2014): Kaveri

• 2-4 Steamroller CPU cores
• On-die AMD Radeon R7 graphics with 384-512 GPU cores
• Socket FM2+

The third generation of the platform, codenamed Kaveri, was partly released on January 14, 2014. Kaveri contains up to four Steamroller CPU cores clocked to 3.7 GHz with a turbo mode of 4 GHz, up to a 512-core Graphics Core Next GPU, two decode units per module instead of one (which allows each core to decode four instructions per cycle instead of two), AMD TrueAudio, Mantle, an on-chip ARM Cortex-A5 MPCore, and will release with a new socket, FM2+. Ian Cutress and Rahul Garg of Anandtech asserted that Kaveri represented the unified system-on-a-chip realisation of AMD's acquisition of ATI. The performance of the 45W A8-7600 Kaveri APU was found to be similar to that of the 100W Richland part, leading to the claim that AMD made significant improvements in on-die graphics peformance per watt; however, CPU performance was found to lag behind similarly-specified Intel processors, a lag that was unlikely to be resolved in the Bullzdozer family APUs. The A8-7600 component was delayed from a Q1 launch to an H1 launch because the Steamroller architecture components are alleged to not scale well at higher clock speeds.

Puma architecture (2014): Beema and Mullins

Main article: Puma (microarchitecture)

• Puma CPU cores
• AMD Radeon R4 graphics (800 MHz over the 600 MHz of R3 graphics)
• Socket AM1 support

See also

• AMD Bulldozer
• AMD mobile platform
• List of AMD Accelerated Processing Unit microprocessors
• List of AMD mobile microprocessors
• Radeon
• Unified Video Decoder

External links

• AMD Fusion Family official website
• HSA Heterogeneous System Architecture Overview on YouTube by Vinod Tipparaju at SC13 in November 2013
• HSA and the software ecosystem
• HSA