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'''QsNet''' is a high speed interconnect designed by [[Quadrics]] used in [[HPC]] [[Computer cluster|clusters]], particularly Linux [[Beowulf (computing)|Beowulf Clusters]]. Although it can be used with TCP/IP; like [[SCI]], [[Myrinet]] and [[Infiniband]] it is usually used with a communication [[API]] such as [[Message_Passing_Interface|MPI]] or [[Shmem|SHMEM]] called from a [[Parallel_computing|parallel program]]. |
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The interconnect consists of a PCI card in each compute node and one or more a dedicated switch chasses. These are connected with a copper cables. Within the switch chassis are a number of line cards that carry ''Elite'' switch [[ASIC]]s. These are internally linked to form a [[Fat tree|fat tree]] topology. Like other interconnects such as [[Myrinet]] very large systems can be build by using multiple switch chasses arranged as spine (top-level) and leaf (node-level) switches. Such systems are usually called [[FederatedNetworks|federated networks]]. |
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As of 2003, there are two generations of QsNet. The older QsNetI was launched in 1998 and used PCI 66-64 cards that had 'elan3' Custom ASIC on them. These gave an MPI bandwitdh of around 350MByte/s unidirectional with 5us latency. [[QsNet II]] was launched in 2003. It used [[PCI-X]] 133MHz cards that carry 'elan4' ASICs. These give an MPI bandwitdh of 912MByte/s and MPI latency of 1.26 us, performance depends on platform used. |
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In 2004 Quadrics started releasing small to medium switch stand-alone switch configurations called QsNetII E-Series, these configurations range from the 8 to the 128-way systems. |
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==External links== |
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* [http://www.quadrics.com Quadrics website] |
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* [http://doc.quadrics.com/Quadrics/QuadricsHome.nsf/DisplayPages/3A912204F260613680256DD9005122C7 Quadrics QsNet Page] |
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* [http://doc.quadrics.com/Quadrics/QuadricsHome.nsf/DisplayPages/476637E138359A1C80256E6A0059B85B Quadrics 8-way] |
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Latest revision as of 00:35, 2 July 2020
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