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The West Bridge is a growing new architectural approach which enhances and modularizes a peripheral controller in an embedded computer architecture. Conceptually, the West Bridge parallels and complements the decentralization represented by the [[North Bridge]] and the [[South Bridge]].
The '''West Bridge''' is a growing architectural approach, originally developed by [[Cypress Semiconductor]], which enhances and modularizes a peripheral controller in an embedded computer architecture. Conceptually, the West Bridge parallels and complements the decentralization represented by the [[Northbridge (computing)|North Bridge]] and the [[Southbridge (computing)|South Bridge]]. Most notably, it has been used by [[Research in Motion]] to permit extremely high data transfer rates in its [[BlackBerry]] devices.<ref name="EEtimes">[http://www.eetimes.com/showArticle.jhtml?articleID=203101718 EETimes - Under the Hood: Blackberry Wins Handset Data-Rate Bakeoff]</ref>


==Overview==
==Overview==
While the North Bridge focuses on memory control and the South Bridge focuses on "slower" capabilities of the motherboard, the West Bridge focuses on peripheral control. The new architectural modularization opens the potential for increased system performance. Being directly connected, peripheral control can be handled wholly and independently through a West Bridge's controller, leaving a processor offloaded and free to focus on other data intensive operations. Not only in increasing performance of the system via the processor, a West Bridge companion chip may itself serve directly as a peripheral accelerator.
While the North Bridge focuses on memory control and the South Bridge focuses on the "slower" capabilities of the motherboard, the West Bridge focuses on peripheral control. The new architectural modularization opens up the potential for increased system performance. Being directly connected, peripheral control can be handled wholly and independently through a West Bridge controller, leaving a processor offloaded and free to focus on other data-intensive operations. While it enhances the system's performance via the processor, a West Bridge companion chip may also serve directly as a peripheral accelerator.



==Etymology==
==Etymology==
The term West Bridge was first introduced by [[Cypress Semiconductor]], which designs products to provide optimal performance and connectivity in the embedded world. The name was chosen deliberately to be a meme consistent with the North Bridge and South Bridge concepts. "West Bridge" refers both to the architectural scheme in general and to the product family with which it was introduced, by Cypress.
The term West Bridge was first introduced by [[Cypress Semiconductor]], which designs products to provide optimal performance and connectivity in the embedded world. The name was chosen deliberately to be a [[meme]] consistent with the North Bridge and South Bridge concepts. "West Bridge" refers both to the architectural scheme in general and to the product family with which it was introduced by Cypress.


<gallery>
File:WestBridgeLogo.png
</gallery>


== Interface Support ==
== Interface Support ==


Interfaces change all the time towards faster, lower power, fewer pins, newer standards, making it a difficult task for processors to follow and integrate them. A prime function of Cypress West Bridge devices is to enable connection to these varied interfaces.
Interfaces continually change towards faster, lower power, fewer pins, and newer standards, making it challenging for processors to follow and integrate them. A prime function of West Bridge devices is to enable connection to these varied interfaces.


An example of such an interface is NAND Flash, which keeps evolving with new generations of Multi-Level Cell NAND. A West Bridge device might handle the MLC NAND management and enable lowest-cost memory support for a main processor, which otherwise would only support NOR or Single-Level Cell NAND.
An example of such an interface is [[Flash memory#NAND flash|NAND Flash]], which keeps evolving with new generations of Multi-Level Cell NAND. A West Bridge device might handle the MLC NAND management and enable lowest-cost memory support for a main processor, which otherwise would only support NOR or Single-Level Cell NAND.


Some commonly supported interfaces of West Bridge companion chips are:
Some commonly supported interfaces of West Bridge companion chips are:
* Mass storage
** GPIO
** MMC+
** SD v1.1
** SD v2.0
** SDIO
** CE-ATA
** MLC NAND
** SLC NAND
** Full NAND management
* Processor
** SRAM
** SPI
** ADMUX
** NAND
** NOR
* USB
** USB 2.0 at 480&nbsp;Mbit/s


== Applications ==
*Mass storage
The West Bridge architecture is relevant to a broad range of applications.
**GPIO
**MMC+
**SD v1.1
**SD v2.0
**SDIO
**CE-ATA
**MLC NAND
**SLC NAND
**Full NAND Management


Common applications include:
*Processor
* Handsets
**SRAM
* Portable media players
**SPI
* Personal digital assistants
**ADMUX
* Portable navigation devices
**NAND
* Digital cameras
**NOR
* Printers
* Point-of-sale terminals
* Set-top boxes
* Security dongles


== References ==
*USB
<references/>
**USB 2.0 at 480Mbps


== External links ==
* [http://www.embedded.com/rss/showArticle.jhtml?articleID=199903260&pgno=2 Embedded.com - West Bridge-arrive at improved high-speed USB in multimedia handset design]
* [http://edageek.com/2007/12/10/cypress-cywb0124ab/ EdaGeek.com - Cypress West Bridge Antioch Controller Ranks First in Benchmarks]


== Applications ==
Common applications that would benefit from West Bridge product include Handsets, Portable Media Players, Personal Digital Assistants, Portable Navigation Devices, Digital Cameras, Printers, and Point-of-sale terminals.


[[Category:Motherboard]]
[[Category:Computer peripherals]]
[[Category:Embedded systems]]


== Products ==
* Antioch<sup>TM</sup> - Ultra-low power peripheral controller
* Astoria<sup>TM</sup> - Multimedia mass storage controller for embedded applications
* MoBL-USB FX2LP18<sup>TM</sup> - Ultra-low Power Programmable MCU
* MoBL-USB TX3LP18<sup>TM</sup> - World's smallest High-Speed ULPI transceiver.
* MoBL-USB TX2<sup>TM</sup> - High-Speed UTMI transceiver, with the lowest standby (suspend) current in the industry
* MoBL Dual-Port<sup>TM</sup> and MoBL ADM Dual-Port<sup>TM</sup> - Ultra fast and low power connection between multiple processors

== External links ==
*[http://www.cypress.com/westbridge/ West Bridge<sup>TM</sup> Official Site]
*[http://www.embedded.com/rss/showArticle.jhtml?articleID=199903260&pgno=2 Embedded.com - West Bridge-arrive at improved high-speed USB in multimedia handset design]
*[http://edageek.com/2007/12/10/cypress-cywb0124ab/ Cypress's West Bridge Antioch Controller Ranks First in Benchmarks]
*[http://www10.edacafe.com/nbc/articles/view_article.php?articleid=437403 Cypress Introduces World's Smallest USB Transceiver to Conserve Board Space in Mobile Handsets]

[[Category:Computer hardware]]


{{Compu-hardware-stub}}
{{Comp-hardware-stub}}

Latest revision as of 01:51, 26 April 2024

The West Bridge is a growing architectural approach, originally developed by Cypress Semiconductor, which enhances and modularizes a peripheral controller in an embedded computer architecture. Conceptually, the West Bridge parallels and complements the decentralization represented by the North Bridge and the South Bridge. Most notably, it has been used by Research in Motion to permit extremely high data transfer rates in its BlackBerry devices.[1]

Overview

[edit]

While the North Bridge focuses on memory control and the South Bridge focuses on the "slower" capabilities of the motherboard, the West Bridge focuses on peripheral control. The new architectural modularization opens up the potential for increased system performance. Being directly connected, peripheral control can be handled wholly and independently through a West Bridge controller, leaving a processor offloaded and free to focus on other data-intensive operations. While it enhances the system's performance via the processor, a West Bridge companion chip may also serve directly as a peripheral accelerator.

Etymology

[edit]

The term West Bridge was first introduced by Cypress Semiconductor, which designs products to provide optimal performance and connectivity in the embedded world. The name was chosen deliberately to be a meme consistent with the North Bridge and South Bridge concepts. "West Bridge" refers both to the architectural scheme in general and to the product family with which it was introduced by Cypress.

Interface Support

[edit]

Interfaces continually change towards faster, lower power, fewer pins, and newer standards, making it challenging for processors to follow and integrate them. A prime function of West Bridge devices is to enable connection to these varied interfaces.

An example of such an interface is NAND Flash, which keeps evolving with new generations of Multi-Level Cell NAND. A West Bridge device might handle the MLC NAND management and enable lowest-cost memory support for a main processor, which otherwise would only support NOR or Single-Level Cell NAND.

Some commonly supported interfaces of West Bridge companion chips are:

  • Mass storage
    • GPIO
    • MMC+
    • SD v1.1
    • SD v2.0
    • SDIO
    • CE-ATA
    • MLC NAND
    • SLC NAND
    • Full NAND management
  • Processor
    • SRAM
    • SPI
    • ADMUX
    • NAND
    • NOR
  • USB
    • USB 2.0 at 480 Mbit/s

Applications

[edit]

The West Bridge architecture is relevant to a broad range of applications.

Common applications include:

  • Handsets
  • Portable media players
  • Personal digital assistants
  • Portable navigation devices
  • Digital cameras
  • Printers
  • Point-of-sale terminals
  • Set-top boxes
  • Security dongles

References

[edit]
[edit]