Jump to content

Multi-chip module: Difference between revisions

From Wikipedia, the free encyclopedia
Browse history interactively
← Previous editNext edit →
Content deleted Content added
VisualWikitext
→top: ce
Line 6: Line 6:
Rao Tummala, Solid State Technology. “[http://electroiq.com/blog/2006/07/soc-vs-mcm-vs-sip-vs-sop/ SoC vs. MCM vs SiP vs. SoP].” Retrieved August 4, 2015.
Rao Tummala, Solid State Technology. “[http://electroiq.com/blog/2006/07/soc-vs-mcm-vs-sip-vs-sop/ SoC vs. MCM vs SiP vs. SoP].” Retrieved August 4, 2015.
</ref>
</ref>
Other terms, such as "hybrid" or "[[hybrid integrated circuit]]", also refer to MCMs. The individual ICs that make up an MCM are known as '''chiplets'''.<ref>{{Cite web|url=https://en.wikichip.org/wiki/chiplet|title=Chiplet - WikiChip|website=en.wikichip.org}}</ref> Intel and AMD are using MCMs to improve performance and reduce costs, as splitting a large monolithic IC into smaller chiplets allows for easy performance improvements (easily allows for more transistors split across multiple chiplets), more ICs per wafer, and improved [[Semiconductor device fabrication#Device test|yield]], as smaller dies have a reduced risk of getting destroyed by process variations during [[semiconductor fabrication]]. This approach also allows for chiplets to be reused in several products, reduces the amount of time required to design a module compared to designing a monolithic IC, and also reduces the number of bugs that have to be solved during design. However, communication between chiplets consumes more power and has higher latency than components in monolithic ICs.<ref>https://www.anandtech.com/show/16021/intel-moving-to-chiplets-client-20-for-7nm</ref> Each chiplet is physically smaller than a conventional monolithic IC die, (A monolithic IC is an [[IC package]] with a single die that performs all functions).<ref>{{Cite journal|url=https://www.wired.com/story/keep-pace-moores-law-chipmakers-turn-chiplets/|title=To Keep Pace With Moore's Law, Chipmakers Turn to 'Chiplets'|journal=Wired|first=Tom|last=Simonite|date=November 6, 2018|via=www.wired.com}}</ref><ref>{{Cite web|url=https://www.engadget.com/2019/04/16/upscaled-cpu-chiplet/|title=Upscaled: This is the year of the CPU 'chiplet'|website=Engadget}}</ref> An example of MCMs in use for mainstream CPUs is [[AMD]]'s [[Zen 2]] design.
Other terms, such as "hybrid" or "[[hybrid integrated circuit]]", also refer to MCMs. The individual ICs that make up an MCM are known as '''chiplets'''.<ref>{{Cite web|url=https://en.wikichip.org/wiki/chiplet|title=Chiplet - WikiChip|website=en.wikichip.org}}</ref> Intel and AMD are using MCMs to improve performance and reduce costs, as splitting a large monolithic IC into smaller chiplets allows for easy performance improvements (easily allows for more transistors split across multiple chiplets), more ICs per wafer, and improved [[Semiconductor device fabrication#Device test|yield]], as smaller dies have a reduced risk of getting destroyed by process variations during [[semiconductor fabrication]]. This approach also allows for chiplets to be reused in several products, reduces the amount of time required to design a module compared to designing a monolithic IC, and also reduces the number of bugs that have to be solved during design. However, communication between chiplets consumes more power and has higher latency than components in monolithic ICs.<ref>https://www.anandtech.com/show/16021/intel-moving-to-chiplets-client-20-for-7nm</ref> Each chiplet is physically smaller than a conventional monolithic IC die - a monolithic IC is an [[IC package]] with a single die that performs all functions.<ref>{{Cite journal|url=https://www.wired.com/story/keep-pace-moores-law-chipmakers-turn-chiplets/|title=To Keep Pace With Moore's Law, Chipmakers Turn to 'Chiplets'|journal=Wired|first=Tom|last=Simonite|date=November 6, 2018|via=www.wired.com}}</ref><ref>{{Cite web|url=https://www.engadget.com/2019/04/16/upscaled-cpu-chiplet/|title=Upscaled: This is the year of the CPU 'chiplet'|website=Engadget}}</ref> An example of MCMs in use for mainstream CPUs is [[AMD]]'s [[Zen 2]] design.


==Overview==
==Overview==

Revision as of 09:22, 14 April 2021

A ceramic multi-chip module containing four POWER5 processor dies (center) and four 36 MB L3 cache dies (periphery).

A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or "pins") where multiple integrated circuits (ICs or "chips"), semiconductor dies and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC.[1] Other terms, such as "hybrid" or "hybrid integrated circuit", also refer to MCMs. The individual ICs that make up an MCM are known as chiplets.[2] Intel and AMD are using MCMs to improve performance and reduce costs, as splitting a large monolithic IC into smaller chiplets allows for easy performance improvements (easily allows for more transistors split across multiple chiplets), more ICs per wafer, and improved yield, as smaller dies have a reduced risk of getting destroyed by process variations during semiconductor fabrication. This approach also allows for chiplets to be reused in several products, reduces the amount of time required to design a module compared to designing a monolithic IC, and also reduces the number of bugs that have to be solved during design. However, communication between chiplets consumes more power and has higher latency than components in monolithic ICs.[3] Each chiplet is physically smaller than a conventional monolithic IC die - a monolithic IC is an IC package with a single die that performs all functions.[4][5] An example of MCMs in use for mainstream CPUs is AMD's Zen 2 design.

Overview

Multi-chip modules come in a variety of forms depending on the complexity and development philosophies of their designers. These can range from using pre-packaged ICs on a small printed circuit board (PCB) meant to mimic the package footprint of an existing chip package to fully custom chip packages integrating many chip dies on a high density interconnection (HDI) substrate.

Multi-Chip Module packaging is an important facet of modern electronic miniaturization and micro-electronic systems. MCMs are classified according to the technology used to create the HDI substrate.

  • MCM-L – laminated MCM. The substrate is a multi-layer laminated printed circuit board (PCB, used in AMD's Zen 2 processors).
  • MCM-D – deposited MCM. The modules are deposited on the base substrate using thin film technology.
  • MCM-C – ceramic substrate MCMs, such as low temperature co-fired ceramic (LTCC)

The PCB that interconnects the chiplets is known as an interposer. This is often either organic or is made of silicon (as in High Bandwidth Memory)[6] Both have their advantages and limitations. Using interposers to connect several chiplets instead of connecting several monolithic ICs in separate packages reduces the power needed to transmit signals between chiplets, increases the amount of transmission channels, and reduces delays caused by resistance/capacitance (RC delays).[7]

Chiplets are often attached to interposers using flip chip.

Chip stack MCMs

Wireless NoC on 3D integrated circuit

A relatively new development in MCM technology is the so-called "chip-stack" package.[8] Certain ICs, memories in particular, have very similar or identical pinouts when used multiple times within systems. A carefully designed substrate can allow these dies to be stacked in a vertical configuration making the resultant MCM's footprint much smaller (albeit at the cost of a thicker or taller chip). Since area is more often at a premium in miniature electronics designs, the chip-stack is an attractive option in many applications such as cell phones and personal digital assistants (PDAs). With the use of a 3D integrated circuit and a thinning process, as many as ten dies can be stacked to create a high capacity SD memory card.[9] This technique can also be used for High Bandwidth Memory.

The possible way to increasing the performance of data transfer in the Chip stack is use Wireless Networks on Chip (WiNoC).[10]

Examples of multi-chip packages

3D multi-chip modules

Main articles: 3D integrated circuit and Package on package

See also

References

  1. ^ Rao Tummala, Solid State Technology. “SoC vs. MCM vs SiP vs. SoP.” Retrieved August 4, 2015.
  2. ^ "Chiplet - WikiChip". en.wikichip.org.
  3. ^ https://www.anandtech.com/show/16021/intel-moving-to-chiplets-client-20-for-7nm
  4. ^ Simonite, Tom (November 6, 2018). "To Keep Pace With Moore's Law, Chipmakers Turn to 'Chiplets'". Wired – via www.wired.com.
  5. ^ "Upscaled: This is the year of the CPU 'chiplet'". Engadget.
  6. ^ https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/2-5d-ic/
  7. ^ https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/2-5d-ic/interposers/
  8. ^ Jon Worrel (15 April 2012). "Intel migrates to desktop Multi-Chip Modules (MCMs) with 14nm Broadwell". Fudzilla.
  9. ^ Richard Chirgwin, The Register. “Memory vendors pile on '3D' stacking standard.” April 2, 2013. February 5, 2016.
  10. ^ Slyusar V. I., Slyusar D.V. Pyramidal design of nanoantennas array. // VIII International Conference on Antenna Theory and Techniques (ICATT’11). - Kyiv, Ukraine. - National Technical University of Ukraine “Kyiv Polytechnic Institute”. - September 20–23, 2011. - Pp. 140 - 142. [1]
  11. ^ Ghoshal, U.; Van Duzer, T. (1992). "High-performance MCM interconnection circuits and fluxoelectronics". Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92. pp. 175–178. doi:10.1109/MCMC.1992.201478. ISBN 0-8186-2725-5.
  12. ^ Burns, M. J.; Char, K.; Cole, B. F.; Ruby, W. S.; Sachtjen, S. A. (1993). "Multichip module using multilayer YBa2Cu3O7−δinterconnects". Applied Physics Letters. 62 (12): 1435–1437. Bibcode:1993ApPhL..62.1435B. doi:10.1063/1.108652.
  13. ^ Satoru Iwata, Iwata Asks. “Changes in Television.” Retrieved August 4, 2015.
  14. ^ Shimpi, Anand Lal. "VIA's QuadCore: Nano Gets Bigger". www.anandtech.com. Retrieved 2020-04-10.
  15. ^ "MCP (Multichip Package) | Samsung Semiconductor". www.samsung.com.
  16. ^ "NAND based MCP | Samsung Memory Link". samsung.com.
  17. ^ "e-MMC based MCP | Samsung Memory Link". samsung.com.
  18. ^ Cutress, Ian. "The AMD Ryzen Threadripper 1950X and 1920X Review: CPUs on Steroids". www.anandtech.com. Retrieved 2020-04-10.
  19. ^ Lilly, Paul (2019-12-17). "AMD Ryzen Threadripper 3960X, 3970X Meet Scalpel For Zen 2 Delidding Operation". HotHardware. Retrieved 2020-04-10.
  20. ^ Cutress, Ian. "AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome". www.anandtech.com. Retrieved 2020-04-10.
Retrieved from "https://en.wikipedia.org/enwiki/w/index.php?title=Multi-chip_module&oldid=1017731424"