Jump to content

Xenos (graphics chip): Difference between revisions

From Wikipedia, the free encyclopedia
Content deleted Content added
Rubones (talk | contribs)
Undid revision 1059627526 by Triang3l (talk)
Tags: Undo Mobile edit Mobile web edit Advanced mobile edit
Rubones (talk | contribs)
Undid revision 1059623317 by Triang3l (talk)
Tags: Undo Mobile edit Mobile web edit Advanced mobile edit
Line 2: Line 2:
[[Image:Ic-photo-ATI--(X-BOX 360-GPU).jpg|thumb|Xbox 360 GPU]]
[[Image:Ic-photo-ATI--(X-BOX 360-GPU).jpg|thumb|Xbox 360 GPU]]
<!-- Image with inadequate rationale removed: [[Image:R500gpu.jpg|200px|thumb|Xbox 360 GPU; note the smaller eDRAM [[Integrated circuit|die]] to the left of the main Xenos die]] -->
<!-- Image with inadequate rationale removed: [[Image:R500gpu.jpg|200px|thumb|Xbox 360 GPU; note the smaller eDRAM [[Integrated circuit|die]] to the left of the main Xenos die]] -->
The '''Xenos''' is a custom [[graphics processing unit]] (GPU) designed by [[ATI Technologies|ATI]] (now taken over by [[Advanced Micro Devices|AMD]]), used in the [[Xbox 360]] [[video game console]] developed and produced for [[Microsoft]]. Developed under the codename "C1",<ref name=Beyond3D>{{cite web | url=http://www.beyond3d.com/content/articles/4/| title=ATI Xenos: Xbox 360 Graphics Demystified | author=Wavey Dave Baumann | publisher=Beyond3D | access-date=2006-04-11}}</ref> it is based on the R400 "Crayola" architecture,<ref>{{cite web |title=Ex. 2050 - R400 Document Library FH - folder_history (PROTECTIVE ORDER) — IPR2015-00325 - LG Electronics, Inc. v. ATI Technologies ULC |url=https://portal.unifiedpatents.com/ptab/case/IPR2015-00325 |website=Unified Patents |access-date=10 December 2021 |date=9 September 2015}}</ref> which is used exclusively in the Xenos after the cancellation of the plans to produce [[Radeon]] graphics cards based on it in favor of a modification of the earlier [[Radeon R300 series|R300]] architecture used in the [[Radeon R400 series]], as well as the [[Radeon X1000 series|R500]] architecture.<ref>{{cite web |title=ATI R400 |url=http://endian.net/details.aspx?tag=atir400 |website=endian.net |archive-url=http://web.archive.org/web/20070928002223/http://endian.net/details.aspx?tag=atir400 |archive-date=28 September 2007 |url-status=dead}}</ref> The Xenos introduced new design ideas that were later adopted in the [[TeraScale (microarchitecture)|TeraScale microarchitecture]], such as the [[unified shader architecture]], and is the base for the [[Qualcomm]] [[Adreno]] 200 mobile GPU, initially called the AMD Z430.<ref name="Z430">{{cite web |title=AMD Receives Next-Generation OpenGL ES 2.0 Graphics Technology Certification |url=https://www.techpowerup.com/62693/amd-receives-next-generation-opengl-es-2-0-graphics-technology-certification |website=TechPowerUp |access-date=10 December 2021 |date=11 June 2008}}</ref> The package contains two separate [[Die (integrated circuit)|dies]], the GPU and an [[eDRAM]] (manufactured by [[NEC]]), featuring a total of 337 million transistors.
The '''Xenos''' is a custom [[graphics processing unit]] (GPU) designed by [[ATI Technologies|ATI]] (now taken over by [[Advanced Micro Devices|AMD]]), used in the [[Xbox 360]] [[video game console]] developed and produced for [[Microsoft]]. Developed under the codename "C1",<ref name=Beyond3D>{{cite web | url=http://www.beyond3d.com/content/articles/4/| title=ATI Xenos: Xbox 360 Graphics Demystified | author=Wavey Dave Baumann | publisher=Beyond3D | access-date=2006-04-11}}</ref> it is in many ways related to the [[Radeon R520|R520]] architecture and therefore very similar to an ATI [[Radeon X1800 XT]]{{dubious|date=June 2020}}{{citation needed|date=June 2020}} series of PC [[graphics card]]s as far as features and performance are concerned. However, the Xenos introduced new design ideas that were later adopted in the [[TeraScale (microarchitecture)|TeraScale microarchitecture]], such as the [[unified shader architecture]]. The package contains two separate [[Die (integrated circuit)|dies]], the GPU and an [[eDRAM]] (manufactured by [[NEC]]), featuring a total of 337 million transistors.


==Specifications==
==Specifications==
The shader units are organized in three [[SIMD]] groups with 16 processors per group, for a total of 48 processors. Each of these processors is composed of a 5-wide vector unit (total 5 FP32 [[Arithmetic logic unit|ALUs]]), resulting in 240 units, that can serially execute up to two instructions per cycle (a multiply and an addition). All processors in a SIMD group execute the same instruction, so in total up to three instruction threads can be simultaneously under execution.
The chip is based on [[TeraScale (microarchitecture)|TeraScale microarchitecture]], the shader units are organized in three [[SIMD]] groups with 16 processors per group, for a total of 48 processors. Each of these processors is composed of a 5-wide vector unit (total 5 FP32 [[Arithmetic logic unit|ALUs]]), resulting in 240 units, that can serially execute up to two instructions per cycle (a multiply and an addition). All processors in a SIMD group execute the same instruction, so in total up to three instruction threads can be simultaneously under execution.


* 500&nbsp;MHz parent GPU on [[90 nanometer|90 nm]], [[65 nanometer|65 nm]] (since 2008) [[TSMC]] process or [[45 nanometer|45nm]] [[GlobalFoundries]] process (since 2010, with [[Xenon (processor)|CPU]] on same die) of total 232 million transistors
* 500&nbsp;MHz parent GPU on [[90 nanometer|90 nm]], [[65 nanometer|65 nm]] (since 2008) [[TSMC]] process or [[45 nanometer|45nm]] [[GlobalFoundries]] process (since 2010, with [[Xenon (processor)|CPU]] on same die) of total 232 million transistors
Line 38: Line 38:
* [[TeraScale (microarchitecture)#Hardware tessellation|TeraScale hardware tesselator]]
* [[TeraScale (microarchitecture)#Hardware tessellation|TeraScale hardware tesselator]]
* [[Graphics Core Next#Geometric processor|GCN hardware tesselator]]
* [[Graphics Core Next#Geometric processor|GCN hardware tesselator]]
* [[RSX 'Reality Synthesizer']] [[Graphics processing unit|GPU]] used in the [[PlayStation 3]]
* [[RSX 'Reality Synthesizer']] - [[Graphics processing unit|GPU]] used in the [[PlayStation 3]]
* [[Latte (graphics chip)]] GPU used in the [[Wii U]]
* [[Latte (graphics chip)]] [[Graphics processing unit|GPU]] used in the [[Wii U]]
* [[Adreno]] 200 — the mobile GPU produced by Qualcomm, initially named the AMD Z430, based on the Xenos<ref name="Z430" />


==References==
==References==

Revision as of 20:21, 22 December 2021

Xbox 360 GPU

The Xenos is a custom graphics processing unit (GPU) designed by ATI (now taken over by AMD), used in the Xbox 360 video game console developed and produced for Microsoft. Developed under the codename "C1",[1] it is in many ways related to the R520 architecture and therefore very similar to an ATI Radeon X1800 XT[dubiousdiscuss][citation needed] series of PC graphics cards as far as features and performance are concerned. However, the Xenos introduced new design ideas that were later adopted in the TeraScale microarchitecture, such as the unified shader architecture. The package contains two separate dies, the GPU and an eDRAM (manufactured by NEC), featuring a total of 337 million transistors.

Specifications

The chip is based on TeraScale microarchitecture, the shader units are organized in three SIMD groups with 16 processors per group, for a total of 48 processors. Each of these processors is composed of a 5-wide vector unit (total 5 FP32 ALUs), resulting in 240 units, that can serially execute up to two instructions per cycle (a multiply and an addition). All processors in a SIMD group execute the same instruction, so in total up to three instruction threads can be simultaneously under execution.

  • 500 MHz parent GPU on 90 nm, 65 nm (since 2008) TSMC process or 45nm GlobalFoundries process (since 2010, with CPU on same die) of total 232 million transistors
    • 240 vector units floating-point vector processors for shader execution, divided in three dynamically scheduled SIMD groups of 80 units each.[2]
      • Unified shading architecture (each pipeline is capable of running either pixel or vertex shaders)
      • 10 FP ops per vector processor per cycle (5 fused multiply-add)
      • Maximum vertex count: 1.21 Billion vertices per second 
      • Maximum polygon count: ~500 million polygons per second
      • Maximum shader operations: 240 billion shader operations per second (3 shader pipelines × 80 units × 2 ALUs × 0.5 GHz (500 MHz) )
      • 240 GFLOPS
      • MEMEXPORT shader function
    • 16 texture filtering units (TF) and 16 texture addressing units (TA)
      • 16 filtered samples per clock
        • Maximum pixel fillrate: 4.00 GPixel/s
        • Maximum texel fillrate: 8 gigatexels per second (16 textures × 500 MHz)
      • 16 unfiltered texture samples per clock
    • Maximum dot product operations: 24 billion per second
    • Support for a superset of DirectX 9.0c API DirectX Xbox 360, and Shader Model 3.0+
  • 500 MHz, 10 MB daughter embedded DRAM (at 256Gbit/s) framebuffer on 90 nm, 80 nm (since 2008 [3]) or 65nm (since 2010 [4]).
    • NEC designed eDRAM die includes additional logic (192 parallel pixel processors) for color, alpha compositing, alpha blending, Z/stencil buffering, and anti-aliasing called "Intelligent Memory", giving developers 4-sample anti-aliasing at very little performance cost.
    • Procedural Synthesis Technology(XPS): During read streaming into the CPU, a custom prefetch instruction, extended data cache block touch (xDCBT) prefetches data directly to the L1 data cache of the intended core, which skips putting the data in the L2 cache to avoid thrashing the L2 cache. Writes streaming from each core skip the L1 cache, due to its no-write allocation (avoids thrashing of high-bandwidth, transient, write-only data streams on the L1 cache), and goes directly to the L2 cache. The system allows for the GPU to directly read data produced by the CPU without going to main memory. In this specific case of data streaming, called Xbox procedural synthesis (XPS), the CPU is effectively a data decompressor, generating geometry on-the-fly for consumption by the GPU 3D core.
    • 105 million transistors [5]
    • 8 render output units
      • Maximum pixel fillrate: 16 gigasamples per second fillrate using 4X multisample anti aliasing (MSAA), or 32 gigasamples using Z-only operation; 4 gigapixels per second without MSAA (8 ROPs × 500 MHz)
      • Maximum Z sample rate: 8 gigasamples per second (2 Z samples × 8 ROPs × 500 MHz), 32 gigasamples per second using 4X anti aliasing (2 Z samples × 8 ROPs × 4X AA × 500 MHz)[1]
      • Maximum anti-aliasing sample rate: 16 gigasamples per second (4 AA samples × 8 ROPs × 500 MHz)[1]
      • Support for bilinear, trilinear, anisotropic filtering, Alpha to Coverage, hardware Tessellation and Predicated Tiling.[6]
  • Cooling: Both the GPU and CPU of the console have heatsinks. The GPU's heatsink uses heatpipe technology, to conduct heat from the GPU and eDRAM die to the fins of the heatsink. The heatsinks are actively cooled by a pair of 60 mm exhaust fans. The new XCGPU chipset redesign is featured in both the Xbox 360 S and the Xbox 360 E and integrates the CPU (Xenon) and GPU (Xenos) in one package and is actively cooled by a single heatsink rather than two.

See also

References

  1. ^ a b c Wavey Dave Baumann. "ATI Xenos: Xbox 360 Graphics Demystified". Beyond3D. Retrieved 2006-04-11.
  2. ^ Xbox 360 hardware specifications Archived August 22, 2008, at the Wayback Machine
  3. ^ "Welcome to Valhalla - Inside the New 250GB XBox 360 Slim". Anandtech.
  4. ^ "Tech Report: A Look At The EDRAM On Valhalla". Image Quality Matters.
  5. ^ ATI engineers by way of Beyond 3D's Dave Baumann.
  6. ^ https://msdn.microsoft.com/en-us/library/bb464139.aspx