Multi-chip module: Difference between revisions
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The possible way to increasing the performance of data transfer in the Chip stack is use Wireless [[Network on a chip|Networks on Chip]] (WiNoC).<ref>Slyusar V. I., Slyusar D.V. Pyramidal design of nanoantennas array. // VIII International Conference on Antenna Theory and Techniques (ICATT’11). - Kyiv, Ukraine. - National Technical University of Ukraine “Kyiv Polytechnic Institute”. - September 20–23, 2011. - Pp. 140 - 142. [https://slyusar.kiev.ua/ICATT_2011_Slyusar2.pdf]</ref> |
The possible way to increasing the performance of data transfer in the Chip stack is use Wireless [[Network on a chip|Networks on Chip]] (WiNoC).<ref>Slyusar V. I., Slyusar D.V. Pyramidal design of nanoantennas array. // VIII International Conference on Antenna Theory and Techniques (ICATT’11). - Kyiv, Ukraine. - National Technical University of Ukraine “Kyiv Polytechnic Institute”. - September 20–23, 2011. - Pp. 140 - 142. [https://slyusar.kiev.ua/ICATT_2011_Slyusar2.pdf]</ref> |
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==Examples of multi-chip packages== |
== Examples of multi-chip packages == |
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*[[IBM]] [[Bubble memory]] MCMs (1970s) |
* [[IBM]] [[Bubble memory]] MCMs (1970s) |
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*[[IBM 3081]] mainframe's thermal conduction module (1980s) |
* [[IBM 3081]] mainframe's thermal conduction module (1980s) |
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*Superconducting Multichip modules (1990s)<ref>{{Cite book |doi = 10.1109/MCMC.1992.201478|isbn = 0-8186-2725-5|chapter = High-performance MCM interconnection circuits and fluxoelectronics|title = Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92|year = 1992|last1 = Ghoshal|first1 = U.|last2 = Van Duzer|first2 = T.|pages = 175–178|s2cid = 109329843}}</ref><ref>{{Cite journal |doi = 10.1063/1.108652|bibcode = 1993ApPhL..62.1435B|title = Multichip module using multilayer YBa2Cu3O7−δinterconnects|year = 1993|last1 = Burns|first1 = M. J.|last2 = Char|first2 = K.|last3 = Cole|first3 = B. F.|last4 = Ruby|first4 = W. S.|last5 = Sachtjen|first5 = S. A.|journal = Applied Physics Letters|volume = 62|issue = 12|pages = 1435–1437}}</ref> |
* Superconducting Multichip modules (1990s)<ref>{{Cite book |doi = 10.1109/MCMC.1992.201478|isbn = 0-8186-2725-5|chapter = High-performance MCM interconnection circuits and fluxoelectronics|title = Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92|year = 1992|last1 = Ghoshal|first1 = U.|last2 = Van Duzer|first2 = T.|pages = 175–178|s2cid = 109329843}}</ref><ref>{{Cite journal |doi = 10.1063/1.108652|bibcode = 1993ApPhL..62.1435B|title = Multichip module using multilayer YBa2Cu3O7−δinterconnects|year = 1993|last1 = Burns|first1 = M. J.|last2 = Char|first2 = K.|last3 = Cole|first3 = B. F.|last4 = Ruby|first4 = W. S.|last5 = Sachtjen|first5 = S. A.|journal = Applied Physics Letters|volume = 62|issue = 12|pages = 1435–1437}}</ref> |
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*[[Intel]] [[Pentium Pro]], [[Pentium II OverDrive]], [[Pentium D]] Presler, [[Xeon]] Dempsey, Clovertown, Harpertown and Tigerton, [[Core 2 Quad]] (Kentsfield, Penryn-QC and Yorkfield), [[Clarkdale (microprocessor)|Clarkdale]], [[Arrandale]], [[Kaby Lake-G]], and models with [[Crystalwell]] (those with the GT3e or GT4e graphics) |
* [[Intel]] [[Pentium Pro]], [[Pentium II OverDrive]], [[Pentium D]] Presler, [[Xeon]] Dempsey, Clovertown, Harpertown and Tigerton, [[Core 2 Quad]] (Kentsfield, Penryn-QC and Yorkfield), [[Clarkdale (microprocessor)|Clarkdale]], [[Arrandale]], [[Kaby Lake-G]], and models with [[Crystalwell]] (those with the GT3e or GT4e graphics) |
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*[[SD card|Micro-SD cards]] and [[Sony]] [[Memory Stick|memory stick]]s |
* [[SD card|Micro-SD cards]] and [[Sony]] [[Memory Stick|memory stick]]s |
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*[[Xenos (graphics chip)|Xenos]], a [[Graphics processing unit|GPU]] designed by [[ATI Technologies]] for the [[Xbox 360]], with [[eDRAM]] |
* [[Xenos (graphics chip)|Xenos]], a [[Graphics processing unit|GPU]] designed by [[ATI Technologies]] for the [[Xbox 360]], with [[eDRAM]] |
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*[[POWER2]], [[POWER4]], [[POWER5]], [[POWER7]], [[POWER8]], and [[Power10]] from [[IBM]] |
* [[POWER2]], [[POWER4]], [[POWER5]], [[POWER7]], [[POWER8]], and [[Power10]] from [[IBM]] |
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*[[IBM z196]] |
* [[IBM z196]] |
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*Nintendo's [[Wii U]] [[Espresso (microprocessor)]] has its CPU, [[GPU]], and onboard VRAM (integrated into the GPU) on one MCM.<ref>Satoru Iwata, Iwata Asks. “[http://iwataasks.nintendo.com/interviews/#/wiiu/console/0/0 Changes in Television].” Retrieved August 4, 2015.</ref> |
* Nintendo's [[Wii U]] [[Espresso (microprocessor)]] has its CPU, [[GPU]], and onboard VRAM (integrated into the GPU) on one MCM.<ref>Satoru Iwata, Iwata Asks. “[http://iwataasks.nintendo.com/interviews/#/wiiu/console/0/0 Changes in Television].” Retrieved August 4, 2015.</ref> |
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*[[VIA Nano]] QuadCore<ref>{{cite web|url=https://www.anandtech.com/show/4332/vias-quadcore-nano-gets-bigger|title=VIA's QuadCore: Nano Gets Bigger|last=Shimpi|first=Anand Lal|website=www.anandtech.com|access-date=2020-04-10}}</ref> |
* [[VIA Nano]] QuadCore<ref>{{cite web|url=https://www.anandtech.com/show/4332/vias-quadcore-nano-gets-bigger|title=VIA's QuadCore: Nano Gets Bigger|last=Shimpi|first=Anand Lal|website=www.anandtech.com|access-date=2020-04-10}}</ref> |
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*Flash and RAM memory combined on a [[Package on package|PoP]] by [[Micron Technology|Micron]] |
* Flash and RAM memory combined on a [[Package on package|PoP]] by [[Micron Technology|Micron]] |
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*[[Samsung]] MCP solutions combining mobile [[DRAM]] and [[NAND flash|NAND]] storage.<ref>{{cite web|title=MCP (Multichip Package) |
* [[Samsung]] MCP solutions combining mobile [[DRAM]] and [[NAND flash|NAND]] storage.<ref>{{cite web|title=MCP (Multichip Package) | Samsung Semiconductor|url=http://www.samsung.com/semiconductor/mcp/|website=www.samsung.com|language=en}}</ref><ref>{{cite web|title=NAND based MCP | Samsung Memory Link|url=https://memorylink.samsung.com/ecomobile/mem/ecomobile/product/productOverview.do?topMenu=P&subMenu=mcp&partSetNo=MCP&partSetLabel=NAND%20based%20MCP|website=samsung.com}}</ref><ref>{{cite web|title=e-MMC based MCP | Samsung Memory Link|url=https://memorylink.samsung.com/ecomobile/mem/ecomobile/product/productOverview.do?topMenu=P&subMenu=mcp&partSetNo=eMCP&partSetLabel=e-MMC%20based%20MCP|website=samsung.com}}</ref> |
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*AMD [[Ryzen Threadripper]] and [[Epyc]] CPUs based on [[Zen (microarchitecture)|Zen]] or [[Zen+]] architecture are MCMs of two or four chips<ref>{{cite web|url=https://www.anandtech.com/show/11697/the-amd-ryzen-threadripper-1950x-and-1920x-review|title=The AMD Ryzen Threadripper 1950X and 1920X Review: CPUs on Steroids|last=Cutress|first=Ian|website=www.anandtech.com|access-date=2020-04-10}}</ref> ([[Ryzen]] based on Zen or Zen+ is not MCM and consist of one chip) |
* AMD [[Ryzen|Ryzen Threadripper]] and [[Epyc]] CPUs based on [[Zen (microarchitecture)|Zen]] or [[Zen+]] architecture are MCMs of two or four chips<ref>{{cite web|url=https://www.anandtech.com/show/11697/the-amd-ryzen-threadripper-1950x-and-1920x-review|title=The AMD Ryzen Threadripper 1950X and 1920X Review: CPUs on Steroids|last=Cutress|first=Ian|website=www.anandtech.com|access-date=2020-04-10}}</ref> ([[Ryzen]] based on Zen or Zen+ is not MCM and consist of one chip) |
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*AMD's non-[[AMD Accelerated Processing Unit|APU]] [[Ryzen]], Ryzen Threadripper and Epyc CPUs based on the [[Zen 2]] or [[Zen 3]] architecture are MCMs of one, two, four<ref>{{cite web|url=https://hothardware.com/news/amd-ryzen-threadripper-3960x-3970x-zen-2-delidding|title=AMD Ryzen Threadripper 3960X, 3970X Meet Scalpel For Zen 2 Delidding Operation|last=Lilly|first=Paul|date=2019-12-17|website=HotHardware|language=en-us|access-date=2020-04-10}}</ref> or eight chips containing CPU cores and one bigger I/O chip<ref>{{cite web|url=https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome|title=AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome|last=Cutress|first=Ian|website=www.anandtech.com|access-date=2020-04-10}}</ref> |
* AMD's non-[[AMD Accelerated Processing Unit|APU]] [[Ryzen]], Ryzen Threadripper and Epyc CPUs based on the [[Zen 2]] or [[Zen 3]] architecture are MCMs of one, two, four<ref>{{cite web|url=https://hothardware.com/news/amd-ryzen-threadripper-3960x-3970x-zen-2-delidding|title=AMD Ryzen Threadripper 3960X, 3970X Meet Scalpel For Zen 2 Delidding Operation|last=Lilly|first=Paul|date=2019-12-17|website=HotHardware|language=en-us|access-date=2020-04-10}}</ref> or eight chips containing CPU cores and one bigger I/O chip<ref>{{cite web|url=https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome|title=AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome|last=Cutress|first=Ian|website=www.anandtech.com|access-date=2020-04-10}}</ref> |
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* [[AMD Instinct]] MI series GPUs based on [[CDNA (microarchitecture)#CDNA 2|CDNA 2]] architecture are MCMs of one or two graphics compute die (GCD) chips. |
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*[[AMD RDNA 3]] GPUs |
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* AMD [[Radeon RX 7000 series]] GPUs based on [[RDNA (microarchitecture)#RDNA 3|RDNA 3]] architecture are MCMs with one GCD and up to six memory cache die (MCD) chips. |
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*[[Radeon Instinct|AMD Radeon Instinct MI200 series]] GPUs |
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*[[Intel Xe#Ponte Vecchio|Intel Xe Ponte Vecchio]] GPUs |
* [[Intel Xe#Ponte Vecchio|Intel Xe Ponte Vecchio]] GPUs |
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*Any other processor with [[High Bandwidth Memory]] |
* Any other processor with [[High Bandwidth Memory]] |
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==3D multi-chip modules== |
==3D multi-chip modules== |
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Revision as of 14:42, 6 November 2022
 | This article needs additional citations for verification. (June 2013) |
A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or "pins") where multiple integrated circuits (ICs or "chips"), semiconductor dies and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC.[1] Other terms for MCM packaging include "heterogeneous integration" or "hybrid integrated circuit".[2] The advantage of using MCM packaging is it allows a manufacturer to use multiple components for modularity and/or to improve yields over a conventional monolithic IC approach.
Overview
Multi-chip modules come in a variety of forms depending on the complexity and development philosophies of their designers. These can range from using pre-packaged ICs on a small printed circuit board (PCB) meant to mimic the package footprint of an existing chip package to fully custom chip packages integrating many chip dies on a high density interconnection (HDI) substrate. The final assembled MCM substrate may be done in one of the following ways:
- The substrate is a multi-layer laminated printed circuit board (PCB), such as those used in AMD's Zen 2 processors.
- The substrate is built on ceramic, such as low temperature co-fired ceramic
- The ICs are deposited on the base substrate using Thin Film technology.
The ICs that make up the MCM package may be:
- ICs that can perform most, if not all of the functions of a component of a computer, such as the CPU. Examples of this include implementations of IBM's POWER5 and Intel's Core 2 Quad. Multiple copies of the same IC are used to build the final product. In the case of POWER5, multiple POWER5 processors and their associated off-die L3 cache are used to build the final package. With the Core 2 Quad, effectively two Core 2 Duo dies were packaged together.
- ICs that perform only some of the functions, or "Intellectual Property Blocks" ("IP Blocks"), of a component in a computer. These are known as chiplets.[3][4] An example of this are the processing ICs and I/O IC of AMD's Zen 2-based processors.
The PCB that interconnects the ICs is known as an interposer. This is often either organic (a laminated circuit board, which contains carbon, hence organic) or is made of silicon (as in High Bandwidth Memory)[5] Both have their advantages and limitations. Using interposers to connect several ICs instead of connecting several monolithic ICs in separate packages reduces the power needed to transmit signals between ICs, increases the amount of transmission channels, and reduces delays caused by resistance/capacitance (RC delays).[6] However, communication between chiplets consumes more power and has higher latency than components in monolithic ICs.[7]
Chip stack MCMs
.PNG)
A relatively new development in MCM technology is the so-called "chip-stack" package.[8] Certain ICs, memories in particular, have very similar or identical pinouts when used multiple times within systems. A carefully designed substrate can allow these dies to be stacked in a vertical configuration making the resultant MCM's footprint much smaller (albeit at the cost of a thicker or taller chip). Since area is more often at a premium in miniature electronics designs, the chip-stack is an attractive option in many applications such as cell phones and personal digital assistants (PDAs). With the use of a 3D integrated circuit and a thinning process, as many as ten dies can be stacked to create a high capacity SD memory card.[9] This technique can also be used for High Bandwidth Memory.
The possible way to increasing the performance of data transfer in the Chip stack is use Wireless Networks on Chip (WiNoC).[10]
Examples of multi-chip packages
- IBM Bubble memory MCMs (1970s)
- IBM 3081 mainframe's thermal conduction module (1980s)
- Superconducting Multichip modules (1990s)[11][12]
- Intel Pentium Pro, Pentium II OverDrive, Pentium D Presler, Xeon Dempsey, Clovertown, Harpertown and Tigerton, Core 2 Quad (Kentsfield, Penryn-QC and Yorkfield), Clarkdale, Arrandale, Kaby Lake-G, and models with Crystalwell (those with the GT3e or GT4e graphics)
- Micro-SD cards and Sony memory sticks
- Xenos, a GPU designed by ATI Technologies for the Xbox 360, with eDRAM
- POWER2, POWER4, POWER5, POWER7, POWER8, and Power10 from IBM
- IBM z196
- Nintendo's Wii U Espresso (microprocessor) has its CPU, GPU, and onboard VRAM (integrated into the GPU) on one MCM.[13]
- VIA Nano QuadCore[14]
- Flash and RAM memory combined on a PoP by Micron
- Samsung MCP solutions combining mobile DRAM and NAND storage.[15][16][17]
- AMD Ryzen Threadripper and Epyc CPUs based on Zen or Zen+ architecture are MCMs of two or four chips[18] (Ryzen based on Zen or Zen+ is not MCM and consist of one chip)
- AMD's non-APU Ryzen, Ryzen Threadripper and Epyc CPUs based on the Zen 2 or Zen 3 architecture are MCMs of one, two, four[19] or eight chips containing CPU cores and one bigger I/O chip[20]
- AMD Instinct MI series GPUs based on CDNA 2 architecture are MCMs of one or two graphics compute die (GCD) chips.
- AMD Radeon RX 7000 series GPUs based on RDNA 3 architecture are MCMs with one GCD and up to six memory cache die (MCD) chips.
- Intel Xe Ponte Vecchio GPUs
- Any other processor with High Bandwidth Memory
3D multi-chip modules
See also
- System in package (SIP)
- System on a chip (SoC)
- Hybrid integrated circuit
- Chip carrier Chip packaging and package types list
- Single Chip Module (SCM)
- UFS Multi Chip Package (uMCP)
References
- ^ Rao Tummala, Solid State Technology. "SoC vs. MCM vs SiP vs. SoP", Retrieved August 4, 2015.
- ^ Don Scansen, EE Times "Chiplets: A Short History Retrieved 26 April, 2021
- ^ Samuel K. Moore, IEEE Spectrum "Intel's View of the Chiplet Revolution" Retrieved 26 April, 2021
- ^ Semi Engineering "Chiplets" Retrieved 26 April, 2021
- ^ "2.5D - Semiconductor Engineering". Semiengineering.com. Retrieved 2022-05-13.
- ^ "Interposers".
- ^ Dr. Ian Cutress, AnandTech "Intel Moving to Chiplets: 'Client 2.0' for 7nm"
- ^ Jon Worrel (15 April 2012). "Intel migrates to desktop Multi-Chip Modules (MCMs) with 14nm Broadwell". Fudzilla.
- ^ Richard Chirgwin, The Register. “Memory vendors pile on '3D' stacking standard.” April 2, 2013. February 5, 2016.
- ^ Slyusar V. I., Slyusar D.V. Pyramidal design of nanoantennas array. // VIII International Conference on Antenna Theory and Techniques (ICATT’11). - Kyiv, Ukraine. - National Technical University of Ukraine “Kyiv Polytechnic Institute”. - September 20–23, 2011. - Pp. 140 - 142. [1]
- ^ Ghoshal, U.; Van Duzer, T. (1992). "High-performance MCM interconnection circuits and fluxoelectronics". Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92. pp. 175–178. doi:10.1109/MCMC.1992.201478. ISBN 0-8186-2725-5. S2CID 109329843.
- ^ Burns, M. J.; Char, K.; Cole, B. F.; Ruby, W. S.; Sachtjen, S. A. (1993). "Multichip module using multilayer YBa2Cu3O7−δinterconnects". Applied Physics Letters. 62 (12): 1435–1437. Bibcode:1993ApPhL..62.1435B. doi:10.1063/1.108652.
- ^ Satoru Iwata, Iwata Asks. “Changes in Television.” Retrieved August 4, 2015.
- ^ Shimpi, Anand Lal. "VIA's QuadCore: Nano Gets Bigger". www.anandtech.com. Retrieved 2020-04-10.
- ^ "MCP (Multichip Package) | Samsung Semiconductor". www.samsung.com.
- ^ "NAND based MCP | Samsung Memory Link". samsung.com.
- ^ "e-MMC based MCP | Samsung Memory Link". samsung.com.
- ^ Cutress, Ian. "The AMD Ryzen Threadripper 1950X and 1920X Review: CPUs on Steroids". www.anandtech.com. Retrieved 2020-04-10.
- ^ Lilly, Paul (2019-12-17). "AMD Ryzen Threadripper 3960X, 3970X Meet Scalpel For Zen 2 Delidding Operation". HotHardware. Retrieved 2020-04-10.
- ^ Cutress, Ian. "AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome". www.anandtech.com. Retrieved 2020-04-10.
