Zero register: Difference between revisions
Changed example from MIPS to the more common ARM64 today |
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Zero appears as a constant in many instructions, notably "branch if zero", and optimizing these instructions can have a positive benefit on performance. Some architectures accomplish this with dedicated [[opcode]]s, specialized variations of their basic instructions. Implementing these requires additional logic in the [[instruction decoder]]. The zero register can accomplish the same effect without requiring new opcodes, although at the cost of dedicating a register to this feature, which may have negative impact for architectures with limited number of registers. |
Zero appears as a constant in many instructions, notably "branch if zero", and optimizing these instructions can have a positive benefit on performance. Some architectures accomplish this with dedicated [[opcode]]s, specialized variations of their basic instructions. Implementing these requires additional logic in the [[instruction decoder]]. The zero register can accomplish the same effect without requiring new opcodes, although at the cost of dedicating a register to this feature, which may have negative impact for architectures with limited number of registers. |
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The [[x86]] architecture has no zero register, [[ARM architecture family|ARM]] added a zero register for ARM64. The [[RISC-V]] architecture includes one with the register name "x0" and the ABI name "zero |
The [[x86]] architecture has no zero register, [[ARM architecture family|ARM]] added a zero register for ARM64. The [[RISC-V]] architecture includes one with the register name "x0" and the ABI name "zero"; the reason for this inclusion is stated as "Dedicating a register to zero is surprisingly a large factor in simplifying the RISC-V ISA."<ref>{{Cite book |last=Patterson |first=David |title=The RISC-V Reader: An Open Architecture Atlas |edition=Beta Ed., 0.0.1 |page=18}}</ref> |
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==References== |
==References== |
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Revision as of 01:07, 8 February 2024
A zero register is a processor register that always returns the value zero and has no effect when it is written to. It is found in instruction set architectures including the CDC 6600, System/360 and ARM64, among others.
Zero appears as a constant in many instructions, notably "branch if zero", and optimizing these instructions can have a positive benefit on performance. Some architectures accomplish this with dedicated opcodes, specialized variations of their basic instructions. Implementing these requires additional logic in the instruction decoder. The zero register can accomplish the same effect without requiring new opcodes, although at the cost of dedicating a register to this feature, which may have negative impact for architectures with limited number of registers.
The x86 architecture has no zero register, ARM added a zero register for ARM64. The RISC-V architecture includes one with the register name "x0" and the ABI name "zero"; the reason for this inclusion is stated as "Dedicating a register to zero is surprisingly a large factor in simplifying the RISC-V ISA."[1]
References
- ^ Patterson, David. The RISC-V Reader: An Open Architecture Atlas (Beta Ed., 0.0.1 ed.). p. 18.
- Mashey, John (8 August 1998). "Top 10 Mistakes in Computer Architecture".
- "RISC-V Spec" (PDF).
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