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Professor Keshab K. Parhi
Born	(1959-06-15) June 15, 1959 Bhadrak, Odisha, India
Citizenship	United States
Awards	IEEE Fellow ACM Fellow AAAS Fellow AIMBE Fellow NAI Fellow IEEE Kiyo Tomiyasu Award
Academic background
Alma mater	IIT Kharagpur (B.Tech.) University of Pennsylvania (M.S.) University of California, Berkeley (Ph.D.)
Thesis	Algorithm and Architecture Design for High-Speed Signal Processing (1988)
Doctoral advisor	David G. Messerschmitt
Academic work
Institutions	University of Minnesota, Twin Cities (UMN)
Doctoral students	https://www.genealogy.math.ndsu.nodak.edu/id.php?id=41741
Main interests	VLSI, Signal Processing, Artifical Intelligence, Data-Driven Neuroscience, DNA Computing
Website	https://www.ece.umn.edu/users/parhi/

Keshab K. Parhi (born (1959-06-15)June 15, 1959 in Bhadrak, Odisha, India) is an Indian-American electrical and computer engineer. He is currently the Erwin A. Kelen Chair in the department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities. His research addresses architecture design of VLSI integrated circuit chips for signal processing, communications, artificial intelligence, and cryptosystems with a focus on reducing latency and increasing speed, while reducing chip area and energy consumption. His research has also addressed data-driven neuroscience and DNA computing.

Career

Parhi received the B. Tech. degree from the Indian Institute of Technology, Kharagpur in 1982, the M.S. degree from the University of Pennsylvania in 1984, and the Ph.D. degree from the University of California, Berkeley in 1988. He joined the department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities in October 1988. He was promoted to Associate Professor with tenure in July 1992 and promoted to full professor in July 1995. During July 1997–June 2022, he held the Edgar F. Johnson Professorship in Electronic Communication. Since July 2022, he holds the Erwin A. Kelen Chair in Electrical Engineering. During July 2008–August 2011, he served as the Director of Graduate Studies of the Electrical Engineering Program.

Research

Parhi’s interdisciplinary research in late 1980s advanced the field of VLSI signal processing by integrating concepts from computer architecture, digital signal processing (DSP), and VLSI design. In particular, he developed algorithm transformations techniques such as unfolding and folding for DSP programs described by iterative data-flow graphs.

His research has led to pipelined-parallel architectures for signal processing operations such as recursive and adaptive digital filters, decision-feedback equalizers, Tomlinson-Harashima precoders, parallel decision-feedback decoders, and fast Fourier transforms. He has developed architectures for modern error control code decoders such as turbo code, low-density parity check code, and polar codes. His research has been deployed in numerous integrated circuit chips for physical layer communications in wired and wireless media that form the backbone of the internet.

His research has led to high-speed architectures for cryptosystems such as the advanced encryption standard, post-quantum cryptography, and homomorphic encryption. He has also developed approaches to obfuscating integrated circuits using keys to prevent sale of excess parts and to protect key parameters of the design. In 1990s, Parhi worked on a DARPA funded project on high-level synthesis that led to the development of the Minnesota Architecture Synthesis System (MARS) for time-constrained and resource-constrained synthesis of data-flow graphs. His research group also developed the HEAT tool to estimate power consumption with circuit-simulation level accuracy with logic-level simulation.

Parhi has authored the text book: VLSI Digital Signal Processing Systems: Design and Implementation (Wiley, 1999). He has coauthored: Pipelined Adaptive Digital Filters (Springer, 1994), Digit-Serial Computation (Springer, 1995), and Pipelined Lattice and Wave Digital Filters (Springer, 1996). He is the Co-editor of the book: Digital Signal Processing for Multimedia Systems (CRC Press, 1999). Parhi has authored over 725 papers and is inventor or co-inventor of 36 issued US patents.

Professional Service

Parhi has served the IEEE for over 35 years in various capacities. He has served as Associate Editor for numerous transactions published by the IEEE Circuits and Systems Society and the IEEE Signal Processing Society. His leadership roles include:

• IEEE Fellow Selection Committee (1998, 1999)
• Editor-in-Chief, IEEE Transactions on Circuits and Systems I: Regular Papers (2004 and 2005)
• Editor-in-Chief, IEEE Circuits and Systems Magazine (2024-present)
• IEEE Circuits and Systems Society Board of Governors (2005-2007 and 2025-present)
• General Chair, IEEE Workshop on Signal Processing Systems (SiPS), 2002
• Technical Program Cochair, VLSI Signal Processing Workshop (1995)
• Technical Program Cochair, Applications-specific Systems, Architectures, and Processors (ASAP), 1996

Distinctions and Awards

• 2022 Charles E. Bowers Faculty Teaching Award, College of Science and Engineering, University of Minnesota

• 2022 Fellow, American Institute for Medical and Biological Engineering, Citation: For outstanding contributions to machine learning approaches for neuropsychiatric and ophthalmic disorders, and to synthesis of molecular computing systems

• 2021 IEEE Circuits and Systems Society John Choma Education Award, Citation: For contributions to VLSI signal processing education

• 2020 Fellow, Association for Computing Machinery, Citation: For contributions to architectures and design tools for signal processing and networking accelerators

• 2020 Fellow, National Academy of Inventors

• 2017 Fellow, American Association for the Advancement of Science

• 2017 IEEE Circuits and Systems Society Mac Valkenburg Award, Citation: For pioneering contributions to VLSI digital signal processing architectures, design methodologies, and their applications to wired and wireless communications, and service to IEEE Circuits and Systems Society

• 2013 Award for Outstanding Contributions to Post Baccalaureate, Graduate and Professional Teaching, University of Minnesota

• 2012 IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award, Citation: For contributions to VLSI architectures and design methodologies for digital signal processing and communications circuits and systems.

• 2004 Frederick Emmons Terman Award from the American Society of Engineering Education, for authoring the text book “VLSI Digital Signal Processing Systems: Design and Implementation” (Wiley, 1999)

• 2003 IEEE Kiyo Tomiyasu Technical Field Award, Citation: For pioneering contributions to high-speed and low-power digital signal processing architectures for broadband communications systems

• 2001 IEEE W.R. Baker Prize Paper Award

• 1996 Fellow, IEEE, Citation: For contributions to the fields of VLSI digital signal processing architectures, design methodologies and tools

• 1992 National Science Foundation Young Investigator Award

• 1991 IEEE Signal Processing Society Young Author Award

• 1991 IEEE Browder J. Thompson Memorial Prize Paper Award

• 1987 Eli Jury Award for Excellence in Systems Research, University of California at Berkeley

• 1987 Demetri Angelakos Award for altruistic activities afforded fellow graduate students, University of California at Berkeley