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</ref> He has developed architectures for modern [[error correction code|error correction encoders/decoders]] including [[turbo codes]],<ref>{{cite journal|last1=Wang|first1=Z.|last2=Chi|first2=Z.|last3=Parhi|first3=K.K.|date=December 2002|title= Area-Efficient High Speed Decoding Schemes for Turbo/MAP Decoders |journal=IEEE Transactions on VLSI Systems|volume=10|issue=12|pages=902-912|doi=10.1109/TVLSI.2002.808451}}
</ref> He has developed architectures for modern [[error correction code|error correction encoders/decoders]] including [[turbo codes]],<ref>{{cite journal|last1=Wang|first1=Z.|last2=Chi|first2=Z.|last3=Parhi|first3=K.K.|date=December 2002|title= Area-Efficient High Speed Decoding Schemes for Turbo/MAP Decoders |journal=IEEE Transactions on VLSI Systems|volume=10|issue=12|pages=902-912|doi=10.1109/TVLSI.2002.808451}}
</ref> [[low-density parity-check codes]],<ref>{{cite journal|last1=Zhang|first1=T.|last2=Parhi|first2=K.K.|date=April 2004|title= Joint (3,k)-regular LDPC Code and Decoder/Encoder Design |journal=IEEE Transactions on Signal Processing|volume=52|issue=4|pages=1065-1079|doi=10.1109/TSP.2004.823508}}
</ref> [[low-density parity-check codes]],<ref>{{cite journal|last1=Zhang|first1=T.|last2=Parhi|first2=K.K.|date=April 2004|title= Joint (3,k)-regular LDPC Code and Decoder/Encoder Design |journal=IEEE Transactions on Signal Processing|volume=52|issue=4|pages=1065-1079|doi=10.1109/TSP.2004.823508}}
</ref> and [[Polar code (coding theory)|polar codes]].<ref>{{cite journal|last1=Yuan|first1=B.|last2=Parhi|first2=K.K.|date=April 2014|title=Low-Latency Successive-Cancellation Polar Decoder Architectures using 2-bit Decoding|journal=IEEE Transactions on Circuits and Systems I: Regular Papers|volume=61|issue=4|pages=1241-1254|doi=10.1109/TCSI.2013.2283779}}
</ref><ref>{{cite journal|last1=Chen|first1=Y.|last2=Parhi|first2=K.K.|date=June 2004|title=Overlapped Message Passing for Quasi-Cyclic Low-Density Parity Check Codes|journal=IEEE Transactions on Circuits and Systems I: Regular Papers|volume=51|issue=6|pages=1106-1113|doi=10.1109/TCSI.2004.826194}}</ref> and [[Polar code (coding theory)|polar codes]].<ref>{{cite journal|last1=Yuan|first1=B.|last2=Parhi|first2=K.K.|date=April 2014|title=Low-Latency Successive-Cancellation Polar Decoder Architectures using 2-bit Decoding|journal=IEEE Transactions on Circuits and Systems I: Regular Papers|volume=61|issue=4|pages=1241-1254|doi=10.1109/TCSI.2013.2283779}}
</ref><ref>{{cite journal|last1=Yuan|first1=B.|last2=Parhi|first2=K.K.|date=December 15, 2014|title=Early Stopping Criteria for Energy-Efficient Low-Latency Belief-Propagation Polar Code Decoders |journal=IEEE Transactions on Circuits and Systems I: Regular Papers|volume=62|issue=24|pages=6496-6506|doi=10.1109/TSP.2014.2366712}}
</ref><ref>{{cite journal|last1=Yuan|first1=B.|last2=Parhi|first2=K.K.|date=December 15, 2014|title=Early Stopping Criteria for Energy-Efficient Low-Latency Belief-Propagation Polar Code Decoders |journal=IEEE Transactions on Circuits and Systems I: Regular Papers|volume=62|issue=24|pages=6496-6506|doi=10.1109/TSP.2014.2366712}}
</ref> His research has been deployed in numerous [[integrated circuit]] chips for [[physical-layer]] [[Telecommunications engineering|communications]] in wired and wireless media that form the backbone of the [[internet]].
</ref> His research has been deployed in numerous [[integrated circuit]] chips for [[physical-layer]] [[Telecommunications engineering|communications]] in wired and wireless media that form the backbone of the [[internet]].

Revision as of 01:16, 28 December 2024

Keshab K. Parhi
Born1959 (1959)
Bhadrak District, Odisha, India
CitizenshipUnited States
Awards
Academic background
Alma mater
ThesisAlgorithm and Architecture Design for High-Speed Signal Processing (1988)
Doctoral advisorDavid G. Messerschmitt
Academic work
InstitutionsUniversity of Minnesota, Twin Cities (UMN)
Doctoral studentshttps://www.genealogy.math.ndsu.nodak.edu/id.php?id=41741
Main interestsVLSI, Signal Processing, Artifical Intelligence, Neural Engineering, DNA Computing
Websitehttps://www.ece.umn.edu/users/parhi/

Keshab K. Parhi (born 1959 (1959) in Bhadrak District, Odisha, India) is an electrical engineer and computer scientist. He is currently the Erwin A. Kelen Chair in the department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities. His research addresses architecture design of VLSI integrated circuit chips for signal processing, communications, artificial intelligence, and cryptosystems with a focus on reducing latency and increasing speed, while also reducing chip area and energy consumption. His research has also addressed neural engineering and DNA computing.[1]

Career

Parhi received the B. Tech. degree from the Indian Institute of Technology, Kharagpur in 1982, the M.S. degree from the University of Pennsylvania in 1984, and the Ph.D. degree from the University of California, Berkeley in 1988. He joined the Department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities in October 1988. He was promoted to Associate Professor with tenure in July 1992 and promoted to full professor in July 1995. From July 1997 to June 2022, he held the Edgar F. Johnson Professorship in Electronic Communication. Since July 2022, he holds the Erwin A. Kelen Chair in Electrical Engineering. From July 2008 to August 2011, he served as the Director of Graduate Studies of the Electrical Engineering Program.[1]

Parhi has been a Visiting Professor at the Delft University of Technology (1996), Lund University (1999), Fudan University (2017), and Stanford University (2018). He has held short-term appointments at IBM T.J. Watson Research Center (1996), Bell Laboratories (1997), NEC C&C Laboratory (1992 and 1996-1997 on a US National Science Foundation-Cooperative Government Program (CGP) Fellowship)[2], Broadcom Corporation (2000-2002), and Medtronic (2006-2007). From 2005 to 2012, he served as Founder, President, and Chief Scientist of Leanics Corporation. Leanics was supported by SBIR funding from the National Science Foundation and the Department of Defense.[1]

Research

Parhi’s interdisciplinary research in late 1980s advanced the field of VLSI signal processing by integrating concepts from computer architecture, digital signal processing (DSP), and VLSI design. In particular, he developed algorithm transformations techniques[3] such as unfolding[4] and folding[5] for DSP programs described by iterative data-flow graphs.

His research has led to pipelined-parallel architectures for signal processing operations such as recursive[6][7] and adaptive[8][9] digital filters, decision-feedback equalizers,[10][11] Tomlinson-Harashima precoders,[12][13] parallel decision-feedback decoders,[14] and fast Fourier transforms.[15][16][17] He has developed architectures for modern error correction encoders/decoders including turbo codes,[18] low-density parity-check codes,[19][20] and polar codes.[21][22] His research has been deployed in numerous integrated circuit chips for physical-layer communications in wired and wireless media that form the backbone of the internet.

His research has led to high-speed architectures for cryptosystems such as the advanced encryption standard (AES),[23] post-quantum cryptography,[24] and homomorphic encryption.[25] He has also developed approaches to obfuscating integrated circuits using keys to prevent the sale of excess parts and to protect key parameters of the design.[26][27] Parhi and his collaborators have developed approaches to obfuscating (encrypting) the functionality of the integrated circuits to prevent intellectual-property piracy and reverse engineering of key design parameters of these circuits. In the 1990s, Parhi worked on a DARPA funded project on high-level synthesis that led to the development of the Minnesota Architecture Synthesis System (MARS) for time-constrained and resource-constrained synthesis of data-flow graphs.[28] His research group also developed the Hierarchical Energy Analysis Tool (HEAT) to estimate power consumption with circuit-simulation-level accuracy from logic-level simulation.[29]

Parhi has authored the text book: VLSI Digital Signal Processing Systems: Design and Implementation (Wiley, 1999). He has coauthored: Pipelined Adaptive Digital Filters (Springer, 1994), Digit-Serial Computation (Springer, 1995), and Pipelined Lattice and Wave Digital Filters (Springer, 1996). He is the Co-editor of the book: Digital Signal Processing for Multimedia Systems (CRC Press, 1999). Parhi has authored over 725 papers and is inventor or co-inventor of 36 issued US patents.

Professional Service

Parhi has served the Institute of Electrical and Electronics Engineers (IEEE) in various capacities. He has served as Associate Editor for numerous transactions published by the IEEE Circuits and Systems Society and the IEEE Signal Processing Society. His leadership roles include:

Distinctions and Awards

  • 2017 IEEE Circuits and Systems Society Mac Van Valkenburg Award, Citation: For pioneering contributions to VLSI digital signal processing architectures, design methodologies, and their applications to wired and wireless communications, and service to IEEE Circuits and Systems Society[36]
  • 2012 IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award, Citation: For contributions to VLSI architectures and design methodologies for digital signal processing and communications circuits and systems.[38]
  • 2004 Frederick Emmons Terman Award from the ]]American Society of Engineering Education]], for authoring the textbook “VLSI Digital Signal Processing Systems: Design and Implementation” (Wiley, 1999)[39]
  • 2003 IEEE Kiyo Tomiyasu Award, Citation: For pioneering contributions to high-speed and low-power digital signal processing architectures for broadband communications systems[40]
  • 1996 Fellow, IEEE, Citation: For contributions to the fields of VLSI digital signal processing architectures, design methodologies and tools[42]

References

  1. ^ a b c "Keshab K. Parhi Homepage". www.ece.umn.edu. Retrieved 26 December 2024.
  2. ^ https://www.nsf.gov/awardsearch/showAward?AWD_ID=9600372
  3. ^ Parhi, K.K. (December 1989). "Algorithm Transformation Techniques for Concurrent Processors". Proceedings of the IEEE. 77 (12): 1879–1895. doi:10.1109/5.48830.
  4. ^ Parhi, K.K.; Messerschmitt, D.G. (February 1991). "Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding". IEEE Transactions on Computers. 40 (2): 178–195. doi:10.1109/12.73588.
  5. ^ Parhi, K.K.; Wang, C.-Y.; Brown, A.P. (January 1992). "Synthesis of Control Circuits in Folded Pipelined DSP Architectures". IEEE Journal of Solid-State Circuits. 27 (1): 29–43. doi:10.1109/4.109555.
  6. ^ Parhi, K.K.; Messerschmitt, D.G. (July 1989). "Pipeline Interleaving and Parallelism in Recursive Digital Filters, Part I: Pipelining using Scattered Look-Ahead and Decomposition". IEEE Transactions on Acoustics, Speech, and Signal Processing. 37 (7): 1099–1117. doi:10.1109/29.32286.
  7. ^ Parhi, K.K.; Messerschmitt, D.G. (July 1989). "Pipeline Interleaving and Parallelism in recursive Digital Filters, Part II: Pipelined Incremental Block Filtering". IEEE Transactions on Acoustics, Speech, and Signal Processing. 37 (7): 1118–1134. doi:10.1109/29.32287.
  8. ^ Parhi, K.K.; Messerschmitt, D.G. (October 1987). "Concurrent Cellular VLSI Adaptive Filter Architectures". IEEE Transactions on Circuits and Systems. 34 (10): 1141–1151. doi:10.1109/TCS.1987.1086048.
  9. ^ Shanbhag, N.R.; Parhi, K.K. (December 1993). "Relaxed Look-Ahead Pipelined LMS Adaptive Filters and Their Application to ADPCM Coder". IEEE Transactions on Circuits and Systems, Part II: Analog and Digital Signal Processing. 40 (12): 753–766. doi:10.1109/82.260240.
  10. ^ Parhi, K.K. (July 1991). "Pipelining in Algorithms with Quantizer Loops". IEEE Transactions on Circuits and Systems. 38 (7): 745–754. doi:10.1109/31.135746.
  11. ^ Parhi, K.K. (April 2005). "Design of Multi-Gigabit Multiplexer Loop Based Decision Feedback Equalizers". IEEE Transactions on VLSI Systems. 13 (4): 489–493. doi:10.1109/TVLSI.2004.842935.
  12. ^ Gu, Y.; Parhi, K.K. (September 2007). "High-Speed Architecture Design of Tomlinson-Harashima Precoders". IEEE Transactions on Circuits and Systems, Part I: Regular Papers. 54 (9): 1929–1937. doi:10.1109/TCSI.2007.904688.
  13. ^ Gu, Y.; Parhi, K.K. (May 2008). "Design of Parallel Tomlinson-Harashima Precoders". IEEE Transactions on Circuits and Systems, Part II: Express Briefs. 55 (5): 447–451. doi:10.1109/TCSII.2007.914435.
  14. ^ Gu, Y.; Parhi, K.K. (February 2007). "Pipelined Parallel Decision Feedback Decoders for High-Speed Ethernet over Copper". IEEE Transactions on Signal Processing. 55 (2): 707–715. doi:10.1109/TSP.2006.885776.
  15. ^ Cheng, C.; Parhi, K.K. (October 2007). "High-Throughput VLSI Architecture for FFT Computation". IEEE Transactions on Circuits and Systems II: Express Briefs. 54 (10): 863–867. doi:10.1109/TCSII.2007.901635.
  16. ^ Ayinala, M.; Brown, M.J.; Parhi, K.K. (June 2012). "Pipelined Parallel FFT Architectures via Folding Transformation". IEEE Transactions on VLSI Systems. 20 (6): 1068–1081. doi:10.1109/TVLSI.2011.2147338.
  17. ^ Parhi, K.K. (April 2024). A Low-Latency FFT-IFFT Cascade Architecture. Proc. of 2024 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). pp. 181–185. doi:10.1109/ICASSP48485.2024.10447370.
  18. ^ Wang, Z.; Chi, Z.; Parhi, K.K. (December 2002). "Area-Efficient High Speed Decoding Schemes for Turbo/MAP Decoders". IEEE Transactions on VLSI Systems. 10 (12): 902–912. doi:10.1109/TVLSI.2002.808451.
  19. ^ Zhang, T.; Parhi, K.K. (April 2004). "Joint (3,k)-regular LDPC Code and Decoder/Encoder Design". IEEE Transactions on Signal Processing. 52 (4): 1065–1079. doi:10.1109/TSP.2004.823508.
  20. ^ Chen, Y.; Parhi, K.K. (June 2004). "Overlapped Message Passing for Quasi-Cyclic Low-Density Parity Check Codes". IEEE Transactions on Circuits and Systems I: Regular Papers. 51 (6): 1106–1113. doi:10.1109/TCSI.2004.826194.
  21. ^ Yuan, B.; Parhi, K.K. (April 2014). "Low-Latency Successive-Cancellation Polar Decoder Architectures using 2-bit Decoding". IEEE Transactions on Circuits and Systems I: Regular Papers. 61 (4): 1241–1254. doi:10.1109/TCSI.2013.2283779.
  22. ^ Yuan, B.; Parhi, K.K. (December 15, 2014). "Early Stopping Criteria for Energy-Efficient Low-Latency Belief-Propagation Polar Code Decoders". IEEE Transactions on Circuits and Systems I: Regular Papers. 62 (24): 6496–6506. doi:10.1109/TSP.2014.2366712.
  23. ^ Zhang, X.; Parhi, K.K. (September 2004). "High-Speed VLSI Architectures for the AES Algorithm". IEEE Transactions on VLSI Systems. 12 (9): 957–967. doi:10.1109/TVLSI.2004.832943.
  24. ^ Tan, W.; Wang, A.; Zhang, X.; Lao, Y.; Parhi, K.K. (September 2023). "High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography". IEEE Transactions on Computers. 72 (9): 2454–2466. doi:10.1109/TC.2023.3251847.
  25. ^ Tan, W.; Chiu, S.-W.; Wang, A.; Lao, Y.; Parhi, K.K. (January 2024). "PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption". IEEE Transactions on Information Forensics and Security. 19: 1646–1659. doi:10.1109/TIFS.2023.3338553.
  26. ^ Lao, Y.; Parhi, K.K. (May 2015). "Obfuscating DSP Circuits via High-Level Transformations". IEEE Transactions on VLSI Systems. 23 (5): 819–830. doi:10.1109/TVLSI.2014.2323976.
  27. ^ Koteshwara, S.; Kim, C.H.; Parhi, K.K. (January 2018). "Key-Based Dynamic Functional Obfuscation of Integrated Circuits using Sequentially-Triggered Mode-Based Design". IEEE Transactions on Information Forensics and Security. 13 (1): 79–93. doi:10.1109/TIFS.2017.2738600.
  28. ^ Wang, C.-Y.; Parhi, K.K. (March 1995). "High-Level DSP Synthesis using Concurrent Transformations, Scheduling, and Allocation". IEEE Transactions on Computer Aided Design. 14 (3): 274–295. doi:10.1109/43.365120.
  29. ^ Satyanarayana, J.; Parhi, K.K. (June 1996). HEAT: Hierarchical Energy Analysis Tool. ACM/IEEE Design Automation Conference. pp. 9–14. doi:10.1109/DAC.1996.545536.
  30. ^ https://cse.umn.edu/college/collegiate-awards#bowers
  31. ^ https://aimbe.org/press/parhi-COF-7098.pdf
  32. ^ https://ieee-cas.org/award/society-achievement-awards/ieee-cas-john-choma-education-award#recipients
  33. ^ https://www.acm.org/media-center/2021/january/fellows-2020
  34. ^ https://twin-cities.umn.edu/news-events/u-m-professor-keshab-parhi-be-inducted-national-academy-inventors
  35. ^ https://www.aaas.org/news/2017-aaas-fellows-recognized-advancing-science
  36. ^ https://ieee-cas.org/award/society-achievement-awards/ieee-circuits-and-systems-society-mac-van-valkenburg-award#recipients
  37. ^ https://www.iitkgpfoundation.org/images.html?file_id=p36LO29TE08
  38. ^ https://ieee-cas.org/award/society-achievement-awards/ieee-circuits-and-systems-society-charles-desoer-technical#recipients
  39. ^ https://monolith.asee.org/member-resources/awards/full-list-of-awards/awards-archive/division-awards-archive/electrical-and-computer-engineering-division
  40. ^ https://en.wikipedia.org/wiki/IEEE_Kiyo_Tomiyasu_Award
  41. ^ https://en.wikipedia.org/wiki/IEEE_W.R.G._Baker_Award
  42. ^ https://services27.ieee.org/fellowsdirectory/getdetailprofile.html?custNum=%2FoocXrWmHj68o0KcZJDrNQ
  43. ^ https://www.nsf.gov/awardsearch/showAward?AWD_ID=9258670
  44. ^ https://ethw.org/IEEE_Browder_J._Thompson_Memorial_Prize_Paper_Award
  45. ^ https://signalprocessingsociety.org/sites/default/files/uploads/community_involvement/awards/Young_Author_Best_Paper.pdf
  46. ^ https://www2.eecs.berkeley.edu/Students/Awards/10/
  47. ^ https://www2.eecs.berkeley.edu/Students/Awards/1/



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