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Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have increased in complexity into the hundreds of millions of transistors.

Overview

The first semiconductor chips held one transistor each. Subsequent advances added more and more transistors, and, as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as "small-scale integration" (SSI), improvements in technique led to devices with hundreds of logic gates, known as large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved far past this mark and today's microprocessors have many millions of gates and hundreds of millions of individual transistors.

At one time, there was an effort to name and calibrate various levels of large-scale integration above VLSI. Terms like Ultra-large-scale Integration (ULSI) were used. But the huge number of gates and transistors available on common devices has rendered such fine distinctions moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread use. Even VLSI is now somewhat quaint, given the common assumption that all microprocessors are VLSI or better.

As of early 2008, billion-transistor processors are commercially available, an example of which is Intel's Montecito Itanium chip. This is expected to become more commonplace as semiconductor fabrication moves from the current generation of 65 nm processes to the next 45 nm generations (while experiencing new challenges such as increased variation across process corners). Another notable example is Nvidia's 280 series GPU. This microprocessor is unique in the fact that its 1.4 Billion transistor count, capable of a teraflop of performance, is almost entirely dedicated to logic (Itanium's transistor count is largely due to the 24MB L3 cache). Current designs, as opposed to the earliest devices, use extensive design automation and automated logic synthesis to lay out the transistors, enabling higher levels of complexity in the resulting logic functionality. Certain high-performance logic blocks like the SRAM cell, however, are still designed by hand to ensure the highest efficiency (sometimes by bending or breaking established design rules to obtain the last bit of performance by trading stability).

Structured design

Structured VLSI design is a modular methodology originated by Carver Mead and Lynn Conway for saving microchip area by minimizing the interconnect fabrics area. This is obtained by repetitive arrangement of rectangular macro blocks which can be interconnected using wiring by abutment. An example is partitioning the layout of an adder into a row of equal bit slices cells. In complex designs this structuring may be achieved by hierarchical nesting.

Structured VLSI design had been popular in the early 1980s, but lost its popularity later because of the advent of placement and routing tools wasting a lot of area by routing, which is tolerated because of the progress of Moore's Law. When introducing the hardware description language KARL in the mid' 1970s, Reiner Hartenstein coined the term "structured VLSI design" (originally as "structured LSI design"), echoing Edsger Dijkstra's structured programming approach by procedure nesting to avoid chaotic spaghetti-structured programs.

Challenges

As microprocessors become more complex due to technology scaling, microprocessor designers have encountered several challenges which force them to think beyond the design plane, and look ahead to post-silicon:

Power usage/Heat dissipation – As threshold voltages have ceased to scale with advancing process technology, dynamic power dissipation has not scaled proportionally. Maintaining logic complexity when scaling the design down only means that the power dissipation per area will go up. This has given rise to techniques such as dynamic voltage and frequency scaling (DVFS) to minimize overall power.
Process variation – As lithography techniques tend closer to the fundamental laws of optics, achieving high accuracy in doping concentrations and etched wires is becoming more difficult and prone to errors due to variation. Designers now have to simulate across multiple fabrication process corners before the chip is certified ready for production.
Stricter design rules – Due to lithography and etch issues with scaling, design rules for layout have gotten much more stringent. Designers have to keep more of these rules in mind while laying out custom circuits. The overhead for custom design is now reaching a tipping point, with many design houses now opting to switch to electronic design automation (EDA) tools to automate their design process.
Timing/design closure – As clock frequencies tend to scale up, designers are finding it more difficult to distribute and maintain low clock skew between these high frequency clocks across the entire chip. This has led to a rising interest in multicore and multiprocessor architectures, since an overall speedup can be obtained by lowering the clock frequency and distributing processing.
First-pass success – As die sizes shrink (due to scaling), and wafer sizes go up (to lower manufacturing costs), the number of dies per wafer increases. Wafers in modern technologies can cost several million dollars. This deters the old, iterative philosophy involving several "spin-cycles" to find errors in silicon, and encourages first-pass silicon success. Several design philosophies have been developed to aid this new design flow, including design for manufacturing (DFM), design for test (DFT), and many others.

Notable companies

Conferences

ISSCC – IEEE International Solid-State Circuits Conference
CICC – IEEE Custom Integrated Circuit Conference
ISCAS – IEEE International Symposium on Circuits and Systems
VLSI – IEEE International Conference on VLSI Design
DAC – Design Automation Conference
ICCAD – International Conference on Computer-Aided Design
ISPD – International Symposium on Physical Design
ISQED – International Symposium on Quality Electronic Design
DATE – Design Automation and Test in Europe
IEDM – IEEE International Electron Devices Meeting
ASP-DAC – Asia and South Pacific Design Automation Conference

External links

Software

Electric and Magic are open-source software often used to lay out VLSI circuits.
LASI General Purpose VLSI IC layout and design system
VLSI Layout 3D - Visualization Software for LASI - written by Ed Pataky

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 *Stricter design rules – Due to lithography and etch issues with scaling, [[design rule checking|design rules]] for [[layout]] have gotten much more stringent. Designers have to keep more of these rules in mind while laying out custom circuits. The overhead for custom design is now reaching a tipping point, with many design houses now opting to switch to [[electronic design automation]] (EDA) tools to automate their design process.
 *[[Design closure|Timing/design closure]] – As [[clock frequency|clock frequencies]] tend to scale up, designers are finding it more difficult to distribute and maintain low [[clock skew]] between these high frequency clocks across the entire chip. This has led to a rising interest in [[multicore]] and [[multiprocessor]] architectures, since an [[Amdahl's law|overall speedup]] can be obtained by lowering the clock frequency and distributing processing.
-*First-pass success – As die sizes shrink (due to scaling), and wafer sizes go up (to lower manufacturing costs), the number of dies per wafer increases. Wafers in modern technologies cost several million dollars. This deters the old, iterative philosophy involving several "spin-cycles" to find errors in silicon, and encourages first-pass silicon success. Several design philosophies have been developed to aid this new design flow, including design for manufacturing ([[Design for manufacturability (IC)|DFM]]), design for test ([[Design for Test|DFT]]), and [[Design for X|many others]].
+*First-pass success – As die sizes shrink (due to scaling), and wafer sizes go up (to lower manufacturing costs), the number of dies per wafer increases. Wafers in modern technologies can cost several million dollars. This deters the old, iterative philosophy involving several "spin-cycles" to find errors in silicon, and encourages first-pass silicon success. Several design philosophies have been developed to aid this new design flow, including design for manufacturing ([[Design for manufacturability (IC)|DFM]]), design for test ([[Design for Test|DFT]]), and [[Design for X|many others]].
 ==Notable companies==