Language for Instruction Set Architecture: Difference between revisions
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'''LISA''' (Language for Instruction Set Architectures) is a language to describe the [[instruction set architecture]] of a processor. LISA captures the information required to generate [[software tools]] ([[compiler]], [[assembly language|assembler]], [[instruction set simulator]], ...) and implementation hardware (in [[VHDL]] or [[Verilog]]) of a given [[microprocessor|processor]] core. |
'''LISA''' (Language for Instruction Set Architectures) is a language to describe the [[instruction set architecture]] of a processor. LISA captures the information required to generate [[software tools]] ([[compiler]], [[assembly language|assembler]], [[instruction set simulator]], ...) and implementation hardware (in [[VHDL]] or [[Verilog]]) of a given [[microprocessor|processor]] core. |
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LISA has been used to re-implement the hardware of existing processor cores, keeping the [[binary compatibility]] with the legacy version, as all [[software tools]] did already exist and legacy compiled software images could be executed on the newly created hardware. Another application has been to generate the ISS ([[instruction set simulator]]) for RISC processors such the [[ARM Architecture]] ISSes. |
LISA has been used to re-implement the hardware of existing processor cores, keeping the [[binary compatibility]] with the legacy version, as all [[software tools]] did already exist and legacy compiled software images could be executed on the newly created hardware. Another application has been to generate the ISS ([[instruction set simulator]]) for [[Reduced_instruction_set_computing|RISC]] processors such the [[ARM Architecture]] ISSes. |
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'''LISA''' is not focused on the modeling of other on-chip components around the processor core itself, such as peripherals, hardware accelerators, buses and memories; Other languages such as [[SystemC]] can be used for these. |
'''LISA''' is not focused on the modeling of other on-chip components around the processor core itself, such as peripherals, hardware accelerators, buses and memories; Other languages such as [[SystemC]] can be used for these. |
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Revision as of 13:21, 9 August 2012
| Designed by | Vojin Zivojnovic, Stefan Pees, version 1.0 |
|---|---|
| First appeared | 1997, last revised 2007 |
| Website | http://darwin.bth.rwth-aachen.de/opus3/frontdoor.php?source_opus=661&la=de |
| Dialects | |
| LISA 2.0, LISA+ | |
LISA (Language for Instruction Set Architectures) is a language to describe the instruction set architecture of a processor. LISA captures the information required to generate software tools (compiler, assembler, instruction set simulator, ...) and implementation hardware (in VHDL or Verilog) of a given processor core.
LISA has been used to re-implement the hardware of existing processor cores, keeping the binary compatibility with the legacy version, as all software tools did already exist and legacy compiled software images could be executed on the newly created hardware. Another application has been to generate the ISS (instruction set simulator) for RISC processors such the ARM Architecture ISSes.
LISA is not focused on the modeling of other on-chip components around the processor core itself, such as peripherals, hardware accelerators, buses and memories; Other languages such as SystemC can be used for these.
The language has not been yet standardised by IEEE or ISO and is currently owned by RWTH Aachen University, in Germany.
Features
![[icon]](/enwiki/wiki/File:Wiki_letter_w_cropped.svg){kind=small} | This section is empty. You can help by adding to it. (July 2010) |
History
LISA was initially developed at Institute for Integrated Signal Processing Systems (ISS) Aachen, belonging to RWTH Aachen University, in Germany. The current official version from RWTH Aachen is LISA 2.0. The language is still in evolution to cover research on processors, including Reconfigurable computing (in LISA 3.0), multi-core, parallel programming.
One noticeable branch called LISA+ has been created for handling the modeling of peripherals such as interrupt controllers, timers, etc. [1]
See also
References
 | This article includes a list of general references, but it lacks sufficient corresponding inline citations. (April 2009) |
- ^ * [http:/infocenter.arm.com] search for LISA+ Reference Language Manual
Papers
- V. Zivojnovic, S. Pees, Ch. Schläger, H. Meyr, LISA bridges gaps in high-tech languages, Electronic Engineering Times, Oct 7, 1996
- [1] V. Zivojnovic, S. Pees, H. Meyr, LISA – machine description language and generic machine model for HW/SW co-design, Proceedings of the IEEE Workshop on VLSI Signal Processing (San Francisco), Oct. 1996
Books
- Oliver Wahlen: C Compiler Aided Design of Application-specific Instruction-set Processors Using the Machine Description Language LISA (Berichte Aus Der Electrotechnik), Shaker Verlag GmbH, Germany (August 13, 2004), ISBN 3-8322-3035-1
- Anupam Chattopadhyay, Heinrich Meyr and Rainer Leupers: LISA: A Uniform ADL for Embedded Processor Modeling, Implementation and Software Toolsuite Generation in Processor Description Languages, Volume 1, Morgan Kaufmann, ISBN-10: 0123742870
External links
- LISA project page at RWTH Aachen, Germany
- Processor Designer is a tool sold by Synopsys to create processors from LISA 2.0 descriptions