Q32 (computer): Difference between revisions
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==== Description ==== |
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[[Q31|Q-31]] and [[Q32|Q-32]] ([[AN/FSQ-31V]] and [[AN/FSQ-32]]) were [[computer]]s made by [[IBM]] (International Business Machines) in 1960 and 1961 for the United States Air Force [[Strategic Air Command]] (SAC). Four '''Q-31''' units were built. They were used as the Data Processing Center (DPC) portion of the [[SAC Automated Command and Control System]]<ref>{{cite web |
[[Q31|Q-31]] and [[Q32|Q-32]] ([[AN/FSQ-31V]] and [[AN/FSQ-32]]) were [[computer]]s made by [[IBM]] (International Business Machines) in 1960 and 1961 for the United States Air Force [[Strategic Air Command]] (SAC). Four '''Q-31''' units were built. They were used as the Data Processing Center (DPC) portion of the [[SAC Automated Command and Control System]]<ref>{{cite web |
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| last = Wohlman |
| last = Wohlman |
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| first = John |
| first = John |
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| authorlink = |
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| coauthors = |
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| year = 1968 |
| year = 1968 |
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| ⚫ | |||
| url = http://www.airpower.maxwell.af.mil/airchronicles/aureview/1968/jan-feb/wohlman.html |
| url = http://www.airpower.maxwell.af.mil/airchronicles/aureview/1968/jan-feb/wohlman.html |
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| title = Computer-Generated Map Data |
| title = Computer-Generated Map Data |
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| subtitle = An Aid to Command and Control |
| subtitle = An Aid to Command and Control |
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| format = |
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| work = |
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| ⚫ | |||
| accessdate = June 20 |
| accessdate = June 20 |
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| accessyear = 2006 |
| accessyear = 2006 |
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}}</ref> |
}}</ref> |
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| ⚫ | |||
==== Locations ==== |
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| ⚫ | Two (DPC 1 and DPC 2) were installed at SAC headquarters (Bldg 500) at [[Offutt Air Force Base]] outside [[Omaha, Nebraska]]. One (DPC 3) was installed in the Headquarters 15th Air Force Combat Operations Center at [[March Air Force Base]], near [[Riverside, California]] and one (DPC 4) was installed as a backup system at the 2nd Air Force Combat Operations Center at [[Barksdale Air Force Base]]. The '''Q-32''' was installed at [[System Development Corporation]] (SDC) headquarters, Santa Monica, California and was used as a development machine for the compiler and operational software for the '''Q-31'''s. |
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==== Architecture ==== |
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The system was divided into functional sections: |
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:# [[Central Processing Unit]] |
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:# Memory |
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:# High-Speed Input/Output |
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:# Low-Speed Input/Output |
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:# Operations Console |
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===== Central Processing Unit ===== |
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Memory was addressed by words, which were 48 bits long. Each word was divided into 8 6-bit bytes. A 6-bit byte, as opposed to the 8-bit [[byte]] in common use today, was common in IBM and other scientific computers of the time. The address space provided a maximum of 256K words. The '''Q-31'''s were equipped with 4 16kword memory banks, while the '''Q-32''' was equipped with 128kwords. The memory bank was oil and water cooled. |
Memory was addressed by words, which were 48 bits long. Each word was divided into 8 6-bit bytes. A 6-bit byte, as opposed to the 8-bit [[byte]] in common use today, was common in IBM and other scientific computers of the time. The address space provided a maximum of 256K words. The '''Q-31'''s were equipped with 4 16kword memory banks, while the '''Q-32''' was equipped with 128kwords. The memory bank was oil and water cooled. |
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The operation field provided the operation code and a variety of modifiers. Some modifiers allowed instructions to operate only on specific bytes of a word or on specific bits of a byte without separate masking operations. Other modifiers allowed the single 48-bit [[ALU]] to operate on a pair of 24-bit operands to facilitate vector operations. |
The operation field provided the operation code and a variety of modifiers. Some modifiers allowed instructions to operate only on specific bytes of a word or on specific bits of a byte without separate masking operations. Other modifiers allowed the single 48-bit [[ALU]] to operate on a pair of 24-bit operands to facilitate vector operations. |
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The computers were part of the SAC command and control system. SDC developed the system software using [[JOVIAL]] (Jules Own Version of the International Algebraic Language), one of the first high level complied programming languages. |
The computers were part of the SAC command and control system. SDC developed the system software using [[JOVIAL]] (Jules Own Version of the International Algebraic Language), one of the first high level complied programming languages. |
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{{unreferenced}} |
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==References== |
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<references /> |
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Revision as of 22:58, 20 June 2006
Description
Q-31 and Q-32 (AN/FSQ-31V and AN/FSQ-32) were computers made by IBM (International Business Machines) in 1960 and 1961 for the United States Air Force Strategic Air Command (SAC). Four Q-31 units were built. They were used as the Data Processing Center (DPC) portion of the SAC Automated Command and Control System[1]
Locations
Two (DPC 1 and DPC 2) were installed at SAC headquarters (Bldg 500) at Offutt Air Force Base outside Omaha, Nebraska. One (DPC 3) was installed in the Headquarters 15th Air Force Combat Operations Center at March Air Force Base, near Riverside, California and one (DPC 4) was installed as a backup system at the 2nd Air Force Combat Operations Center at Barksdale Air Force Base. The Q-32 was installed at System Development Corporation (SDC) headquarters, Santa Monica, California and was used as a development machine for the compiler and operational software for the Q-31s.
Architecture
The system was divided into functional sections:
- Central Processing Unit
- Memory
- High-Speed Input/Output
- Low-Speed Input/Output
- Operations Console
Central Processing Unit
Memory was addressed by words, which were 48 bits long. Each word was divided into 8 6-bit bytes. A 6-bit byte, as opposed to the 8-bit byte in common use today, was common in IBM and other scientific computers of the time. The address space provided a maximum of 256K words. The Q-31s were equipped with 4 16kword memory banks, while the Q-32 was equipped with 128kwords. The memory bank was oil and water cooled.
The ISA was rather complicated for its time. The instructions were a fixed length of one word providing 24 bits for the operation and 24 bits for the address. The address consisted of 18 bits (3 bytes) for the memory address, with other bits used for the specification of index registers and indirect addressing.
The operation field provided the operation code and a variety of modifiers. Some modifiers allowed instructions to operate only on specific bytes of a word or on specific bits of a byte without separate masking operations. Other modifiers allowed the single 48-bit ALU to operate on a pair of 24-bit operands to facilitate vector operations.
References
- ^ Wohlman, John (1968). "Computer-Generated Map Data". Air University Review. Retrieved June 20.
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