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===Acquisition===
===Acquisition===
In November 2017, Cavium's board of directors agreed to the company's purchase by [[Marvell Technology Group]] for $6 billion in cash and stock.<ref name=":11">{{cite news|last1=PALLADINO|first1=Valentina|title=Marvell Technology to buy chipmaker Cavium for about $6 billion|url=https://arstechnica.com/information-technology/2017/11/marvell-technology-strikes-deal-to-buy-chipmaker-cavium-for-6-billion/|accessdate=20 November 2017|publisher=Ars Technica|date=20 November 2017}}</ref> The merger was finalized on July 6, 2018.
In November 2017, Cavium's board of directors agreed to the company's purchase by [[Marvell Technology Group]] for $6 billion in cash and stock.<ref name=":11">{{cite news|last1=PALLADINO|first1=Valentina|title=Marvell Technology to buy chipmaker Cavium for about $6 billion|url=https://arstechnica.com/information-technology/2017/11/marvell-technology-strikes-deal-to-buy-chipmaker-cavium-for-6-billion/|accessdate=20 November 2017|publisher=Ars Technica|date=20 November 2017}}</ref> The merger was finalized on July 6, 2018.

==Products==

===cnMIPS microarchitecture===
The cnMIPS [[microarchitecture]] implements the [[MIPS64]] [[instruction set]].

===cnMIPS II microarchitecture===

===cnMIPS III microarchitecture===

===OCTEON SoCs===
<ref>[https://www.cavium.com/Table.html#Octeon Cavium.com: Cavium Octeon SoCs Product Table] {{webarchive |url=https://web.archive.org/web/20161020102805/https://www.cavium.com/Table.html#Octeon |date=October 20, 2016 }}</ref>
{|class="wikitable" style="font-size: 85%; text-align: center"
!rowspan=2|Model
!rowspan=2|Launch
!rowspan=2|Fab ([[nanometer|nm]])
!colspan=3|[[cnMIPS (microarchitecture)|cnMIPS I]]-cores
!rowspan=2|Notes
|-
! #
! Core clock ([[Hertz|MHz]])
! L2 cache<br>[KB]
|-
| CN3005 || 2002 || rowspan=9|90 || 1 || rowspan=4|300–500 || 64 ||
|-
| CN3010 || || 1 || 128 ||
|-
| CN3110 || || 1 || 256 ||
|-
| CN3120 || || 2 || 256 ||
|-
| CN3630 || || 4 || rowspan=5|400–600 || 512 ||
|-
| CN3830 || || 4 || 1024 ||
|-
| CN3840 || || 8 || 1024 ||
|-
| CN3850 || || 12 || 1024 ||
|-
| CN3860 || || 16 || 1024 ||
|-
|}

===OCTEON Plus SoCs===
<ref>[https://www.cavium.com/Table.html#Octeonplus Cavium.com: Cavium Octeon Plus SoCs Product Table] {{webarchive |url=https://web.archive.org/web/20161020102805/https://www.cavium.com/Table.html#Octeonplus |date=October 20, 2016 }}</ref>
{|class="wikitable" style="font-size: 85%; text-align: center"
!rowspan=2|Model
!rowspan=2|Launch
!rowspan=2|Fab ([[nanometer|nm]])
!colspan=3|[[cnMIPS (microarchitecture)|cnMIPS I]]-cores
!rowspan=2|Notes
|-
! #
! Core clock ([[Hertz|MHz]])
! L2 cache<br>[KB]
|-
| CN5010 || || rowspan=18|90 || 1 || rowspan=2|300–700 || 128 ||
|-
| CN5020 || || 2 || 128 ||
|-
| CN5220 || || 2 || rowspan=2|500–800 || 512 ||
|-
| CN5230 || || 4 || 512 ||
|-
| CN5430 || || 4 || rowspan=4|500–700 || 1024 ||
|-
| CN5434 || || 6 || 1024 ||
|-
| CN5530 || || 4 || 1024 ||
|-
| CN5534 || || 6 || 1024 ||
|-
| CN5640 || || 8 || rowspan=10|600–800 || 2048 ||
|-
| CN5645 || || 10 || 2048 ||
|-
| CN5650 || || 12 || 2048 ||
|-
| CN5740 || || 8 || 2048 ||
|-
| CN5745 || || 10 || 2048 ||
|-
| CN5750 || || 12 || 2048 ||
|-
| CN5830 || || 4 || 2048 ||
|-
| CN5840 || || 8 || 2048 ||
|-
| CN5850 || || 12 || 2048 ||
|-
| CN5860 || || 16 || 2048 ||
|-
|}

===OCTEON II SoCs===
<ref>[https://www.cavium.com/Table.html#OcteonII Cavium.com: Cavium Octeon II SoCs Product Table] {{webarchive |url=https://web.archive.org/web/20161020102805/https://www.cavium.com/Table.html#OcteonII |date=October 20, 2016 }}</ref>
{|class="wikitable" style="font-size: 85%; text-align: center"
!rowspan=2|Model
!rowspan=2|Launch
!rowspan=2|Fab ([[nanometer|nm]])
!colspan=3|[[cnMIPS (microarchitecture)|cnMIPS II]]-cores
!rowspan=2|Notes
|-
! #
! Core clock ([[Hertz|MHz]])
! L2 cache<br>[KB]
|-
| CN6010 || || rowspan=16|65 || 1 || rowspan=2|400–800 || 512 ||
|-
| CN6020 || || 2 || 512 ||
|-
| CN6120 || || 2 || rowspan=2|600–1200 || 1024 ||
|-
| CN6130 || || 4 || 1024 ||
|-
| CN6220 || || 2 || rowspan=2|800–1000 || 1024 ||
|-
| CN6230 || || 4 || 1024 ||
|-
| CN6320 || || 2 || rowspan=7|800–1500 || 2048 ||
|-
| CN6330 || || 4 || 2048 ||
|-
| CN6335 || || 6 || 2048 ||
|-
| CN6635 || || 6 || 2048 ||
|-
| CN6645 || || 10 || 2048 ||
|-
| CN6740 || || 8 || 4096 ||
|-
| CN6760 || || 16 || 4096 ||
|-
| CN6860 || || 16 || rowspan=3|800–1400 || 4096 ||
|-
| CN6870 || || 24 || 4096 ||
|-
| CN6880 || || 32 || 4096 ||
|-
|}

===OCTEON III SoCs===
<ref>[https://www.cavium.com/Table.html#OcteonIII Cavium.com: Cavium Octeon III SoCs Product Table] {{webarchive |url=https://web.archive.org/web/20161020102805/https://www.cavium.com/Table.html#OcteonIII |date=October 20, 2016 }}</ref>
<ref>[https://www.cavium.com/OCTEON-III_CN77XX.html#OcteonIII Cavium.com: Cavium Octeon III SoCs Product CN77XX Table] {{webarchive |url=https://web.archive.org/web/20161020102445/https://www.cavium.com/OCTEON-III_CN77XX.html#OcteonIII |date=October 20, 2016 }}</ref>
{|class="wikitable" style="font-size: 85%; text-align: center"
!rowspan=2|Model
!rowspan=2|Launch
!rowspan=2|Fab ([[nanometer|nm]])
!colspan=3|[[cnMIPS (microarchitecture)|cnMIPS III]]-cores
!rowspan=2|Notes
|-
! #
! Core clock ([[Hertz|MHz]])
! L2 cache<br>[KB]
|-
| CN7010 || || rowspan=13|28 || 1 ||rowspan=2|800–1200 || 512 ||
|-
| CN7020 || || 2 || 512 ||
|-
| CN7120 || || 2 ||rowspan=3|800–1600 || 512 ||
|-
| CN7125 || || 3 || 512 ||
|-
| CN7130 || || 4 || 512 ||
|-
| CN7340 || || 8 || rowspan=3|1500-2000 || rowspan=3|4096 ||
|-
| CN7350 || || 12 ||
|-
| CN7360 || || 16 ||
|-
| CN7760 || || 16 ||rowspan=5|1600–2500 || 8192 ||
|-
| CN7770 || || 24 || 8192 ||
|-
| CN7870 || || 24 || 16384 ||
|-
| CN7880 || || 32 || 16384 ||
|-
| CN7890 || || 48 || 16384 ||
|-
|}

===ThunderX SoCs===
The ThunderX line of [[System on a Chip|SoCs]] from Cavium were released with up to 48 dual issue, [[Out-of-order execution|out of order]] [[ARMv8]] cores.<ref>{{cite news|last1=De Gelas|first1=Johan|title=ARM Challenging Intel in the Server Market|url=https://www.anandtech.com/show/8776/arm-challinging-intel-in-the-server-market-an-overview|accessdate=8 March 2017|publisher=Anandtech|date=16 December 2014}}</ref><ref>[https://www.cavium.com/ThunderX_ARM_Processors.html Cavium.com ThunderX product page] {{webarchive |url=https://web.archive.org/web/20161124225559/https://www.cavium.com/ThunderX_ARM_Processors.html |date=November 24, 2016 }}</ref> These SoCs were targeted at servers in network intensive applications, competing with [[Intel Xeon]] products.<ref name='ThunderX_review'>{{cite news|last1=De Gelas|first1=Johan|title=Investigating the Cavium ThunderX|url=https://www.anandtech.com/show/10353/investigating-cavium-thunderx-48-arm-cores|accessdate=8 March 2017|publisher=Anandtech|date=15 June 2016}}</ref> The ThunderX line is manufactured by [[Global Foundries]] at 28&nbsp;nm and is reported to have a [[thermal design power|TDP]] less than 100W.<ref name='ThunderX_review' />
{|class="wikitable" style="font-size: 85%; text-align: center"
!rowspan=2|Model
!rowspan=2|Launch
!rowspan=2|Fab ([[nanometer|nm]])
!colspan=2|[[ARM architecture#ARMv8-A|ARMv8-A]]-cores
!rowspan=2|Notes
|-
! #
! Core clock ([[Hertz|MHz]])
|-
| CN87xx_xx || 2014 || rowspan=2|28 || 8–16 || Up to 2500 ||
|-
| CN88xx_xx || 2014 || 24–48 || Up to 2500 ||
|}
[[Sandia National Laboratories]]' second generation supercomputer in their Vanguard project called Sullivan was based Cavium's ThunderX processors. The first generation was called Hammer, it was based on [[X-Gene (microarchitecture)|X-Gene]] by [[Applied Micro Circuits Corporation|Applied Micro]].<ref name=":1">{{Cite web|url=https://fuse.wikichip.org/news/1583/cavium-takes-arm-to-petascale-with-astra/|title=Cavium Takes ARM to Petascale with Astra|last=Schor|first=David|date=2018-08-25|website=WikiChip Fuse|language=en-US|access-date=2019-05-27}}</ref>

* [[Comparison of ARMv8-A cores]]

=== ThunderX2 SoCs ===
Cavium announced in 2016 the ThunderX2 line of SoCs, initially as iterative improvement of their ThunderX line.<ref name='ThunderX_review' /><ref>{{cite news|last1=Russell|first1=John|title=Cavium Unveils ThunderX2 Plans, Reports ARM Traction is Growing|url=https://www.hpcwire.com/2016/05/31/cavium-unveils-thunderx2-plans-reports-arm-traction-growing/|accessdate=8 March 2017|publisher=HPC Wire|date=31 May 2016}}</ref> The name was later used for the former Vulcan SoC design purchased from [[Broadcom]].<ref>{{cite web|url=https://reviews.llvm.org/D30510|title=⚙ D30510 Vulcan is now ThunderX2T99|website=reviews.llvm.org}}</ref><ref>{{cite news|last1=Kampman|first1=Jeff|title=Scaling Raven Ridge with David Kanter: The TR Podcast 191|url=https://techreport.com/review/33038/scaling-raven-ridge-with-david-kanter-the-tr-podcast-191|accessdate=5 January 2018|publisher=Tech Report|date=5 January 2018}}</ref> ThunderX2 has up to 32 custom ARM cores and is manufactured on Global Foundries' 16&nbsp;nm [[FinFET]] process. These and other improvements are reported to offer twice the performance per core of the ThunderX line.

[[Cray]] has added "ARM Option" (i.e. CPU [[blade server|blade]] option, using the ThunderX2) to their [[Cray XC50|XC50]] supercomputers, and Cray states that ARM is "<!--In talking with Fred Kohout, Cray's Chief Marketing Officer and VP of products, there are also DOE customers interested in ThunderX2-powered XC50 – not surprising considering that the agency used some of its FastForward 2 money to fund Cray's initial work in this area. Although most of the main processing units in pre-exascale and exascale machines in the US are likely to be based on either x86 or Power, ARM gives the DOE -->a third processor architecture for building next-generation supercomputers", for clients such as [[United States Department of Energy|the US Department of Energy]].<ref name="Cray">{{Cite web|url=https://www.top500.org/news/cray-adds-arm-option-to-xc50-supercomputer/|title=Cray Adds ARM Option to XC50 Supercomputer {{!}} TOP500 Supercomputer Sites|website=www.top500.org|language=en|access-date=2017-11-14|quote=Cray claims its ARM compiler demonstrated better performance in two-thirds of 135 benchmarks, and much better performance – 20 percent or more – in one-third of them, compared to open source ARM compilers from LLVM and GNU. The Cray ThunderX2 blades can be mixed with other XC50 blades outfitted with Intel Xeon-SP or Xeon Phi processors and NVIDIA Tesla GPUs. Both air-cooled and liquid-cooled options are available. Cray already has one customer lined up for the ThunderX2-powered XC50: the Great Western 4 (GW4) Alliance, a research consortium of four UK universities (Bristol, Bath, Cardiff and Exeter). In January 2017, the alliance announced it had contracted Cray to build "Isambard", a 10,000-core ARM-based supercomputer, which will provide a Tier 2 HPC service. The UK's Met Office was also involved on the deal, since it was interested in seeing how its weather and climate codes would run on such a machine. The system will be paid for out of a £3 million award from the Engineering and Physical Sciences Research Council (EPSRC). It’s scheduled to be fully deployed by the end of this year.}}</ref>

The Cray XC50-series supercomputer for the [[University of Bristol]] is called '''Isambard''', named after [[Isambard Kingdom Brunel]]. The supercomputer is expected to feature around 160 nodes, each with two 32-core ThunderX2 processors running at 2.1&nbsp;GHz. Peak theoretical performance of the 10,240 cores and 40,960 threads is 172 teraFLOPS.<ref name=":2">{{Cite web|url=https://fuse.wikichip.org/news/1316/a-look-at-caviums-new-high-performance-arm-microprocessors-and-the-isambard-supercomputer/|title=A Look at Cavium's New High-Performance ARM Microprocessors and the Isambard Supercomputer|date=2018-06-03|website=WikiChip Fuse|language=en-US|access-date=2019-05-27}}</ref>

The third generation of the [[Sandia National Laboratories]]' Vanguard project called '''Mayer''' was based on pre-production ThunderX2 and consisted of 47 nodes. The fourth generation also based on ThunderX2 is called '''Astra''' and will become operation by November 2018. Each Astra node will feature two 28-core ThunderX2 processors running at 2.0&nbsp;GHz with 128&nbsp;GB DDR4. Each rack has 18x [[Hewlett Packard Enterprise]] Apollo 70 chassis with 72 compute nodes along with 3 [[InfiniBand]] switches. Astra will feature a total of 36 racks. Thus Astra will have 5,184 ThunderX2 processors, 145,152 ThunderX2 cores and 580,608 threads. Astra's peak theoretical performance is 4.644 PFLOPS in Single Precision, and 2.322&nbsp;PFLOPS in Double Precision and will support 324&nbsp;TB DDR4.<ref name=":1" /> Astra is the first ARM-based [[Petascale computing|Petascale]] supercomputer to enter the [[TOP500]] list. In November 2018 it is ranked at 204, while {{as of|2019|June|lc=y}} it's ranked at 156 after an upgrade.<ref>{{Cite web|url=https://www.top500.org/system/179565|title=Astra – Apollo 70, Cavium ThunderX2 CN9975-2000 28C 2GHz, 4xEDR Infiniband {{!}} TOP500 Supercomputer Sites|website=www.top500.org|access-date=2019-08-17}}</ref>

On March 2, 2020, Marvell announced OCTEON TX2 and OCTEON Fusion processors feature OCTEON TX2 Microarchitecture.<ref name=":13">{{Cite web|url=https://www.anandtech.com/show/15572/marvell-announces-octeon-fusion-and-octeon-tx2-5g-infrastructure-processors|title=Marvell Announces OCTEON Fusion and OCTEON TX2 5G Infrastructure Processors|last=Frumusanu|first=Andrei|website=www.anandtech.com|access-date=2020-03-20}}</ref>

==== ThunderX2/Vulcan core ====
ThunderX2 Microarchitecture<ref name=":0">{{Cite web|url=https://www.anandtech.com/show/12694/assessing-cavium-thunderx2-arm-server-reality|title=Assessing Cavium's ThunderX2: The Arm Server Dream Realized At Last|last=Gelas|first=Johan De|website=www.anandtech.com|access-date=2019-05-27}}</ref><ref name=":2" />:

* ISA: [[ARM architecture#ARMv8.1-A|ARMv8.1-A]] with 128-bit NEON SIMD
*[[Simultaneous multithreading|SMT4]]
* L1-instruction cache: 32 KB with 8-way associativity and Instruction TLB
* L1-data cache: 32 KB with 8-way associativity with 64 entries Load buffer and 36 entries Store Buffer & Forwarding
* Load bandwidth: 2x 16B
* L2 cache: 256 KB with 8-way with associativity and 2048-entry STLB
* L3 cache: 1&nbsp;MB/core
* Fetch Width: 8 instructions (32-byte window)
* Decode width: 4
* Sustainable instructions/cycle: 4
* Loop buffer: 128 entries
* Instructions in flight: 180-entry ReOrder Buffer (ROB)
* Scheduler/Issue queue: Unified 60 entries
* Issue: 6
* Pipeline: 13–15 stages
*Cavium's Coherent Processor Interconnect 2 (CCPI2) with 600&nbsp;Gbit/s bandwidth

==== OCTEON TX2 core ====
OCTEON TX2 Microarchitecture<ref name=":13" />:

* ISA: [[ARM architecture#ARMv8.2-A|ARMv8.2-A]] with 128-bit NEON SIMD
* L1-instruction cache: 66 KB
* L1-data cache: 41 KB with 5-way associativity
*Issue: 4

{| class="wikitable sortable"
|+OCTEON TX, TX2 & OCTEON Fusion
|-
! rowspan="3" | Model
! rowspan="3" | Launch
! rowspan="3" |Fab ([[nanometer|nm]])
! colspan="6" |CPU
! rowspan="3" data-sort-type="number" |[[Thermal design power|TDP]]
|Memory
! colspan="3" |[[Input/output|I/O]]
! rowspan="3" |[[Multiprocessing]]
|-
! rowspan="2" |Core
! rowspan="2" |Cores<br />(Threads)
! colspan="2" |[[Clock rate]]
! rowspan="2" |L2 <br />cache
! rowspan="2" |L3 <br />cache
|
! rowspan="2" |[[PCI Express]]
! rowspan="2" |[[Ethernet]]
! rowspan="2" |[[IPsec|IPSEC]]
|-
! Normal
! data-sort-type="number" | Turbo
|
|-
| CN99XX<ref name=":0" />
|2019
| rowspan="7" |16
|ThunderX2
|32 (128)
| 2.2GHz
| 2.5GHz
|8MB
|32MB
| 180W
|8x DDR4-3200
|56x [[PCI Express 3.0|Gen 3]]
|
|
|2S with 600&nbsp;Gbit/s (CCPI2)
|-
|CN98XX<ref name=":13" />
| rowspan="6" |2020
| rowspan="3" |TX2
|30-36
|
|2.4GHz
|8MB
|21MB
|80–120W
|6x DDR4-3200
|32x [[PCI Express#PCI Express 4.0|Gen 4]]
|5x 100G
20x 25G
|200 Gbps
|
|-
|CN96XX
|18–24
|
|2.4GHz
|5MB
|14MB
|55–80W
|3x DDR4-3200
|24x [[PCI Express 3.0|Gen 4]]
|3x 100G
12x 25G
|100 Gbps
|
|-
|CN92XX
|12-18
|
|2.0GHz
|5MB
|8MB
|45–65W
|2x DDR4-3200
|24x [[PCI Express 3.0|Gen 4]]
|4x 25G
8x 10G
|50 Gbps
|
|-
|CN83XX
|ThunderX
|8-24
|
|2.0GHz
|
|8MB
|30–55W
|2x DDR4-2100
|22x [[PCI Express 3.0|Gen 3]]
|12x 10G
|30 Gbps
|
|-
|CN913X
|[[ARM Cortex-A72|A72]]
|4 (4)
|
|2.2GHz
|1MB
|1MB
|9–14W
|1x DDR4-2400
|18x [[PCI Express 3.0|Gen 3]]
|3x 10G
6x 1/2.5G
|15 Gbps
|
|-
|CNF95XX
|TX2
|6
|
|2.6GHz
|1.25MB
|3.5MB
|
|2x DDR4-2666
|
|
|
|
|}

=== ThunderX3 SoCs ===
On March 16, 2020, Marvell announced ThunderX3 and their plan for ThunderX4 in 2022.<ref name=":12">{{Cite web|url=https://www.anandtech.com/show/15621/marvell-announces-thunderx3-96-cores-384-thread-3rd-gen-arm-server-processor|title=Marvell Announces ThunderX3: 96 Cores & 384 Thread 3rd Gen Arm Server Processor|last=Frumusanu|first=Andrei|website=www.anandtech.com|access-date=2020-03-20}}</ref>

Microarchitecture details<ref name=":12" />:

* ISA: [[ARM architecture#ARMv8.3-A|ARMv8.3-A]]
*4 128-bit SIMD units

ThunderX3 SoC details include<ref name=":12" />:

*Up to 96x ThunderX3 cores
* Up to Base Frequency of 2.2&nbsp;GHz and turbo frequency up to 3&nbsp;GHz
* Up to 384 threads ([[Simultaneous multithreading|SMT4]])
* Up to 8-channel DDR4-3200
* Up to 64x PCIe 4.0 lanes
*[[TSMC]] N7P
* Up to TDP: 240 W
* Multiprocessing: 1S and 2S configurations with 672 Gbit/s bandwidth using Cavium's Coherent Processor Interconnect 3 (CCPI3)


==References==
==References==

Revision as of 15:20, 27 July 2020

Cavium, Inc.
Company typePublic
IndustryProcessors and boards
Founded2001; 23 years ago (2001)
DefunctJuly 6, 2018; 6 years ago (2018-07-06)
FateAcquired by Marvell Technology Group
Headquarters
San Jose, California
,
United States
Key people
Syed Ali (president & CEO)
Raghib Hussain (founder &​ COO)
ProductsMicroprocessors, boards
Number of employees
850[1]

Cavium was a fabless semiconductor company based in San Jose, California, specializing in ARM-based and MIPS-based network, video and security processors and SoCs.[2] The company was co-founded by Syed B. Ali and M. Raghib Hussain,[3] who were introduced to each other by a Silicon Valley entrepreneur. Cavium offers processor- and board-level products targeting routers, switches, appliances, storage and servers.

The company went public in May 2007 with about 175 employees. As of 2011, following numerous acquisitions, it had about 850 employees worldwide, of whom about 250 were located at company headquarters in San Jose.

Cavium is owned by Marvell Technology Group since July 6, 2018.[4]

History

Name change

On June 17, 2011, Cavium Networks, Inc. changed their name to Cavium, Inc.[5]

Acquisitions

Date Acquired company Historical product line
August 2008 Star Semiconductor ARM-based systems-on-chip processors[6]
December 2008 W&W Communications Video compression software and hardware[7]
December 2009 MontaVista Software Carrier Grade Linux compliant Linux & embedded systems[8]
January 2011[9] Celestial Semiconductor SoCs for digital media applications, including satellite, cable, and Internet TV[10]
February 2011 Wavesat Telecommunications Semiconductor solutions for carrier and mobile device manufacturers[11]
July 2014 Xpliant, Inc. Switching and SDN Specialist[12]
June 2016 QLogic, Inc. Ethernet and Storage Specialist[13]

Acquisition

In November 2017, Cavium's board of directors agreed to the company's purchase by Marvell Technology Group for $6 billion in cash and stock.[14] The merger was finalized on July 6, 2018.

References

  1. ^ "Cavium Networks Inc. returns to San Jose". Silicon Valley Business News. 8 July 2011. Retrieved 2015-01-08.
  2. ^ New York Times Company Profile for Cavium Inc. Archived March 5, 2016, at the Wayback Machine
  3. ^ "Syed Ali's company Cavium gets acquired for $6 billion". techober.com. Retrieved 2017-11-24.
  4. ^ Shilov, Anton. "Marvell Completes Acquisition of Cavium, Gets CPU, Networking & Security Assets". www.anandtech.com. Retrieved 2019-09-01.
  5. ^ http://biz.yahoo.com/e/110620/cavm8-k.html [dead link‍]
  6. ^ "Cavium Networks Completes Acquisition of Taiwan-Based Star Semiconductor". cavium.com (Press release).
  7. ^ "Cavium Networks Completes Acquisition of W&W Communications". cavium.com. Archived from the original on 2016-06-13. Retrieved 2020-07-16.
  8. ^ "Cavium Networks Completes Acquisition of MontaVista Software | embedded virtualization" (Press release). December 18, 2009. Archived from the original on 2016-06-12.
  9. ^ McGrath, Dylan (31 January 2011). "Cavium buys Chinese fabless chip firm". EE Times. Retrieved 17 February 2011.
  10. ^ "Company Overview". Celestial Semiconductor. Archived from the original on 2011-03-09. Retrieved 17 February 2011.
  11. ^ "Wavesat | CrunchBase". www.crunchbase.com. Retrieved 2016-07-10.
  12. ^ "Cavium to Acquire Switching and SDN Specialist Xpliant to Accelerate Deployment of Software Defined Networks" (Press release). Archived from the original on 2017-08-03. Retrieved 2019-01-14.
  13. ^ "Company press release: Cavium to Acquire QLogic – Opportunity to drive significant growth at scale in data center and storage markets" (Press release). Archived from the original on 2017-01-14. Retrieved 2017-01-15.
  14. ^ PALLADINO, Valentina (20 November 2017). "Marvell Technology to buy chipmaker Cavium for about $6 billion". Ars Technica. Retrieved 20 November 2017.
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