SBus
 Four SBus slots | |
| Year created | 1989 |
|---|---|
| Created by | Sun Microsystems |
| Superseded by | PCI (1997) |
| Width in bits | 32 |
| No. of devices | 8 masters, unlimited slaves |
| Speed | 16.6 MHz - 25 MHz |
| Style | Parallel |
SBus is a computer bus system that was used in most SPARC-based computers from Sun Microsystems and others during the 1990s. It was introduced by Sun in 1989 to be a high-speed bus counterpart to their high-speed SPARC processors, replacing the earlier (and by this time, outdated) VMEbus used in their Motorola 68020- and 68030-based systems and early SPARC boxes. When Sun moved to open the SPARC definition in the early 1990s, SBus was likewise standardized and became IEEE-1496. In 1997 Sun started to migrate away from SBus to PCI, and today SBus is no longer used.
SBus is in many ways a "clean" design. It was targeted only to SPARC processors so many cross-platform issues were not a consideration. SBus was based on a big-endian 32-bit address and data bus, can run at speeds ranging from 16.6 MHz to 25 MHz, and is capable of transferring up to 100 MB/s. Devices are each mapped onto a 28-bit address space (256 MB). Only eight masters are supported, although there are an unlimited number of slaves.
When the 64-bit UltraSPARC was introduced, SBus was modified to use clock-doubling and transfer two 32-bit data words per cycle to produce a 200 MB/s 64-bit bus. (For contrast, modern 66 MHz/64-bit PCI is 528 MB/s.) This variant of the SBus architecture used the same 96-pin connector as the older one.
SBus was a peripheral interconnect only; Sun systems used another standardized system as a CPU-memory bus, MBus.
External link
- PCI:SBus Comparison (PDF)