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This is an old revision of this page, as edited by Pizzahut2 (talk | contribs) at 00:03, 19 October 2024 (→Release date: changed heading to "Roadmap - release date column"). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

Isn't Westmere just a shrink?

I thought Westmere was only a 32nm shrink of Nehalem, in the same way that Penryn is a 45nm shrink of Merom/Conroe/Woodcrest. If that is the case, then surely it's not a proper CPU microarchitecture?

--Masud 15:17, 25 September 2007 (UTC)[reply]

I made them seperate entries because although Penryn is a 45nm shrink of Merom/Conroe/Woodcrest, there are several changes made. There is more cache, improved power management, faster divisor, etc. Westmere will probably be similar in changes, so I listed it as a sperate uarch. If you don't like how I have it, maybe we could indent those two lines to show that they are improved versions of Core and Nehalem. Imperator3733 19:23, 25 September 2007 (UTC)[reply]
I have two issues.
Firstly, assuming we keep Westmere on the list, Penryn should also feature on the list. This is because they are both shrinks.
Secondly, Intel's "tick-tock" strategy is about introducing a new μarch every two years, and moving to the next manufacturing process in between new architectures. Nehalem is very different from Core, with the QuickPath (formerly called CSI) technology, and interchangeable cores to feature on the same piece of silicon, and more, as I'm sure you know. Compare the difference between Nehalem and Core μarchs, and the difference between Penryn and Core. I can only assume that Westmere will feature incremental improvements to Nehalem in the same way that Penryn features incremental improvements to Core.
My recommendation would be to keep Westmere on this page, indent it as you described, but not call it a microarchitecture, but just a shrink. Also, we should add Penryn to this page, also indented, and also describe it as a shrink. Of course, if there is any Intel documentation that describes Westmere as a separate μarch from Nehalem, then we should keep it as you have done it.
--Masud 11:22, 26 September 2007 (UTC)[reply]

Intel Tick-Tock merge proposal

Someone proposed merging this article and Intel Tick-Tock. I just wanted to state my agreement for such and plans to carry such out in the future if there are is not a consensus against such a move. I believe the Tick-Tock is descriptive of Intel's committed cadence across a number of their more recent CPU microarchitectural and fabrication technology developments and as such makes sense to incorporate it as one or more section(s) within this article (an argument could be made to incorporate this into a list of their fabrication technologies as well but since there is no such article and it so far only applies to their CPU microarchitectures I believe this is currently the most appropriate place). It could further be generalized in to a general roadmap table including parts that have not been part of their tick-tock cadence. 50.53.15.59 (talk) 15:08, 23 July 2013 (UTC)[reply]

My 2 cents: "tick-tock" is obscure/jargony; by contrast "list of Intel CPU microarchitectures" seems clearer. Feldercarb (talk) 23:26, 13 January 2014 (UTC)[reply]

Merged as new section 68.165.77.79 (talk) 04:28, 23 September 2015 (UTC)[reply]

Indentation = shrink ("tock")?

See http://en.wikipedia.org/enwiki/w/index.php?title=List_of_Intel_CPU_microarchitectures&diff=570526280&oldid=570517480 if it's a tock, please revert. "2-way coarse-grained multithreading per core (not simultaneous)" seems to be quite different. Can it still be the same microarchitecture? When is it a new one, if there are tweaks? Always? See also Pendium M and Enhanched Pentium M (take out indent?). Not only a shrink. But minor enhanchments? New instructions(? SSE3 and SSE2) can hardly be minor enhanchments as they imply "new"/enhanched microarchitecture? Maybe th "tock" always includes something more that a shrink? comp.arch (talk) 13:02, 28 August 2013 (UTC)[reply]

Clarkdale/Arrandale?

SO I have an Arrandale cpu in my laptop. By the Wiki article, its desktop counterpart is the Clarkdale. However, its nopwhere to be found on the list. Why is this?207.81.0.235 (talk) 13:24, 20 January 2015 (UTC)BeeCier[reply]

Clarkdale (microprocessor) and Arrandale (microprocessor) are not microarchitectures, but microarchitectures variants. Visite fortuitement prolongée (talk) 20:16, 4 April 2015 (UTC)[reply]

Move from Tick/Tock to Process/Architecture/Optimisation

Is it time to rename the Tick, Tock and semi-Tock to Process, Architecture and Optimisation? Seems to be the new roadmap Intel has adopted. http://www.anandtech.com/show/10183/intels-tick-tock-seemingly-dead-becomes-process-architecture-optimization

Cambookpro (talk) 22:32, 14 April 2016 (UTC)[reply]

Generational chronology road map ?

Even in all Wiki articles about Intel's CPU, there are many references to generational chronology. 8th generation this, 6th generation that... But I can't find any article relating code names to generations, nor exposing such generational chronology by itself. IMHO this article should include it. Simply by adding the column... Thanks. --24.200.214.47 (talk) 22:19, 26 February 2017 (UTC)[reply]

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Roadmap desktop 2021 / mobile 2020

Not sure how reliable this is, also needs translation: https://tweakers.net/nieuws/151984/roadmap-toont-dat-intel-in-2021-nog-desktop-cpus-op-14nm-maakt.html --Pizzahut2 (talk) 10:31, 25 April 2019 (UTC)[reply]

Is the next CPU microarchitecture name "Sunny Cove" or "Ice Lake"?

I guess Intel was using "XXX Lake" names for their microarchitectures starting with Skylake, but Intel now seem to refer to the microarchitecture as "Sunny Cove" and seem to refer to the mobile Sunny Cove processors as having the code name "Ice Lake".

So are the "XXX Lake" names being used for something other than CPU microarchitectures now, e.g. for chips with both CPU and GPU, as Anandtech seems to be suggesting here ("Sunny Cove, built on 10nm, will come to market in 2019 and offer increased single-threaded performance, new instructions, and ‘improved scalability’. Intel went into more detail about the Sunny Cove microarchitecture, which is in the next part of this article. To avoid doubt, Sunny Cove will have AVX-512. We believe that these cores, when paired with Gen11 graphics, will be called Ice Lake.")? Guy Harris (talk) 18:36, 10 May 2019 (UTC)[reply]

x86 microarchitectures table

The table starts with microarchitectures, putting microprocessors into parentheses. Then starting with Penryn, it's suddenly continued with microprocessors instead of microarchitectures. Pizzahut2 (talk) 20:52, 18 December 2019 (UTC)[reply]

Palm Cove?

Is "Palm Cove" a real microarchitecture? The only significant info I could find on it is at WikiChip. Other sources such as Anandtech suggest that it is mostly Skylake microarchitecture with a few additions like AVX-512 and some instructions. Is there any reliable source for Palm Cove? --Vossanova o< 20:05, 4 May 2020 (UTC)[reply]

Which section for Alder Lake?

On May 21st I moved Alder Lake from "Pentium 4 / Core lines" to "Hybrid" since it's a hybrid, but this got reverted May 28th with the reason "it's not the same hybrid as Lakefield, Lakefield Refresh and Ryefield". Recent roadmap: https://heise.cloudimg.io/width/1920//_www-heise-de_/imgs/18/2/9/5/0/5/2/0/Roadmap-318a5c78606a6aa6.jpg --Pizzahut2 (talk) 13:54, 21 August 2020 (UTC)[reply]

Alder Lake is definitely a hybrid, maybe they didn't know that back in May though. A more recent source can be found here, which includes that same roadmap image. It's a bit deceptive to put it in that table below Tiger Lake, because that suggests it's a direct successor to the non-hybrid Tiger Lake, which isn't necessarily true. I don't think Intel has discussed what, if any, processor would be only Golden Cove. So, two options. 1) take it back out, and take Lakefield off the table too, or 2) leave it, and add Alder Lake next to Gracemont as well (that might just make things more confusing without context). --Vossanova o< 20:32, 21 August 2020 (UTC)[reply]
Reading the new article a bit more, Intel considers Alder Lake more of a "performance hybrid" than Lakefield, so it's possible Alder Lake could be a successor to Tiger Lake, just with some extra Gracemont cores (leaked slides suggest up to 8 GC + 8 GM cores). So I'm leaning toward leaving it like it is for now. --Vossanova o< 20:39, 21 August 2020 (UTC)[reply]

P7 codename is ambiguous at best as NetBurst vs Merced

It appears journalists were using the term to reference a 'post-Pentium III' product, both NetBurst and Merced. It is unclear if this is really is official or present in Intel internal designations.

Articles using P7 as Merced

Articles using P7 as a continuance of P6

P7 as Banias & Dothan

Future/speculated processors

I'm okay with future processors going in the Roadmap section, but not in the table at the top of the page. This is the place for verifiable facts of what actually exists in the public eye, not speculation or insider info. So, it should end with what has been released as of present date. A certain anonymous user will disagree with me over and over again, but what does everyone else think? --Vossanova o< 12:49, 30 March 2021 (UTC)[reply]

I don't see a problem with that, that's how I believe things should be with the WP:CRYSTALBALL rule. All the verified info in one place (the main article) and then the future subject-to-change info in a separate place (i.e. the roadmap).
It may look like 100 different users were reverting edits and disrupting the article, but in actuality it was coming all from one user, IP hopping and possibly using open proxies to evade blocks. Highly unacceptable and intolerable behaviour to be honest. That user seems to edit primarily from the 42.190.x.x IP range now, which has now been blocked long-term after I filed a report at ANI for their history of edit wars and personal attacks which continued to this day. AP 499D25 (talk) 14:35, 18 February 2023 (UTC)[reply]

Intel Accelerates Process and Packaging Innovations

Here is an article of the future fabrication process at Intel Accelerates Process and Packaging Innovations. Rjluna2 (talk) 17:24, 28 July 2021 (UTC)[reply]

MMX

The article now says about P6 that is was "First x86 processor to support SIMD instruction with XMM register implemented," I think this is incorrect. The first was Pentium MMX, which added MMX but was otherwise based on P5. See MMX_(instruction_set). The first P6 processor, Pentium Pro, did not include MMX. Page Pentium_Pro notes "However, its lack of MMX implementation reduces performance in multimedia applications that made use of those instructions."

ErkkiRuohtula (talk) 17:07, 1 December 2021 (UTC)[reply]

Intel Roadmap confirms Raptor Lake, Arrow Lake, Lunar Lake, Emerald Rapids

https://www.intel.com/content/www/us/en/newsroom/news/bold-multiyear-xeon-roadmap-accelerate-data-center-leadership-growth.html

https://www.intel.com/content/dam/www/public/us/en/newsroom/posts/inv-day-processor-roadmap-16x9.jpg

https://twitter.com/IanCutress/status/1494448351730937857

https://pbs.twimg.com/media/FL1Y2HFXsAMguSM?format=jpg&name=4096x4096

The leaks were dead accurate, yet small minded people here(they know who they are) removed the codenames because of stupid crystalball rule. Have fun re-adding all those codenames to the article and tables now. And yes, smarter editors like me feel very vindicated that losers at life admins and mods defending that dumb rule are proven wrong again and again. — Preceding unsigned comment added by 42.190.161.224 (talk) 07:36, 18 February 2022 (UTC)[reply]

@42.190.161.224: Of course they couldn't be added, those were only rumors. If they were wrong, then we would have been writing false information. We, as editors, need to follow specific rules. P.S: please sign your messages by using four tildes. Itsquietuptown ✉️📜 13:29, 18 February 2022 (UTC)[reply]
Have a read through WP:CIVIL, please do not attack other editors if you want your voice genuinely heard and talked about. AP 499D25 (talk) 11:46, 17 February 2023 (UTC)[reply]

Raptor Cove/Lake

IMO should be a subitem of Golden Cove. Not really a new arch at all. Also similar if not exactly the same as Sandy Bridge -> Ivy Bridge and SkyLake derivatives. Artem S. Tashkinov (talk) 14:51, 25 October 2022 (UTC)[reply]

Atom roadmap table cluttered with "Un­known"

Might be better to leave these cells blank (or use "?"), so the word "Unknown" isn't spamming the table. Plus it would be easier to add the missing information, because the visual editor can't edit table cells which use table cell templates. Pizzahut2 (talk) 18:33, 23 June 2024 (UTC)[reply]

"Skymont (microarchitecture)" listed at Redirects for discussion

The redirect Skymont (microarchitecture) has been listed at redirects for discussion to determine whether its use and function meets the redirect guidelines. Readers of this page are welcome to comment on this redirect at Wikipedia:Redirects for discussion/Log/2024 June 29 § Skymont (microarchitecture) until a consensus is reached. Jay 💬 01:29, 29 June 2024 (UTC)[reply]

Roadmap - release date column

There are two different dates, a) product launch, where the CPUs appear in Intel's public ARK database and an announcement is made at the newsroom of Intel's website, and b) market availability, usually at the same time globally, and accompanied by reviews (due to the NDA expiring). What is preferable? I guess ideally both dates, but then either the table gets wider or the height of the rows increases a lot (if references and notes are put into an extra line to keep the column width small). Pizzahut2 (talk) 21:25, 11 October 2024 (UTC)[reply]

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