Intel 8086

Intel 8086

General information
Launched	1978
Discontinued	Present
Common manufacturer	Intel
Performance
Max. CPU clock rate	4.77 MHz to 10 MHz
Architecture and classification
Instruction set	x86
Physical specifications
Socket	40 pin DIP

The 8086 is a 16-bit microprocessor chip designed by Intel in 1978, which gave rise to the x86 architecture. Intel 8088, released in 1979, was essentially the same chip, but with an external 8-bit data bus (allowing the use of cheaper and fewer supporting logic chips), and is notable as the processor used in the original IBM PC.

Background

The microprocessor 8086 was intended as a temporary substitute for the ambitious iAPX 432 project in an attempt to draw attention from the less-delayed 16 and 32-bit processors of other manufacturers (such as Motorola, Zilog, and National Semiconductor). Both the architecture and the physical chip were therefore developed very quickly, and were based on the earlier 8080 and 8085 designs with a similar register set. The chip had around 29,000 transistors (many for microcode) and would also function as a continuation of the 8085; although not directly source code compatible, it was designed so that assembly language for the 8085 could be automatically converted into (sub-optimal) 8086 assembly source, usually with little or no hand-editing. However, the 8086 design was expanded to support full 16-bit processing instead of the fairly basic 16-bit capabilities of the Intel 8080/8085.

While arguably not as renowned as the 8088 chip, the legacy of the 8086 is enduring. References to it can still be found on most modern computers - the Vendor entry for all Intel Device IDs is 8086.

Details

Buses and operation

• All internal registers as well as internal and external data buses are 16 bits wide, firmly establishing the "16-bit microprocessor" moniker of the 8086.
• A 20-bit external address bus gives a 1 MB (segmented) physical address space (2²⁰ = 1,048,576)
• 16-bit I/O addresses give 64 KB of separate I/O space. (2¹⁶ = 65,536)
• The control pins carry the essential signals for all kinds of operations. (specific info needed here)

A few comments:

• 8086 instructions varied from 1 to 6 bytes. Therefore, fetch and execution were concurrent (as it remains in modern x86 CPUs): The bus interface unit feeds the instruction stream to the execution unit through a 6 byte prefetch queue, a form of loosely coupled pipelining.

• The data bus, being multiplexed with the address bus, is only slightly diminishing performance as other factors (more important for this particular chip) shadow this design choice; transfers of 16 (or 8) bit quantities are done in a four-clock memory access cycle.

• The performance gain resulting from the full (instead of partial) 16 bit architecture, as well as other enhancements over the 8080 and 8085, is quite significant (despite some cases where the older chips may be faster; see below).

• The maximum linear address space is only 64 KB, simply because internal registers are only 16 bits wide. Programming over 64 KB boundaries involves adjusting segment registers (see below) and is therefore fairly awkward.

Registers and instructions

The 8086 has eight (more or less general) 16-bit registers including the stack pointer, but excluding the instruction pointer, flag register and segment registers. Four of them could also be accessed as eight 8-bit registers (see picture).

Due to a compact encoding inspired by 8085 and other 8-bit processors, most instructions were one-address or two-address operations which means that the result were stored in one of the operands.

At most one of the operands could be in memory, but this memory operand could also be the destination, while the other operand, the source, could be either register or immediate. A single memory location could also often be used as both source and destination which, among other factors, further contributed to a rather small executable code footprint, comparable to most eight bit machines.

Although the degree of orthogonality between registers and operations were greater than in 8085, it were still low, and registers were also sometimes used implicitly by instructions. While perfectly sensible for the assembly programmer, this complicated register allocation for compilers compared to more regular contemporary 16- and 32-bit processors (such as VAX or 68000); on the other hand, compared to contemporary 8-bit processors (such as 8085 or 6502), it was significantly easier to generate code for the 8086 design.

As mentioned above 8086 also featured 64 KB of 8-bit (or alternatively 32 K-word of 16-bit) I/O space. A 64 KB (one segment) stack growing towards lower addresses is supported by hardware; 2-byte words are pushed to the stack and the stack top (bottom) is pointed out by SS:SP. There are 256 interrupts, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the return address.

Segmentation

There were also four segment registers that could be set from index registers. The segment registers allowed the CPU to access one mebibyte + 64 KiB - 16 bytes of memory in an odd way. Rather than just supplying missing bytes, as in most segmented processors, the 8086 shifted the segment register left 4 bits and added it to the offset address, thus:

physical address = segment×16 + offset

The physical memory address was therefore 20 bits wide (while both segment and offset were 16 bits). As a result of this scheme, segments overlapped, making it possible to have up to 4096 different pointers addressing the same location. While acceptable, and even useful, for assembly language programming (where control of the segments was complete) it caused confusion and was considered poor design by most people, forcing entirely new concepts (near and far keywords) into languages such as Pascal and C; data and/or code could be managed within near 16-bit segments, or a large data structure (or many and/or large procedures) could be accessed by far pointers (32-bit segment:offset pairs) reaching the full physical address space.

Although this scheme made expanding the address space to more than 2²⁰ bytes more difficult, it was nevertheless soon expanded by a new MMU-controlled addressing scheme in the 80286's protected mode. Later, and on top of this, 80386 expanded the whole general purpose registers set (and hence, the offsets) to 32 bits, thereby enabling a linear addressing range of 2³² bytes (with a total range of 2³⁶). However, those chips were, for a long period of time, often used in real mode, remaining compatible with older OSes.

In a similar way, early programs could ignore the segments, and just use plain 16-bit addressing, which allowed 8-bit software to be easily ported to the 8086. The authors of MS-DOS took advantage of this by providing an API very similar to CP/M. This was important when the 8086 was new, because it allowed many existing CP/M applications to be quickly made available on the new platform, which greatly eased the transition.

Performance

Execution times for typical instructions (in clock cycles):

Timings are best case, depending on prefetch status, instruction alignment, and other factors.

MOV reg,reg: 2, reg,im: 4, reg,mem: 8+EA, mem,reg: 9+EA,  mem,im: 10+EA cycles
ALU reg,reg: 3, reg,im: 4, reg,mem: 9+EA, mem,reg: 16+EA, mem,im: 17+EA cycles

JMP reg: 11, JMP label: 15, Jcc label: 16 (cc = condition code)

MUL reg: 70..118 cycles
IDIV reg: 101..165 cycles

EA: time to compute effective address, ranging from 5 to 12 cycles.

As can be seen from these tables, operations on registers and immediates were fast (between 2 and 4 cycles), while memory-operand instructions and jumps were quite slow; jumps took more cycles than on the simple 8080 and 8085, and the 8088 (used in the IBM PC) was additionally hampered by its narrower bus. The reasons why most memory related instructions were so slow were threefold:

• The execution and fetch units were loosely coupled; this is efficient for instruction prefetch, but less optimal for jumps and random data access.
• Address generation calculations were largely performed by microcode routines.
• The address and data buses were multiplexed in order to fit a standard 40-pin dual in-line package.

It should be noted, however, that the memory access performance was drastically enhanced with Intel's next generation chips; the 80186 and 80286 both had address calculation in hardware, saving many cycles; 80286 also had separate (non-multiplexed) address and data buses.

It operated 0.33 MIPS, 0.66 MIPS at 8 MHz, and 0.75 MIPS at 10 MHz.

Chip versions

The clock frequency was originally limited to 5 MHz (IBM PC used 4.773 MHz, 4/3 the standard NTSC color burst frequency of 3.579545 MHz), but the last versions in HMOS were specified for 10 MHz. CMOS-versions were manufactured for a long time (at least a while into the 1990s) for embedded systems, although its successor, the 80186/80188, has been more popular for embedded use.

Compatible and, in many cases, enhanced versions were manufactured by Fujitsu, Harris/Intersil, OKI, Siemens AG, Texas Instruments, NEC, and AMD. For example, NEC's series of efficiently implemented 8086 compatible processors (NEC V20, V25, V30, etc) are still used in embedded systems, as are Intel 80186.

The 8086/8088 could be connected to a mathematical coprocessor to add floating point capability. The Intel 8087 was the standard math coprocessor, operating on 80-bit numbers, but manufacturers like Weitek soon offered higher performance alternatives.

Clones

The electronics industry of the Soviet Union was able to replicate the 8086 through both industrial espionage and reverse engineering. The resulting chip, K1810BM86, was pin-compatible with the original Intel 8086 and had the same instruction set. This IC was the core of Soviet-made PC-compatible ES1840 and ES1841 desktops. However, in hardware these computers had significant differences from their authentic prototypes (respectively PC and PC/XT): the K1810BM86 was a copy from Intel 8086, not Intel 8088, and the data/address bus circuitry was designed independently of original IBM products.

An interesting pair of derivatives were the NEC V20 and NEC V30. These were hardware compatible with the 8088 and 8086, respectively, but incorporated the instruction set of the Intel 80186. They were intended to provide drop-in upgrade capabilities to allow manufacturers to upgrade their designs to the new instruction set and faster instruction processing without having to modify their designs.

Notable bugs

8086 CPUs produced prior to 1982 had a severe interrupt bug. IBM provided an upgrade free of charge to affected PCs. Processors remaining with original 1979 markings are quite rare; some people consider them collector's items.

Microcomputers using the 8086

• The most influential microcomputer of all, IBM PC, used the Intel 8088, a version of the 8086 with an eight-bit data bus (as mentioned above).
• The first commercial microcomputer built on the basis of the 8086 was the Mycron 2000.
• The IBM Displaywriter word processing machine and Wang Professional Computer also used the 8086. This chip could also be found in the AT&T 6300 PC (built by Olivetti).
• The Compaq Deskpro used an 8086 running at 7.14 MHz, but was capable of running add-in cards designed for the 4.77 MHz IBM PC XT.

See also

• IBM Personal Computer XT
• x86 architecture

External links

• List of 8086 CPUs and their clones at CPUworld.com