SSE5
The SSE5 (short for Streaming SIMD Extensions 5), announced on August 30, 2007, is a new 128-bit extension to the AMD64 instruction set (itself a 64-bit extension to the 32-bit Intel x86 instruction set) for the AMD Bulldozer processor, due to begin production in 2009.
SSE5 consists of 170 instructions, many of which are designed to improve single-threaded performance. Some SSE5 instructions are RISC-inspired 3-Operand Instructions, the use of which will increase the average number of Instructions Per Cycle achievable by x86 code.[1] Select new instructions include:[2]
- Fused multiply accumulate (FMACxx) instructions
- Integer multiply accumulate (IMAC, IMADC) instructions
- Permutation and conditional move instructions
- Precision control, rounding, and conversion instructions
AMD claims SSE5 will provide dramatic performance improvements, particularly in high performance computing (HPC), multimedia and computer security applications, including a 5x performance gain for AES encryption and a 30% performance gain for DCT used to process video streams.[1]
References
See also
External Links
- A New SSE Instruction Set: AMD Announces SSE5, AnandTech, August 30, 2007, accessed August 30, 2007.
- AMD Announces SSE5 Instruction Set, DailyTech, August 30, 2007, accessed August 30, 2007.