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User:Ramu50

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This is an old revision of this page, as edited by Ramu50 (talk | contribs) at 16:59, 21 June 2008. The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

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Personal Subpages (DO NOT EDIT)

Resources (for Wikipedians) ---Try to view only, Don't edit or republish

 --Each cateogry is subdivied

Introduction

(About Me)
Proud to be Canadian
Religious Viewpoints: God is only needed for the people that are lazy and can't expect the
unexpected, if god is perfect then science is perfect, hence life = flawed, so therefore
God is an outdated philosophical aspect of imagination and brainwashing.

To Do List

Improve unprofessional page  Computer Hardware, Extensible Firmware Interface

Cleanup ARMD-HDD and re-check historical non-fiction being deleted intentionally from users stealing page.

Host Controller Interface Expansion.


Research Project

News 3D Rendering method

Traditional Rendering
---2D Rendering: (Photoshop, Illustraotr, CorelDraw)
---3D Rendering: (Maya, Solidworks)
---Game Rendering

2D Design
-each layer is modify with specific technologies (effects)
relationship: layer = (planes / axis) + technologies
-----however, when several layer is overlayed together, the layers doesn't interact and the technologies is soley depedant on elements, that is why 2D graphics aren't able to deliver realistic effects<br/><br/>

elements (meaning the technologies that is use to makeup the colors) e.g. Pixels [RBG], CMYK, and Vector Grahpics


3D Design
-quality of image is dependant API based
-the element doesn't have a defined properties
-the interaction speed is depedant on the Systematic Management of dividing each part of code into algorithmic, floating point or numeric (& the Parallelis at each layer of code...ILP)
-the physics of interaction act too independantly, they dont act as a unity that is why object can pierce through another object when falling

Logs of Wikipedia Discussion

Please DO NOT edit this Section, use bullet list if you want to add something

Central Processing Unit -True CPU (MAJC)

---see MMOFPS, WarRock discussion for more info
---see MAJC & VLIW in Wikipeida


Creator of Facebook: Comptuer Chipset Architecutre Groups


Xfire: casanova3000s


Free Info Just for the fellow memeber of Wikipedia

List of Notebooks

High Ends / Buisness

Next Computing, Vigor Evo HD (suitcase)
   8 cores from Intel Xeon / AMD Operton
   patented FleXtreme architecture, COTS software and hardware
   PCI-X 64 bit slot, 3TB hard disk

Cizmo, CX15 [Centrino 2]               German notebook vendor
    -Core 2 Duo & Core 2 Quad

Dell XPS, Latitude
Alienware area m15x
Rock, Xtreme SL8 (SLI)
Asus G series (G70) (SLI)               Core 2 Duo, Core 2 Extreme
HP Pavillon, Presario
Beyond, GoFlex317
Acer Aspire
Panasonic Toughbook
Samsung, Q1 Ultra.
Sony, Vaio
BenQ, Joybook
Dell, Precision (M2300, M4300, M6300)
Asus, Lamborghini VX3
???FTEC, Smartbook
???DRS Armor C12
Frontier, FRNL                     (lighter than MacBook Air)
Kohjinsha, SR8
Dialogue Technology, Flybook V5
Dreamcom Corp, DreamCom Series 10
Toshiba Satellite (some are SLI)


Medium Range
Nec, LaVie J series                  (Core 2 Duo, 1.2GHz)
Sungjt, TangoX Nano                  (Via C7-M, 1.2 GHz)
MacBook Air
Everex Cloudbook
Toshiba
    Satellite                     Core 2 Duo, Pentium Dual core Athlon, Turion 64X2
    Satellite Pro                  Core 2 Duo (1.7~2.1GHz)    Turion 64 X2 (2.0GHz)
    Qosmino (not a series)             Core 2 Duo (1.8 GHz)
Pioneer, Dreambook Light IL1(SSD)          (Via C7-M 1.5GHz)

Extremely Low End
Norhtec, “Gecko”                     (Via C7)
Asus Eee PC
   Celeron M
   FingerGlide technology
Kohjinsha, SA series                  (AMD Geode processor LX800 [500MHz])
Elonex One                       (educational) 300MHz CPU

OLPC


List of Hard Drive Technologies

Encryption, Security Implementation
Bull, Globull
    -CIK (Crypto Ignition Key) technology
    -keys stored in cryptographic processor only
    -cryptographic processor encrypt data at 100Mbp, using AES

Iomega, Camouflage 250GB [portable Hard-Drive]
     -DropGuard technology, protect from physical shock

Fujitsu & Phoenix Technologies (remote control capabilities)
     -Phoenix FailSafe technology [remotely protects & encrypt]
     -FDE [Fujitsus’, Full-Disk Encryption]

Radion Technology---StarRay [subsidiary] (S-series)
     -divide storage space into2 parts (public & encrypted) called X-Zone
     -3 options: software password, fingerprint, keypad password

Hitachi Global Storage Technologies & PMC-Sierra
     -SAS (Serial Attached SCSI) 6Gb/s chipset
     -include Tachyon SPC 8 * 6 SAS protocol controller
     -8 * 6 RAID-on-Chip controller

Western Digital, technology in GreenPower series
    -SATA drives (RE2-GP) WD Caviar GP 500GB
     -500GB~1TB (5 watts only)

     -entire series is Energy Star 4.0 compliant
     -IntelliPower, balance spin speed, transfer rate, and cache size for power savings
     -IntelliSeek (use to calculate optimum seek speeds to lower power consumption,noise
     and vibration)
-IntelliPark (lower power consumption by automatically unloading heads during idle to
    reduce aerodynamic drag)
    -Active Power Management, monitor the drives’ status and send it sleep whenever
    possible, when require disk recover from idle mode in less than 1 second
    -??uses IntelliPower caching algorithms




Typical hard drive require 13.5 watts


Future To Do List

Section: CPU
(move from Chipset dicussion) discussion started by ramu50 Most people today don't know that CPU itself doesn't run in GigaHertz, the Gigahertz is calculated by (ALU + NPU + FPU) *FSB* max IOPS = CPU speed (Note: my calculations may not be correct, but I know it is through some sort of forumla). Hence it is assist by chipset to achieve that speed. ALU, NPU and FPU are the internal core of CPU and initally round around 300MHz thus proceed onto 800MHz. Strictly speaking CPU and all the other families of RISC, MIPS are not processors at all, they are microprocessor. The only true CPU is MAJC, because it can handle ANY type of data. 19:59, 27 May 2008 (UTC)

[Error statement fixed]~~~Sorry for the inconvience--Ramu50 (talk) 19:54, 29 May 2008 (UTC)

Uh... what??? Do you have any reference for that? Are you talking about the use of clock multipliers or something? Your statement about MAJC being the only "true processor" makes no sense; traditionally, the distinction between a "processor" and a "microprocessor" was that the former was implemented with discrete logic (SSI or MSI chips), while the latter was implemented in a single VLSI chip. ǝɹʎℲxoɯ (contrib) 22:12, 27 May 2008 (UTC)
Nope, CPUs certainly do run in the GHz range (IBM Power6) and GHz is certainly not calculated by "(ALU + NPU + FPU) *FSB* max IOPS = CPU speed". Chipsets have nothing to do with "assisting" the CPU to achieve high rates. There are processors such as the DECchip 21064, that take an external clock signal from a crystal oscillator before divinding it and outputing it as the system clock to the chipset. As for your claims that on MAJC is the only "true processor" becuase it processes all types of instruction in one unit simply does not make sense. The MAJC has circuitry that is not shared between different instructions (fixed point, floating point) just like any other processor, except for that the other processors separate the circuitry used for each type of instruction into units. Rilak (talk) 08:58, 28 May 2008 (UTC)

Sorry I meant by the current design architecture isn't a CPU. MAJC is a CPU, while the current CPU should be considered as a microprocessor, sorry I said before "The only true processor is MAJC" I forgot to add the word "Central."

CPU = Central Processing Unit and Central = Management, well when you are processing intensive logic processing (you get something like this 80% APU, 18% NPU, 2% FPU), is that management? Unable to balance it efficiently thus producing 45~50 degree Celsius of heat is not management. The design architecture of MAJC is they can handle any type of data, in one single unit, they don't require subunit and in processing sometimes you get interlocks, C = A + B, E = C + D where the second instruction must be read before the entire thing can be process. In a regular CPU today, you have NPU doing all the work while the ALU + FPU is doing nothing, but in MAJC the entire unit is processing thus, require less power because the amount of processing require is distrbuted evenly. Says if the previous interlocks require 2 clock cycle, both MAJC and CPU are capable with scheduling something that takes only less than 2 clock cycle.

But the problem arise is what happen when you are doing abstraction (in graphics) when most of the data are arthimetic, then you can't schedule because the NPU is full, but in MAJC each transistor is only partial work so they are able process more work thus able to manage things more efficiently.

MAJC I think isn't recognize today, because I think they just started in 1990s and they are still researching on processor technologies (like Intel Extended Memory 64 technology, SpeedStep...etc.). But I think the industry should recognize the architecture of MAJC, because if the current Intel, AMD, Via, IBM, PowerPC is consider a CPU, then explain to me what difference is it between a GPU, NPU (Network Processing Unit in Killer NIC). GPU has a subunit NPU and FPU, just because it has less subunit doesn't mean its central, each processor has its own different function so which subunit they need is obviously different from each other.

  • Forget about the CPU in Gigahertz, I didn't save my the source, plus that was about 3 years ago when I found it. --Ramu50 (talk) 18:10, 29 May 2008 (UTC)
I am afraid I don't understand what NPUs (I assume that NPU in this context refers to Network Processing Unit) has to do with CPUs or why APU (ALU?), FPUs, GPUs and NPUs are the same thing. This discussion is also getting a little off topic (this talk page is for the discussion of how to improve the article about Chipsets) but if you wish, you can take it to my user talk page. Rilak (talk) 07:04, 30 May 2008 (UTC)

FPU, ALU, NPU in CPU subunits is known as
FPU = Floating Point Processing Unit
ALU = Alogrithmic Processing Unit (meaning logic)
NPU = Numeric Processing Unit

Common ones GPU Graphic Processing Unit (currently being considered as a partial APU, because of the discovery of Geometric mapping of sound DSP (Digital Signaling Processor)--use in Optical Mouse


APU = Audio Processing Units
PPU = Physics Processing Unit (very dependant)
NPU = Networking Processing Unit (see BigFoot Network, Killer NIC cards)

I think this is more related to CPU, NOT chipset. I will move this entire discussion to CPU discussion. --Ramu50 (talk) 16:04, 30 May 2008 (UTC)