POWER6
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The POWER6 microprocessor is IBM's follow-on to the POWER5. It is part of the eCLipz project, said to have a goal of converging IBM's server hardware where practical (hence "ipz" in the acronym: iSeries, pSeries, and zSeries).[1]
POWER6 was described at the IEEE International Solid-State Circuits Conference (ISSCC) in February 2006, and additional details were added at the Microprocessor Forum in October 2006[1] and at the next ISSCC in February 2007. It was formally announced on 21 May 2007 [2].
Description
The POWER6 has approximately 790 million transistors and is 341 mm² large fabricated on a 65 nm process. It was released on the 8th June 2007, at speeds of 3.5 GHz, 4.2 GHz and 4.7 GHz[2], but the company has noted prototypes have reached 6 GHz.[3] POWER6 reached first silicon in the middle of 2005[4], and bumped to 5.0 GHz in May 2008.[5]
Dr Frank Soltis, an IBM chief scientist, said IBM had solved power leakage problems associated with high frequency by using a combination of 90 nm and 65 nm parts in the POWER6 design.[6]
The processor is a dual core design and has 128 KiB of L1 cache (64 KiB data + 64 KiB instruction), an eight-way set-associative design with a two-stage pipeline supporting two independent 32-bit reads or one 64-bit write per cycle.[7] Each core will have a 4 MiB "semi shared" L2 cache, where the cache is assigned a specific core, but the other has a fast access to it. The two cores share a 32 MiB large L3 cache which is off die, using an 80 GB/s bus.[8]
Each core has two integer units, two binary floating-point units, and a novel decimal floating-point unit, and is capable of two way SMT. The binary floating-point unit incorporates “many microarchitectures, logic, circuit, latch and integration techniques to achieve [a] 6-cycle, 13-FO4 pipeline,” according to a company paper.[7] Unlike the servers from IBM's competitors, the POWER6 has hardware support for IEEE 754 decimal arithmetic and includes the first decimal floating-point unit integrated in silicon. More than 50 new floating point instructions handle the decimal math and conversions between binary and decimal.[8] This is a feature also added to the processors powering IBM's System z.[9]
There is an AltiVec unit to POWER6, and the processor is fully compliant with the new Power ISA v.2.03 specification. POWER6 also takes advantage of ViVA-2, Virtual Vector Architecture, which enables the combination of several POWER6 nodes to act as a single Vector processor.[9]
A notable difference from POWER5 is that IBM moved from an out-of-order design to an in-order design, a change which often requires software recompilation for optimized performance. However, the processor still achieves significant performance improvements even with unmodified software, according to the lead engineer on the POWER6 project.[10]
IBM also makes use of a 5 GHz duty-cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire that is 3 µm wide and 1.2 µm thick. The POWER6 design uses dual power supplies, a logic supply in the 0.8-to-1.2 Volt range and an SRAM power supply at about 150-mV higher.[7]. The thermal characteristics of POWER6 are similar to that of the POWER5.
POWER6 can connect to up to 31 other processors using two inter node links (50 GB/s), and supports up to 10 logical partitions per core (up to a limit of 254 per system). There is an interface to a service processor that monitors and adjusts performance and power according to set parameters.[11]
POWER6 includes many innovative features for improved reliability and energy saving (see list of recommended reading below).
Rather than develop different versions of POWER6 for different applications, IBM can produce different configurations of the chip (0, 1 or 2 on-chip L3 cache controllers, 1 or 2 on-chip memory controllers) for deployment in different servers. Different chip packaging is also used for price/performance reasons.
Products
The current range of POWER6 systems (as at 7 October 2008) include "Express" models (the 520, 550 and 560) and Enterprise models (the 570 and 595). Power Systems.[3]. The various system models are designed to serve any sized business. For example, the 520 Express is marketed to small businesses while the Power 595 is basically a mainframe. The main difference between the Express and Enterprise models is that the latter include Capacity Upgrade on Demand (CUoD) capabilities and hot-plug processor/memory "books". All Power systems are noted for their huge expansion and storage capabilities.
IBM also offers two POWER6 based single wide blade servers, the JS12 and the JS22 blade module.[4] The JS12 is equipped with two 3.8GHz Power 6 cores while the JS22 has four 4.0GHz Power 6 cores. Both blades support AIX, i, and Linux. The BladeCenter S and H chassis is supported for blades running AIX, i, and Linux. The BladeCenter E, HT, and T chassis support blades running AIX and Linux but not i.
At the SuperComputing 2007 (SC07) conference in Reno a new water-cooled Power 575 was revealed. The 575 is composed of 2U "nodes" each with 32 POWER6 cores at 4.7 GHz with up to 256 GB of RAM. Up to 448 cores can be installed in a single frame.
See also
- IBM POWER
- Power Architecture
- POWER7
- z10, a mainframe processor sharing much technology with the POWER6.
References
- ^ "A Mainframe Roadmap". Isham Research. Retrieved 2005-06-15.
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- ^ "IBM POWER system hardware". [IBM]. Retrieved 2008-10-09.
- ^ "IBM's Power6 Processors to Hit 5.6GHz". The Register. Retrieved 2006-02-07.
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- ^ "IBM's Power6 Gets First Silicon as Power5+ Looms". IT Jungle. Retrieved 2005-08-22.
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- ^ "IBM smacks rivals with 5.0GHz Power6 beast". The Register. Retrieved 2008-10-12.
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- ^ Roger Howorth (2006-02-08). "IBM's Power6 processor to run at 4GHz in 2007". IT Week.
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- ^ a b c "IBM Tips Power6 Processor Architecture". InformationWeek. Retrieved 2006-02-06.
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- ^ a b "Fall Processor Forum: Power6 at 5 GHz". Heise online. Retrieved 2006-10-12.
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- ^ a b "An eCLipz Looms on the Horizon". Real World Technologies. Retrieved 2005-12-19.
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- ^ "IBM POWER system hardware". [IBM]. Retrieved 2008-10-09.
- ^ "IBM cranks dual-core Power6 beyond 4GHz". EETimes. Retrieved 2006-10-10.
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External links
- Oracle Sets New World Records for 4-Core and 8-Core Performance in Two-Tier SAP Sales and Distribution Standard Application Benchmark, 24 MAY 2007
- IBM Press Kit
- IBM's Power6 doubles speed
- IBM Unleashes World's Fastest Chip in Powerful New Computer, 21 May 2007
- InformationWeek report on the Power6 announcement
- Real World Tech, Dec 19, 2005
- InformationWeek, Feb 6, 2006
- C|Net, Oct 10, 2006
- Heise Online, Oct 12, 2006
- Real World Tech, Oct 16, 2006
- Arstechnica, Oct 19, 2006
- Arstechnica, Feb 12, 2007
- Arstechnica, May 21, 2007
- The POWER6 microarchitecture, November 2007. IBM.com
Recommended reading
- POWER Roadmap, IBM, Oct 2006
- IBM POWER6 Reliability, IBM, Nov 2007
- IBM POWER6 microprocessor physical design and design methodology, IBM, Nov 2007
- EnergyScale for IBM POWER6 microprocessor based systems, IBM, Nov 2007
- System power management support in the IBM POWER6 microprocessor, IBM, Nov 2007
- IBM POWER6 microarchitecture, IBM, Nov 2007
- IBM POWER6 SRAM arrays, IBM, Nov 2007
- IBM POWER6 accelerators: VMX and DFU, IBM, Nov 2007