Ne-XVP
Ne-XVP was a research project performed between 2005-2008 at Philips Semiconductors and later at NXP Semiconductrs. The project undertook a holistic approach to define a next generation multimedia processing architecture for embedded MPSoCs that targets programmability, performance scalability, and silicon efficiency in an evolutionary way. The evolutionary way implies using existing processor cores such as NXP TriMedia as building blocks and supporting industry programming standards such as POSIX threads. Based on the technology-aware design space exploration, the project concluded that hardware accelerators facilitating task management, coherency and right dimensioning of compute cores deliver good programmability, scalable performance and competitive silicon efficiency.
Ne-XVP's research subjects and corresponding publications:
- Asymmetric multicore architecture with generic accelerators [1]
- Hardware Multithreading in VLIWs [2]
- Low-complexity cache coherence [1]
- Instruction Cache sharing [1]
- Hardware accelerators for task scheduling and synchronization:
- Design Space Exploration with Performance Density as the optimization function [1]
- Technology modeling for embedded processors [5] [6]
- Parallelization of complex multimedia algorithms (H.264, Frame Rate Conversion) [7] [8]
History
The project consisted of:
- Ghiath Al-Kadi
- Zbigniew Chamski
- Dmitry Cheresiz
- Marc Duranton (project leader)
- Surendra Guntur
- Jan Hoogerbrugge
- Anirban Lahiri
- Ondrej Popp
- Andrei Terechko
- Alex Turjan
- Clemens Wust
- ...
References
- ^ a b c d A. Terechko, J. Hoogerbrugge, G. Alkadi; S. Guntur; A. Lahiri; M. Duranton; C. Wust; P. Christie; A. Nackaerts; A. Kumar, "Balancing programmability and silicon efficiency of heterogeneous multicore architectures", ACM Transactions on Embedded Computing Systems, Special Issue on Real-time Multimedia, 2010.
- ^ a b J. Hoogerbrugge, A. Terechko, "A multithreaded multicore system for embedded media processing", Transactions on High-Performance Embedded Architectures and Compilers, Volume 4, Issue 2, 2008.
- ^ G. Al-Kadi, A.S. Terechko, "A Hardware Task Scheduler for Embedded Video Processing", in Proceedings of the 4th International Conference on High Performance and Embedded Architectures and Compilers, Paphos, Cyprus, January 25-28, 2009.
- ^ M. Sjalander, A. Terechko, M. Duranton; A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures; Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools; Pages 149-157; 2008; ISBN:978-0-7695-3277-6; IEEE Computer Society Washington, DC, USA.
- ^ A. Terechko, J. Hoogerbrugge; G. Al-Kadi; A. Lahiri; S. Guntur; M. Duranton; P. Christie; A. Nackaerts; A. Kumar, “Performance Density Exploration of Heterogeneous Multicore Architectures”, invited presentation at Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO’09), January 25 2009, in conjunction with the 4th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Paphos, Cyprus, January 25-28, 2009.
- ^ P. Christie, A. Nackaerts, A. Kumar, A. S. Terechko, G. Doornbos, “Rapid Design Flows for Advanced Technology Pathfinding”, invited paper, International Electron Devices Meeting, San Francisco, 2008.
- ^ G. Al-Kadi, J. Hoogerbrugge, S. Guntur, A. Terechko, M. Duranton, “Meandering based parallel 3DRS algorithm for the multicore era”, in IEEE International Conference on Consumer Electronics, Las Vegas, USA, January 11-13, 2010.
- ^ A. Azevedo, B. Juurlink, C. Meenderinck, A. Terechko, J. Hoogerbrugge, M. Alvarez, A. Ramirez, M. Valero, “A Highly Scalable Parallel Implementation of H.264”, in Transactions on High- Performance Embedded Architectures and Compilers, Volume 4, Issue 2, pp. 404-418, 2009.