Talk:MCS-51

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64k of memory, eh?

How is it possible to adress 64k each of RAM and ROM (that would equal 128k in total) with a 16 bit adress bus? Is there a line on the control bus or something to deal with a simple bank-switch kind of thing? Wilsonsamm (talk) 20:08, 2 October 2008 (UTC)[reply]

The 8051 has a Harvard architecture. Please follow the corresponding link in the article. --89.15.178.202 (talk) 20:48, 26 November 2008 (UTC)[reply]

8051 architecture

Is 8051 a CISC or RISC machine? Is 8051 a Harvard architecture? —The preceding unsigned comment was added by 61.17.44.86 (talk) 08:05, 29 January 2007 (UTC).[reply]

The 8051 is defintiely a CISC machine. It's instruction set is wide and varied with lots of addressing modes and only a few registers. RISC machines typically have a much smaller instruction set and a bank of 16 or 32 registers. RISC machines typically only operate on data in the registers and have a "load/store" architecture. The 8051 instruction set mostly operates on the Accumulator and values in memory. Thus, the 8051 is CISC.

The 8051 is considered a Harvard Architecture machine because it has separate code and data spaces. Depending on the implementation however, it can be either Harvard or von-neumann. Older versions of the 8051 are more often van-neumann in that the CPU takes several clock cycles to fetch each operand/instruction individually. Newer single-cycle 8051s are often Harvard so they can get higher performance. The Harvard architecture allows the Instruction and the operands to be fetched in the same cycle. 68.189.241.68 (talk) 14:28, 24 February 2008 (UTC)[reply]

At least with the ROM based variants, the original 8051 could be considered Harvard (and was described as such in the microprocessors course I took in college) in that you could not read from the program address space with normal data read instructions. It was its own address space, and one presumes there was a separate, dedicated path for program fetches. There are special "table lookup" instructions that allow you to read data from the program space, though. Also, on external fetches, the original 8051 CPU would indicate whether it was fetching program or data, so you could continue to keep those address spaces separate even for external memory. That said, once accesses go over the external bus, program and data busses are merged and so are no longer separate busses, and so it does look von Neumann-ish at that point. If a given design ignores the program/data indicator, the two address spaces merge for those external fetches, like in any other von Neumann-style architecture. Note that I limit my comments to the original 8051. I haven't used any of the modern variants so I cannot comment on them. --Mr z (talk) 07:03, 3 September 2008 (UTC)[reply]

8051 has a von Neumann architecture nad not the Harvard architecture —Preceding unsigned comment added by 123.238.27.95 (talk) 19:32, 7 December 2008 (UTC)[reply]

thank you intel —Preceding unsigned comment added by 217.219.35.2 (talk) 06:31, 13 May 2009 (UTC)[reply]

license

I heard a rumor that the 8051 has somehow fallen into the public domain. Is that true? If so, this processor should be listed at open hardware#CPU. Or is Intel still selling the 8051 design under NDA licenses, even though it no longer fabs the chip? Something like ARM Holdings sells CPU designs but does not fab any chips? --68.0.124.33 (talk) 14:13, 13 August 2009 (UTC)[reply]

Various versions

Could we start listing various versions and manufacturers here somehow? A few have wp pages and links lead here but there's no line back to specific/super/modern versions. — Preceding unsigned comment added by Blades (talk • contribs) 12:43, 22 October 2009 (UTC)[reply]

I don't think that such details are desirable in an encyclopedia article. Lists of such details seem to me to be contrary to the general spirit of several sections of Wikipedia:What Wikipedia is not, even though, as far as I know, this particular case is not explicitly mentioned there. JamesBWatson (talk) 14:05, 24 October 2009 (UTC)[reply]

Memory architecture

The discussion of the memory architecture could use a little more detail. There is direct RAM, indirect RAM, SFR's, external RAM, and program memory, plus the bit-addressable feature of part of the RAM and some of the SFR's. I will add a section to the article in the near future, as it seems important to understanding the architecture. Pfagerburg (talk) 05:06, 13 November 2009 (UTC)[reply]

Instruction set mnemonics possible copyvio?

I disagree that a processor instruction set is copyrightable.

However, Intel has claimed (still does claim?) copyright on the 8051 instruction set, and I am unsure if its inclusion in this article is allowable, even with the copyright notice included. (It certainly doesn't say "used by permission.") Template:Cv-unsure I'm also not sure that section belongs in the main article anyway, c.f. Atmel AVR and Atmel AVR instruction set. Regards, Pfagerburg (talk) 05:19, 13 November 2009 (UTC)[reply]

I don't think we need pay too much concern to this issue. For a start it the intention behind behind claiming copyright on an instruction set is to prevent copying of the instruction set (i.e. prevent the manufacture of clone devices), not to prevent documentation of that instruction set. However, it is also now generally accepted that instruction sets are not copywritable, as evidenced by the range of x86 and indeed 8051 clones. As even Intel acknowledge at [1] (section 2.1.1):

While any imitator of the Intel Architecture can provide the CPUID instruction...

That is a slightly different context since it does of course refer to the x86 architecture, but it is exactly the same issue. CrispMuncher (talk) 13:17, 13 November 2009 (UTC)[reply]