Talk:Flip-flop (electronics)

T flip-flop

Could the explanation for a T flip-flop be expanded? Is Q updated every clock cycle? What does it mean "the input is strobed" - the clock or T?by Ny7K 131.111.8.102 22:59, 13 November 2005 (UTC)

There's a sentence in the T flip-flop section that isn't even a sentence:

A toggle flip-flop composed of a single SR flip-flop that becomes an oscillator, when it is clocked.

I'm not sure how to fix it because I don't know what was meant. The next sentence is confusing also. I'd be for dropping that, and the next two sentences:

To achieve toggling, the clock pulse must have exactly the length of half a cycle. While such a pulse generator can be built, a toggle flip-flop composed of two SR flip-flops is the easy solution.

Is the single SR flip-flop implementation actually useful in any practical situation? Can someone provide a citation?

Ccrrccrr (talk) 04:09, 27 February 2008 (UTC)

Indeed, that's lame. So I took it out. If someone figures out something to say there, put it in. Dicklyon (talk) 05:01, 27 February 2008 (UTC)

Flip flop or flip-flop

The correct, or at least "electronics industry-standard" terminology is "flip-flop," that is, with the hyphen.

Chambers Science and Technology Dictionary and the OED agree with you. -- Heron

I now replaced "flip flop" with "flip-flop" in the whole text. Should the page also be moved to "flip-flop"? We would need to first delete the redirect in the other direction in that case. Colin Marquardt 13:45, 28 Aug 2003 (UTC)

Well, I did a cut and paste move. I couldn't find a page where I could request a move or delete the redirect. 172.196.215.224

Circuit diagrams

Some circuit diagrams would be extremely helpful here, but I'm not qualified to draw them... can someone with a bit more knowledge of electronics put one in? Kwertii 22:13, 27 Nov 2003 (UTC)

I will try to modify Heron's for the other types. - Omegatron 18:58, Jul 5, 2004 (UTC)

I added the Q' for JK and SR, since they are always shown that way. T and D often are, too. We should probably add timing diagrams and NOR circuits, too, right? - Omegatron 19:31, Jul 5, 2004 (UTC)

Truth tables

I would like it to have "truth tables". I started one for RS. There are different ways of representing it, though. I have included two. Probably the explicit type is better. Feel free to remove or modify or whatever. I wanted to set the outputs apart from the inputs, though, and just made it bold for now. there is a better way, involving tables. I am going to try to do these symbols, first, though. - Omegatron 18:58, Jul 5, 2004 (UTC)

http://www.rfcafe.com/references/electrical/flip_flop_table.htm

http://poppy.snu.ac.kr/~kchoi/class/lc_intro/sequential.pdf

T flip-flop equation

The characteristic equation for a T flip-flop is given as $Q_{next}={\overline {Q}}$. Should this be $Q_{next}=T\oplus Q$? Josh Cherry 23:57, 17 Sep 2004 (UTC)

It's not right the way it is. I don't remember what that symbol is, but if the truth table matches, then yes, change it (and remind readers like me what the symbol means, with a link to appropriate article). - Omegatron 03:38, Sep 18, 2004 (UTC)

Looks like xor, judging from the truth table...

Internal Composition

What's inside? A Flip-flop is treated as a black box in this article. Can we add something about logic gates and transistors and describe how they allow the Flip-flop to function as it does? - Lokiskoll 09:51, Dec 17, 2004 (EST)

Different clocking types

This article does not explain the difference between flip-flops which are level sensitive (e.g. latches), master/slave, or edge sensitive. Anon April 26, 2005

Moreover, it's totally incorrect to structure flip-flop by timing type and then by functioning type, 'cause these two are different types of classification. E.g. an RS flip-flop can be both level- and edge-triggered.

We should first consider functioning types and then place a chapter "Level-triggered and edge-triggered flip-flops"

btw i'm going to handle this when it's summer and i have some spare time :^) Ivan Pozdeev 15:08, 25 May 2006 (UTC)

J-K flip flop naming a myth?

A recent Slashdot post mentioned the possibility that J-K flip flops were not actually named after Jack Kilby. Does anyone buy this?

His name will forever be engraved in the J-K flip-flop.

This is probably an urban legend. More likely it was the initials of John J. Kardash [google.com], who in the 1950's arbitrarily used his initials on these pins on his blueprints, and it stuck.

(quoted from Slashdot post #12877710; see the Google Answers result for more information) - McCart42 (talk) 17:52, 2005 Jun 22 (UTC)

This should be fixed here as well as the kilby page and the Integrated circuits page. By fixed I mean either removed or finding some fairly reputable source for the information and citing it. Danny31415 4 July 2005 10:37 (UTC)

Presumably the above was written before the note about Dr. Nelson was added to the flip-flops page. I was at Hughes Aircraft at the same time as Dr. Nelson, and can confirm the origin there of the J-K flip-flop. Neither Kilby nor Kardash had anything to do with it.MontyPh 18:05, 10 January 2007 (UTC)Montgomery Phister

Back in 82 when I was in school, the prof claimed it was named after John Kardash. Google search (http://taracom.net/chip.pl?to=management) shows that John Kardash claims he invented the JK flip flop. I agree that the Jack Kilby surmise is unwarranted and should be removed, and at least replaced with John Kardash's version of events. One thing in John Kardash's favor is that TI was in the position to influence a lot of minds, as they sold JK flops by the bucket-load (and probably gave away nearly as many data books!). The idea that Hughes was able to establish industry-wide practice via their internal naming convention is far less plausible. Really, if it comes down to Mr. Nelson's claim vs Mr. Kardash's claim, I don't see why Mr. Nelson would get priority. —Preceding unsigned comment added by 70.253.67.240 (talk) 08:44, 24 December 2008 (UTC)

Ambiguous term?

There seem to exist at least two meanings of the term flip-flop:

1. A generic term for all bistable devices, including direct latch, gated latch and edge-triggered devices
2. Edge-triggered devices only. Datasheets tend to follow this convention

I believe the latter is the only correct use. Ed de Jonge 11:44, 10 March 2006 (UTC)

The latter is the only correct term. It makes no sense to refer to something "flipping" and "flopping" without a trigger. Latches are transparent. Flip flops are semi-transparent. The page needs major updating. —TedPavlic (talk/contrib/@) 21:21, 16 July 2009 (UTC)

I aggree the latter is "correct" in the sense that it is the convention used in datasheets, and also taught at many universities. However, this is very arbitrary, as it has little to to with technical meaning or historical usage of the words; it also seem to have resulted in widespread confusion, also in wikipedia articles - the bistable circuit called SR latch, under "latch", is exactly the same cross coupled NAND-gates as is described as a RS flip-flop in this article; other parts of the texts are carefully trying to explain the (arbitrary) distinction between the two names.

Dare I suggest that this confusion is partially due to the tradition (in English) of assigning very,very precise meanings to simple words, instead of specifying the exact meaning by a few extra words when actual usage calls for it ? I wouldn't know for sure, as I'm obviously no native english speaker.

However, if the edge-triggered characteristic differentiates flip-flops from latches, it would be wrong to state that the flip-flop was invented in 1919 by William Eccles and F. W. Jordan, as this circuit was built by only two triodes - a minimalistic clock-less bistable circuit - despite this, named "flip-flop". There has also been other types of "flip-flops", such as those built by relays (which sounded "flip" and "flop" as well...), long before edge-clocked devices, such as 7473 and the like, became mainstream.

The distinctions between the common bistable elements could just as well be spelled out explicitly:

• simple SR latches
• gated (transparent) latches
• pulse-clocked (i.e. master-slave) latches
• edge-clocked latches

All of which may have JK, D, and other variations

The word "latch" may be replaced by words like "bistable", "register", "flip-flop", or even "memory".

Not very surprisingly, I suggest a MERGE of the latch and the flip-flop articles.

I also belive the article should mention that bistable elements can be built in more than one way, even if we restrict ourselves to electronics; logic gates is one way, discrete bipolar transistors another (old fashioned), and CMOS transmission gates mixed with ordinary CMOS gates, a third. - HenkeB 11:55, 9 June 2006 (UTC)

I second that. However, the widespread convention of only referring to edge-triggered devices as flip-flops should be visibly acknowledged (maybe even within the discussion of every individual variation) to avoid confusion and (inadvertent) edit wars. Also, I have to say that I really like the term "latch" for the gated D-type since it so nicely visualizes the behavior of the circuit, "opening" to make the input visible on the output, and "closing" to "latch" the last value in place. --128.130.60.57 20:35, 23 October 2006 (UTC)

I agree for the greater part, but the circuit you refer to as simply a "latch", is what I would call a "transparent" or "gated" latch. This is because even (so called) flip-flops have this latching function, without the transparent gating behaviour you described so nicely! /HenkeB 00:46, 15 November 2006 (UTC)

I don't think a merge is a good idea, the pages have the potential to become pretty large (because of all the different types) and it makes sense to separate based on level-triggered componenents vs edge-triggered components. I'm trying to fix the problem, we should note the ambiguity, but choose an unambiguous way to present it on wikipedia - so that people can understand us. Fresheneesz 21:37, 3 November 2006 (UTC)

I do not mean to be rude here, but the very term "level-triggered" is something of a contradiction, at least in this context. All digital circuits which can be triggered to go from a state A into another state B (depending on type as well as various other inputs), are triggered by the edge of some signal; they change state (or not!) at the edge, be it "latches" or "flip-flops". The term "level-triggered" could maybe be appropriate for inputs which are sampled at regular intervals, such as interrupt lines on microprocessors (i.e those which are not latching the interrupt-signal by the use of an extra flip-flop) as the word "triggered" aims at another (higher) level in this case. /HenkeB

It isn't a contradiction. When distinguishing between edge-triggered and level-sensitive sequential circuits, one is referring to the effect of the clock on the circuit, not on any other inputs. A flip-flop is edge-triggered because the input state is only sampled on the positive or negative edge of the clock; a latch is level-sensitive because the input state is transparent to the output whenever the clock is high (or low for negative level-sensitive).Gungfusteve (talk) 15:27, 3 September 2008 (UTC)

Ok, the same discussion once again ;) First, I was talking about the concept "level-triggered", not "level-sensitive". However, for me, your argument (I have heard it before) is nothing but an attempt to retroactively adjust improper semantics: What about bistable elements without any clock inputs (such as cross-coupled gates), are they "level-triggered" or "edge-triggered"? And what about inputs such as an interrupt line (see above)? It could hardly be called a clock. For me, it's quite simple: In a strict sense, every input that can be triggered is edge-triggered, otherwise, it's a sampled (or disabled) input. /HenkeB (talk) 01:48, 5 September 2008 (UTC)

In case someone didn't know, an edge-triggered latch or flip-flop is basically a master-slave device which has its own circuitry for generating a very short trigger-pulse. This is to keep it open (in the sense of a level-controlled latch) for the shortest possible time, thereby minimizing the risk for analog oscillations in systems with feedback (such as state machines in computers).

To conclude, the various basic bistable elements can be characterized as follows:

(1) SR-latches and gated latches are controlled by static levels, but reacts (triggers) on the edges.

(2) master-slave devices reacts internally on the first edge and externally on the second edge.

(3) edge-controlled devices are fully controlled by one of the edges.

That is, all types are "triggered" by the edge of a signal.

/HenkeB 00:46, 15 November 2006 (UTC)

The distinction between edge-triggered and level-triggered is somewhat arbitrary, but it is nevertheless important. Edge-triggered devices can only change their state on a clock edge. Level-triggered devices can change state at any point that their enable input is true. If you use a clock as the enable input to a D-latch, the state can change any time during one half of the clock cycle (and as many times as its input changes). Hence, it's transparent during that period. For a D flip-flop, no matter how many times the D input changes, the state is only updated once per clock cycle.

It's very uncommon to see latch mean anything other than a transparent circuit or flip-flop mean anything other than a clock-edge-triggered circuit. I think the people who are trying to blur the distinction are making something out of nothing. Incidentally, SRAM is almost always made out of latches, not flip-flops (SRAM cells are synchronously controlled, but that circuitry is outside of the memory cells themselves). But I suppose that's a byproduct of the article's misleading terminology. 142.59.195.50 01:14, 30 April 2007 (UTC)

Have you read my comments above?! As you (seem to) imply yourself, the real distinction is really between transparent and non-transparent devices (or modes); my main point is that the terms "level triggered" and "edge triggered" are semantically meaningless - you cannot trig on a static level, and a level that changes is an edge... Also, you have the problem that the first flip-flops "were" latches! /HenkeB 12:05, 2 August 2007 (UTC)

As a current Electrical Engineering student I must agree with the above statements relating that latches are not flip flops. However, it seems to be common to abuse the terms. ~~ —Preceding unsigned comment added by 71.182.247.251 (talk) 05:30, 5 February 2010 (UTC)

New picture

No wonder its sticks out like a sore thumb, the picture was added yesterday. I added a little caption, but since the picture isn't explained, I don't even know what its supposed to represent, or where the inputs and outputs are. Not to mention the way the picture shows unconnected wires is not intuitive. It looks like its some sort of display the way it is. Like a spinning circle.. In fact thats what it could be.. but - in any case, that picture isn't at all clear. If someone could tell me where the inputs and outputs are, and what the hell it is, I could redo it so it looks much better. Fresheneesz 06:08, 13 March 2006 (UTC)

This is a nonexisitng 'looped' circuit combined of AND-NOT (NAND) gates.

It doesn't explain anything (moreover, it DOES confuse) so i think it should be at the end of an article about gates as an funny example, if it should be at all. Ivan Pozdeev 14:03, 14 March 2006 (UTC)

Nonexisting? What does that mean? And looped circuit? You're not saying its representing a perpetual motion circuit are you? Sounds like this thing should be deletized. Fresheneesz 04:03, 16 March 2006 (UTC)

When a picture is next to a T-flip flop paragraph, what would it represent, a T-flip-flop maybe? So prove, that this is not a T-flip flop! And I think I added a caption, at least about the color codes. If you have a better driving signal for the T-flip-flop then a square signal, then this will be ok with me, but most T-flip-flips are used in counters and thus get a square signal!--Arnero 13:54, 23 March 2006 (UTC)

I'm afraid most readers are going to be utterly confused by this image. Where's T, Q, and Clk? The routing through the middle doesn't make sense: it appears to be all connected together, so how is it red and blue at the same time? Try to see it from a beginner's perspective. - mako 23:49, 23 March 2006 (UTC)

There are also T-flip-flops/clock dividers without a T input (ie, it's assumed that the output always toggles) 129.128.210.68 17:37, 1 May 2007 (UTC)

Flip-Flop definition

Flip-Flop is not a bistable multivibrator. It can implement one with peripheral components, but it is not even its main use. I would change the definition to the following: In electronics and digital circuits, the flip-flop is a pulsed digital circuit capable of serving as a one-bit memory. --Michagal 15:14, 23 May 2006 (UTC)

I disagree, the basic RS flip flop (from which afaict all the other variants developed) is simply a bistable multivibrator implemented using logic gates rather than discrete components. Plugwash 17:58, 23 May 2006 (UTC)

I think the problem is that the original commenter didn't look up with a bistable multivibrator was. People don't understand that a bistable multivibrator has two stable states. They see "vibrator" and think it oscillates (i.e., an astable multivibrator). A flip flop (in fact, a latch) is certainly a bistable multivibrator. —TedPavlic (talk/contrib/@) 21:19, 16 July 2009 (UTC)

Circuit diagram in D-Type Transparent Latch.svg

The diagram does not seem to be right. If the clock is zero then both outputs are 1. A correct implementation can be found e.g. at http://wearcam.org/ece385/lectureflipflops/flipflops/ , or more exactly http://wearcam.org/ece385/lectureflipflops/flipflops/fig5a.gif

I agree -- the picture of the D flip-flop is wrong (for the reasons mentioned above). The picture should be removed (and preferably corrected). -- Milom 00:16, 19 September 2006 (UTC)

SR flip flop

The symbol for a gated SR flip flop

I don't know if there is such a thing (separate from an SR latch), but i'm putting the picture here until we have a section on an edge triggere SR latch, which i'm sure can be made. Fresheneesz 19:25, 4 November 2006 (UTC)

There is such a thing, but it's very rare in actual use. If you take an SR flip-flop and put an inverter between S and R, then you have a D flip-flop with the "S" input becoming your "D" input. 142.59.195.50 01:17, 30 April 2007 (UTC)

Master-slave D flip-flop

Regarding the graphic in Master-slave D flip-flop, the double NOT logic from C is quite unnecessary -- it's easier just to branch C and not one side and leave the other side normal. St.isaac 02:15, 1 March 2007 (UTC)

Master-Slave DFF has two images: the complete implementation using logic gates and partial schematic using two D-latches. I feel that this is redundant and propose to remove the partial implementation (image on the left) and to change the central image to reflect the fact that it is composed of two D-latches with a NOT in between. Michagal 08:50, 29 March 2007 (UTC)

Q

Is Q an abbreviation for something? --Abdull 15:01, 6 March 2007 (UTC)

Welcome to the world of digital electronics! The real answer is nobody knows. Just like how nobody knows why Vcc and Vss are often used for power connections. They are merely standards that have been adopted because certain papers whom used the values become popular many many years ago.--Dacium 06:54, 5 April 2007 (UTC)

That is not exactly true. Vcc is for collector power supply. The "c" is doubled to differentiate it from the voltage on the collector itself, Vc. Vss is used in FET transistors, "s" is for source.Michagal 13:14, 5 April 2007 (UTC)

More specifically, CC is Common Collector—the bus tied to every collector in a purely npn circuit (not to be confused with a common collector amplifier). The other abbreviations (Vee,Vss,Vdd) were consistent and have stuck for historical reasons. Regarding Q, I don't have any sources, but I'm guessing that it was used because it's the letter before RS. That is, QRS is alphabetical (just as JK is). Additionally, Q is often used to represent the charge (or even energy) in a circuit. A flip-flop doesn't store its memory in charge (it uses positive feedback to create an unstable node that drives trajectories to its rails), but the net effect is very similar to DRAM. That being said, I'm pretty sure the QRS explanation is correct. —TedPavlic (talk) 14:54, 9 February 2009 (UTC)

In my many years of using "VCC" I never encountered that explanation. Do you have a source for it? Dicklyon (talk) 16:27, 9 February 2009 (UTC)

Does Wikipedia count as a source?IC_power_supply_pin --71.182.247.251 (talk) 05:45, 5 February 2010 (UTC)

shakeel_abbasqau@yahoo.com

Note that it is just to store data temporarily, this type of memory formed by the flipflops is volatile which means that it depends on voltage —The preceding unsigned comment was added by 202.83.169.218 (talk) 06:14, 3 May 2007 (UTC).

Additional information (correction) about SR flip-flops and news about JK flip-flops

A lot of articles has been written about SR flip-flops. Although the SR flip-flop is very simple, I have read some wrong conclusions. Very often it is forbidden to connect both inputs S and R simultaneously with 1-signal (NOR-gates used), or in other cases the status of the flip-flop is called 'unstable'. In my opinion this is wrong. The only consequence is, that this status cannot be stored. There is only one problem if S and R get a 0-signal simultaneously after S and R has received a 1-signal before. In this case it is indefinite which state will follow (Q=1 or Q=0). Especially this 3rd status of a SR flip-flop makes it possible to create ideal pulse circuits to pulse flip-flops (normally RC combinations are used) for instance. The usage of such ideal pulse circuits can be a basis to construct non clocked JK flip-flops

Perhaps it might be necessary in future to differ between edge-triggered clock and other inputs. Please find the details and diagrams of ideal pulse circuits and non clocked JK flip-flops in an article "Ideal pulse circuit without RC-combination and non-clocked JK flip-flop"
on my homepage below.

 http://www.hpc-berlin.de/dokumente/flipflop_en.pdf

--Klaus-Eckart 12:51, 13 September 2007 (UTC)

This topic seems to come up a lot on the talk page. This is a page on flip flops, not latches, and so it should describe flip flops. RS flip flops are unstable with $S=R=1$. RS latches are not (unless moving from $S=R=1$ to $S=R=0$ quickly). It's the "flip" and "flopping" that sets up the instability in the flip flop. Such "flipping" and "flopping" doesn't exist with the latch. The solution is to stop calling latches flip flops (i.e., show the difference between asynchronous and synchronous inputs/outputs). —TedPavlic (talk/contrib/@) 21:16, 16 July 2009 (UTC)

Unfortunately, I read the article until today.
I hope to understand you correctly.

Please have a look only at the circuit of a (NOR) RS flip-flop and forget that it is said RS flip-flop with its described properties. And now you think what happens is if R = S = 1. It´s clear -> both outputs are 0!. Do it in practice -> the same result! No instability! Have a look at my article, there can you find now a very simple simulation of the non-clocked JK flipflop. It consists of 5 RS flipflops. You can see quite well that the state at R = S = 1 (NOR) is not at all unstable. This state is stable and usefull.

What causes such a statement - instability?
This statement 'instability' does not describe the characteristics of the circuit. It's just a definition, allow only input assignments that can be saved. This restricts the properties of the actuell circuit but a lot.
What do you think?

What is better, to define the same circuit with different names and different properties, or the RS flipflop in all its complexity to describe?

By the way, with a latch that has nothing to do.--Klaus-Eckart (talk) 10:24, 19 January 2010 (UTC)

Timing and metastability

Under "Timing and metastability", this line "In many cases, metastability in flip-flops can be avoided by ensuring that the data and control inputs are held constant for specified periods before and after the clock pulse, called the setup time (tsu) and the hold time (th) respectively." is a bit unclear and ambiguous. I first thought tsu and th was the time the flip-flop waited before it accepted any input. So "the data and control inputs" refers to _external_ drives? Should the sentence be reformulated? 129.241.203.41 12:14, 11 October 2007 (UTC)

I agree. The metastability can be avoided in ``all cases``, not ``in many cases`` by observing Ts and Th. The definition of tsu and th is the specified time flip-flop's input has to remain '0' or '1' before and after clock's active edge. Michagal 12:32, 11 October 2007 (UTC)

Edge-triggered D flip-flop

I was wondering how the picture below is positive edge triggered. When the signal changes from high to low the data is stored, not when it changes from low to high. Is the clock signal inverted? If so, it should be stated that the picture is negative edge triggered.

File:Edge triggered D flip-flop.png

A positive-edge-triggered D flip-flop.

No, the diagram is fine. Note that when the clock signal is low, both the lines leading out of the first stage (the four gates on the left) into the second stage end up high, regardless of whether D is high or low. And the second stage is a SR latch which is set/reset by sending one of its inputs LOW, so nothing changes when both are high. Only when the clock switches to high with the data input held stable do the lines to the output latch go low (only one of the lines), as is necessary for it to change. (it's important for D to stay at one value during the transition, otherwise there are logic races and the results are unpredictable) 88.107.18.45 (talk) 06:57, 29 December 2008 (UTC)

Gate bias

The article does not explain the historical bias/suitability of NAND gates over AND, OR, XOR, NOR and XNOR to implement flip-flops.Anwar (talk) 17:26, 22 May 2008 (UTC)

This is covered in the article on NAND gates. They happen to be simpler than the others when implemented in DTL and TTL. In RTL, on the other hand, NOR gates are easier and NAND is hard. —Preceding unsigned comment added by 60.241.12.136 (talk) 10:50, 2 September 2009 (UTC)

Practical considerations

Maybe is should be noted, that most flip-flops also have asyncronous preset and clear possibilities,have enable, and if disabled both output go HiZ. Bg665 (talk) 20:10, 21 October 2008 (UTC)

JK flip-flop mistake?

Hello,

At the beginning of the "JK flip-flop" section it reads:

The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command.

This is a JK flip-flop, so shouldn't it say:

The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the J = K = 1 condition as a "flip" or toggle command.

This is an important distinction as it would confuse me to see S = R = 1 in the introduction sentence and then to read the Characteristic table, which has J = K = 1 for the flip.

I was too nervous to just go ahead and change it myself. Does anyone else agree that it needs to be changed? fogus (talk) 20:27, 3 December 2008 (UTC)

It makes sense to use S and R in that sentence. It is making a comparison with an SR flip-flop so SR terms should be used. If you jump straight to J and K the logic of the comparison becomes less obvious, and arguably wouldn't make sense at all - the sentence begins with an SR flip-flop and modifies it to be a JK flip-flop. Using JK nomenclature to begin with would fuzzy the fact that we start with an SR type. CrispMuncher (talk) 22:50, 3 December 2008 (UTC)

SR Flip-flop Truth table

When $S=R=1$, the output isn't undefined, but 0 in both $Q$ and ${\overline {Q}}$. --Unsigned (at least as of February 9, 2009)

It's a race condition. There's a better discussion at latch (electronics). Depending on which delay is shorter, the output will either be 1 or 0. There's no way to predict it. —TedPavlic (talk) 14:47, 9 February 2009 (UTC)

To be more precise, in an edge-triggered SR flip-flop (NOT LATCH!), if $S=R=1$ on a clock edge, the flip flop output will be undetermined. Similarly, as discussed on the latch (electronics) page, moving quickly from a non-restricted state to $S=R=1$ and then back to $S=R=0$ leads to a race condition where the output of the latch is undefined. Of course, the flip flop page should be modified to prevent this confusion. Taking latch-specific information off of the edge-triggered flip flop page would go a long way to clearing up the confusion. —TedPavlic (talk/contrib/@) 15:47, 16 July 2009 (UTC)

The section you edited is about the latch (cross-coupled NOR gates, it says). A latch is a flip-flop, too. I'm not familiar with an edge-triggered SR flip-flop; do they exist? Dicklyon (talk) 16:00, 16 July 2009 (UTC)

An edge-triggered RS flip flop (the combination of two clocked RS latches) is commonly used to motivate the design of the edge-triggered JK flip flop. A quick search of Google and a random click leads to [1] which uses the edge-triggered RS flip flop as a tool to discuss the race condition that can occur (and then uses the JK flip flop as a solution). Most digital texts...

• First introduce the SR latch.
• Next introduce the clocked SR latch (i.e., SR latch with AND gates in front and a "clock" input).
• Next introduce the edge-triggered SR flip flop.
• Next introduce the edge-triggered JK flip flop.
• Add combinational logic to describe D and T flip flops.

I'm ASSUMING that this page was originally laid out to do something similar than that, but since then it's become a mess. The section marked "RS flip flop" should maybe be removed or restructured so that there's no ambiguity that it's describing a flip flop and not a latch (the distinction is important, especially for asynchronous designs). A better solution would be to move the "master–slave" D flip-flop section ahead of all the others as an example of the general flip flop topology. Heck, maybe a better solution would be to reorganize following the conventional outline above. —TedPavlic (talk/contrib/@) 21:23, 16 July 2009 (UTC)

That search bolsters my impression that there's no such thing, except as a pedagogical tool. Anyway, most RS flip flops are latches or even simpler cross-coupled gates; those are still flip-flops, traditionally. I'm not sure what the intention of this page's organization was, but I agree that it's worth trying to clean up; but not by being narrow in intepretatin of terms, or making changes incompatible with the text of a section. Dicklyon (talk) 00:46, 17 July 2009 (UTC)

In the 15:56 16July09 edit, the excitation table was changed to indicate a race condition when Q(t) and Q(t+1) are both one (ie Q remains high). I believe the previous incarnation (at 15:54) was correct, the race condition is properly shown in the characteristic table when R and S are both 1. --P.Gilmore —Preceding unsigned comment added by 64.136.252.140 (talk) 13:58, 25 November 2009 (UTC)

Most of this page fits better under "latch" category

The discussion of "transparency" on this page is poor. It would be better to enhance the latch page with a full description of transparent, transparent-high (opaque-low), and transparent-low (opaque-high) latches, and then use that discussion to motivate the introduction of an edge-triggered device. That edge-triggered device is (now) conventionally called a "flip-flop."

This page as it stands mentions briefly the modern naming convention and then goes on to discuss topics that make more sense under the "latch" category.

So I suggest making this page a pure flip-flop page (in the clocked sense of the term) with references to latch. Detailed discussion of gates and transparency can be handled there. —TedPavlic (talk) 14:45, 9 February 2009 (UTC)

I'm against purity here; I'd rather see the article be inclusive of all things called flip flops. It could be done summary style, with links to in-depth pages on latches, on edge-triggered flip-flops, etc., if that would address your concerns. Dicklyon (talk) 00:38, 17 July 2009 (UTC)

Yeah, latch and flip-flop need to be a lot more clear here. I don't know of a textbook released in the last 5 (10?) years that calls the edge triggered device anything other than a flip-flop and a level sensitive device anything other than a latch... Hobit (talk) 02:14, 12 October 2009 (UTC)

D flip flop missing reset behavior

It would be nice if the D flip flop spoke of reset signal behavior or had it in the truth table. Is reset read on clock edge? Is it async? —Preceding unsigned comment added by Brandon.irwin (talk • contribs) 01:42, 12 December 2009 (UTC)

Typically Reset is read asynchronously but it dosen't have to be. Rester might be better explained with a cirucit level diagram, perhaps I'll add one... Guerberj (talk) 05:46, 13 December 2009 (UTC)

I think that D Flip Flop needs better explanations. And also, I need to point that there is no explanation about the Set Signal. —Preceding unsigned comment added by 94.54.32.255 (talk) 22:12, 6 January 2010 (UTC)

JK flip-flop

I think there's a little discrepancy in the JK flip-flop section. The timing diagram is for a positive edge triggered JK flip-flop, and the article states "The flip-flop is positive-edge triggered (rising clock pulse) as seen in the timing diagram." This is true, but the circuit symbol diagram shows a negative edge triggered flip-flop(clock connection arrow pointing inwards) which could cause some confusion among readers.130.209.241.193 (talk) 09:13, 20 January 2010 (UTC)

I changed the image description to reflect this. This is my first article edit, so if there's any problems or issues don't hesitate to contact me. Also, the JK flip flop description seems to suggest that all JK flip flops are positive edge triggered, which is not the case. Although this may be simply my perception of what is stated, so I haven't changed anything else. I created a Wikipedia account just after detailing the original issue, hence why i'm signing this edit with my screen name and not IP address. Darth Gazak (talk) 09:31, 20 January 2010 (UTC)

STL Scripting

I'm not used to editing wiki and all so ill apologize for not signing this up ahead, Scripted a small flipflop in stl, for anyone that wants to write one, or has to write one, instead of using an LAD or FDB.

// Every x value not preceeded by an comment // they should be in the same byte range // pick something yourself // I have used the 22th byte range, but also thats changable

     A(    
     O     Q      x.7
     O     Q      x.4
     )     
     NOT   
     =     Q      x.0
     A     Q      x.0
     =     L     22.0
     A(    
     A(    
     A(    
     A(    
     O     L     22.0

//

     ON    Q      x.0

// The above is your input, every input is the same ofcourse.

     )     
     NOT   
     =     Q      x.1
     A     Q      x.1
     O     Q      x.6
     )     
     NOT   
     =     Q      x.2
     A     Q      x.2

//

     O     Q      x.0

// The above is your input, every input is the same ofcourse.

     )     
     NOT   
     =     Q      x.3
     A     Q      x.3
     O     Q      x.0
     )     
     NOT   
     =     Q      x.4
     A     Q      x.4
     =     L     22.1
     A(    
     A(    
     A(    
     O     L     22.1

//

     ON    Q      x.0

// The above is your input, every input is the same ofcourse.

     )     
     NOT   
     =     Q      x.5
     A     Q      x.5
     O     Q      x.2
     )     
     NOT   
     =     Q      x.6
     A     Q      x.6

//

     O     Q      x.0

// The above is your input, every input is the same ofcourse.

     )     
     NOT   
     =     Q      x.7
     A     Q      x.7
     =     Q      x.7
     A     L     22.1
     BLD   102

//

     =     Q      x.0

// replace x with an output digit.

     A     L     22.0
     BLD   102

//

     =     Q      x.1

// replace x with an output digit. —Preceding unsigned comment added by 217.166.79.130 (talk) 09:06, 10 February 2010 (UTC)