AVR32

The Atmel AVR32 is a 32-bit RISC/DSP architecture designed by Atmel (Nasdaq:ATML). The AVR32 architecture was architected by a handful of people, including Lead Designer Øyvind Strøm,PhD and CPU Architecture Erik Renno, M.Sc in Atmel's norwegian design centre.

The AVR32 Architecture consists of several micro-architectures, most notably the AVR32A and AVR32B architectures. Further descriptions are found in the AVR32 Architecture Manual

The AVR32 Instruction Set Architecture consists of 16-bit (compact) and 32-bit (extended) instructions, with several specialized instructions not found in architectures like MIPS32 or ARMv5 or ARMv6 ISA. Several US patents are filed for the AVR32 ISA and design platform.

Just like the AVR 8-bit microcontroller architecture, the AVR32 was designed for extremely efficient code density and performance per clock cycle. Atmel used the independant benchmark consortium EEMBC to benchmark the architecture with various compilers and consistantly outperformed both ARMv5 16-bit (THUMB) code and ARMv5 32-bit (ARM) code by as much as 50% on code-size and 3X on performance. For more information, check EEMBC or Atmel's own claims on their website.

The AVR32 architecture is solely used in Atmel's own products and will appear in several devices in 2006. The first implementation of the AVR32 architecture is a 7-stage pipelined, cache-based design platform. This implementation of the AVR32 architecture adds SIMD (single instruction multiple data) DSP (digital signal processing) instructions to the RISC instruction-set, in addition to Java hardware acceleration.

Most instructions are executed single-cycle and the MAC-unit is capable of performing 16x32=48 arithmetic in one cycle.

Any resemblance to the 8-bit AVR is only with respect to the design center (both architectures originated out of Atmel Norway, Trondheim) and some of the debug-tools.