GDDR5 SDRAM

This article is about DDR5 graphics RAM (SDRAM). For non-graphics DDR memory, see SDRAM.

GDDR5, an abbreviation for double data rate type five synchronous graphics random access memory, is a modern type of synchronous graphics random access memory (SGRAM) with a high bandwidth ("double data rate") interface designed for use in graphics cards, game consoles, and high-performance computation.

Overview

Like its predecessor, GDDR4, GDDR5 is based on DDR3 SDRAM memory which has double the data lines compared to DDR2 SDRAM, but GDDR5 also has 8-bit wide prefetch buffers similar to GDDR4.

GDDR5 SGRAM conforms to the standards which were set out in the GDDR5 specification by the JEDEC. SGRAM is single-ported. However, it can open two memory pages at once, which simulates the dual-port nature of other VRAM technologies. It uses an 8n-prefetch architecture and DDR interface to achieve high performance operation and can be configured to operate in ×32 mode or ×16 (clamshell) mode which is detected during device initialization. The GDDR5 interface transfers two 32-bit wide data words per write clock (WCK) cycle to/from the I/O pins. Corresponding to the 8n-prefetch, a single write or read access consists of a 256-bit wide two CK clock cycle data transfer at the internal memory core and eight corresponding 32-bit wide one-half WCK clock cycle data transfers at the I/O pins.

GDDR5 operates with two different clock types. A differential command clock (CK) as a reference for address and command inputs, and a forwarded differential write clock (WCK) as a reference for data reads and writes, that runs at twice the CK frequency. Being more precise, the GDDR5 SGRAM uses a total of three clocks: two write clocks associated with two bytes (WCK01 and WCK23) and a single command clock (CK). Taking a GDDR5 with 5 Gbit/s data rate per pin as an example, the CK clock runs with 1.25 GHz and both WCK clocks at 2.5 GHz. The CK and WCKs are phase aligned during the initialization and training sequence. This alignment allows read and write access with minimum latency.

A single 32-bit GDDR5 chip has about 67 signal pins and the rest are power and grounds in the 170 BGA package.

Commercial implementation

In 2007, Qimonda, a spin-off of Infineon, demonstrated and sampled GDDR5, and released a paper about the technologies behind GDDR5. As of May 10, 2008, Qimonda announced volume production of 512 Mbit GDDR5 modules rated at 3.6 Gbit/s (900 MHz), 4.0 Gbit/s (1 GHz), and 4.5 Gbit/s (1.125 GHz).

Hynix Semiconductor introduced the industry's first 1 Gib GDDR5 memory. It supported a bandwidth of 20 GB/s on a 32-bit bus, which enables memory configurations of 1 GiB at 160 GB/s with only 8 circuits on a 256-bit bus. Hynix 2 Gbit GDDR5 boasts a 7 GHz clock speed. The newly developed GDDR5 is the fastest and highest density graphics memory available in the market. It operates at 7 GHz effective clock-speed and processes up to 28 GB/s with a 32-bit I/O. 2 Gbit GDDR5 memory chips will enable graphics cards with 2 GiB or more of onboard memory with 224 GB/s or higher peak bandwidth. The memory maker claims that the new chip will be in demand in the second half of 2010.

On June 25, 2008, AMD became the first company to ship products using GDDR5 memory with its Radeon HD 4870 video card series, incorporating Qimonda's 512 Mbit memory modules at 3.6 Gbit/s bandwidth.

On February 20, 2013, it was announced that the PlayStation 4 will use 16x4 Gbit (i.e. 16x512 MiB) GDDR5 memory chips for 8 GiB of GDDR5 @ 176 GB/s (CK 1.375 GHz and WCK 2.75 GHz) as combined system and graphics RAM for use with its AMD-powered APU.

See also

• List of device bandwidths

External links

• Introduction To GDDR5 SGRAM(by ELPIDA)
• Making Accurate Measurements on GDDR5 Memory Systems
• GDDR5 Pinout and Description