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AMD APU

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AMD APU
Release date2011
CodenameFusion
Desna
Ontario
Zacate
Llano
Hondo
Trinity
Weatherford
Richland
Kaveri
Kabini
Temash
IGP
Wrestler
WinterPark
BeaverCreek
ArchitectureAMD64
ModelsDesktop E2 Series
Cores2 to 4
Transistors1,178M 32 nm (Llano)
  • 1,303M 32 nm (Trinity)
  • 1,3M 32 nm (Richland)
  • 2,41M 28 nm (Kaveri)
API support
DirectXDirect3D 11
OpenCL1.2
OpenGL4.1+

The AMD Accelerated Processing Unit, formerly known as Fusion, is a series of 64-bit microprocessors from AMD designed to act as a CPU and graphics accelerator (GPU) on a single chip.

AMD announced the first generation APUs, Llano for high-performance and Brazos for low-power devices in January 2011. The second-generation Trinity for high-performance and Brazos-2 for low-power devices were announced in June 2012. The third-generation Kaveri for high performance devices was launched in January 2014, while Kabini and Temash for low-power devices were announced in summer 2013.

The Sony PlayStation 4 and Microsoft Xbox One eighth generation video game consoles both use semi-custom third-generation low-power APUs.

History

The AMD Fusion project started in 2006 with the aim of developing a system on a chip that combined a CPU with a GPU on a single die. The acquisition of graphics chipset manufacturer ATI by AMD was a key step toward realising such a vision.[1] The project reportedly required three internal iterations of the Fusion concept to create a product deemed worthy of release.[1] Reasons contributing to the delay of the project include the technical difficulties of combining a CPU and GPU on the same die at a 45 nm process, and conflicting views on what the role of the CPU and GPU should be within the project.[2]

The first generation desktop and laptop APU, codenamed Llano, was announced on January 4, 2011 at the 2011 CES show in Las Vegas and released shortly after.[3][4] It featured K10 CPU cores and a Radeon HD 6000-series GPU on the same die on the FM1 socket. An APU for low-power devices was announced as the Brazos platform, based on the Bobcat microarchitecture and a Radeon HD 6000-series GPU on the same die.

At a conference in January 2012, corporate fellow Phil Rogers announced that AMD would re-brand the Fusion platform as the Heterogeneous Systems Architecture (HSA), stating that "it's only fitting that the name of this evolving architecture and platform be representative of the entire, technical community that is leading the way in this very important area of technology and programming development."[5] However, it was later revealed that AMD had been the subject of a trademark infringement lawsuit by the Swiss company Arctic, who used the name "Fusion" for a line of power supplies.[6]

The second generation desktop and laptop APU, codenamed Trinity was announced at AMD's Financial Analyst Day 2010[7][8] and released in October 2012.[9] It featured Piledriver CPU cores and Radeon HD 7000 Series GPU cores on the FM2 socket.[10] AMD released a new APU based on the Piledriver microarchitecture on March 12, 2013 for Laptops/Mobile and on June 4, 2013 for desktops under the codename Richland.[11] The second generation APU for low-power devices, Brazos 2.0, remained on the Bobcat microarchitecture but integrated a Radeon HD 7000-series GPU core onto the die.

Semi-custom chips were introduced in the Microsoft Xbox One and Sony PlayStation 4 video games consoles.[12][13]

A third generation of the technology was released on 14 January 2014, featuring greater integration between the CPU and GPU. The desktop and laptop variant is codenamed Kaveri, based on Steamroller architecture, while the low-power variants, codenamed Kabini and Temash, are based on Jaguar architecture.[14]

Features

AMD Heterogeneous System Architecture

Main article: Heterogeneous System Architecture

AMD is a founding member of the HSA Foundation and is consequently actively working on developing the Heterogeneous System Architecture in co-operation with the other members. The following hardware and software implementations are available in AMD's APU-branded products:

Type HSA Feature First Implemented Notes
Optimized Platform GPU Compute C++ Support 2012
Trinity APUs		 Support OpenCL C++ directions and Microsoft’s C++ AMP language extension. This eases programming of both CPU and GPU working together to process support parallel workloads.
HSA-aware MMU GPU can access the entire system memory through the translation services and page fault management of the HSA MMU.
Shared Power Management CPU and GPU now share the power budget. Priority goes to the processor most suited to the current tasks.
Architectural Integration Unified Address Space for CPU and GPU[15][16] 2014
PlayStation 4,
Kaveri APUs		 CPU and GPU now access the memory with the same address space. Pointers can now be freely passed between CPU and GPU, hence enabling zero-copy.
Fully coherent memory between CPU & GPU GPU can now access and cache data from coherent memory regions in the system memory, and also reference the data from CPU's cache. Cache coherency is maintained.
GPU uses pageable system memory via CPU pointers GPU can take advantage of the shared virtual memory between CPU and GPU, and pageable system memory can now be referenced directly by the GPU, instead of being copied or pinned before accessing.
System Integration GPU compute context switch 2015
Carrizo APU		 Compute tasks on GPU can be context switched, allowing a multi-tasking environment and also faster interpretation between applications, compute and graphics.
GPU graphics pre-emption Long-running graphics tasks can be pre-empted so processes have low latency access to the GPU.
Quality of Service[15] In addition to context switch and pre-emption, hardware resources can be either equalized or prioritized among multiple users and applications.

Multi-monitor support

Main article: AMD Eyefinity

Multi-monitor setup based on AMD Eyefinity are also possible with AMD's APU branded product line, as this video showing Civilization V running in 3x1 portrait mode on an Eyefinity-enabled AMD A10-7850K "Kaveri" proves.[17]

Video acceleration

Main articles: Unified Video Decoder and Video Codec Engine

Both Unified Video Decoder (UVD) and Video Codec Engine (VCE) are present on the dies of all APU branded products. They are supported by AMD Catalyst and by the free and open-source graphics device driver#ATI/AMD.

AMD TrueAudio

Main article: AMD TrueAudio

AMD TrueAudio is a new IP core for audio acceleration. It is only found on the "Kaveri"-branded APUs.

Feature overview

The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).

[ VisualEditor ]
Platform High, standard and low power Low and ultra-low power
Codename Server Basic Toronto
Micro Kyoto
Desktop Performance Raphael Phoenix
Mainstream Llano Trinity Richland Kaveri Kaveri Refresh (Godavari) Carrizo Bristol Ridge Raven Ridge Picasso Renoir Cezanne
Entry
Basic Kabini Dalí
Mobile Performance Renoir Cezanne Rembrandt Dragon Range
Mainstream Llano Trinity Richland Kaveri Carrizo Bristol Ridge Raven Ridge Picasso Renoir
Lucienne 		Cezanne
Barceló 		Phoenix
Entry Dalí Mendocino
Basic Desna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L Stoney Ridge Pollock
Embedded Trinity Bald Eagle Merlin Falcon,
Brown Falcon 		Great Horned Owl Grey Hawk Ontario, Zacate Kabini Steppe Eagle, Crowned Eagle,
LX-Family 		Prairie Falcon Banded Kestrel River Hawk
Released Aug 2011 Oct 2012 Jun 2013 Jan 2014 2015 Jun 2015 Jun 2016 Oct 2017 Jan 2019 Mar 2020 Jan 2021 Jan 2022 Sep 2022 Jan 2023 Jan 2011 May 2013 Apr 2014 May 2015 Feb 2016 Apr 2019 Jul 2020 Jun 2022 Nov 2022
CPU microarchitecture K10 Piledriver Steamroller Excavator "Excavator+"[18] Zen Zen+ Zen 2 Zen 3 Zen 3+ Zen 4 Bobcat Jaguar Puma Puma+[19] "Excavator+" Zen Zen+ "Zen 2+"
ISA x86-64 v1 x86-64 v2 x86-64 v3 x86-64 v4 x86-64 v1 x86-64 v2 x86-64 v3
Socket Desktop Performance — AM5 — —
Mainstream — AM4 — —
Entry FM1 FM2 FM2+ FM2+[a], AM4 AM4 —
Basic — — AM1 — FP5 —
Other FS1 FS1+, FP2 FP3 FP4 FP5 FP6 FP7 FL1 FP7
FP7r2
FP8 		? FT1 FT3 FT3b FP4 FP5 FT5 FP5 FT6
PCI Express version 2.0 3.0 4.0 5.0 4.0 2.0 3.0
CXL — —
Fab. (nm) GF 32SHP
(HKMG SOI) 		GF 28SHP
(HKMG bulk) 		GF 14LPP
(FinFET bulk) 		GF 12LP
(FinFET bulk) 		TSMC N7
(FinFET bulk) 		TSMC N6
(FinFET bulk) 		CCD: TSMC N5
(FinFET bulk)
cIOD: TSMC N6
(FinFET bulk) 		TSMC 4nm
(FinFET bulk) 		TSMC N40
(bulk) 		TSMC N28
(HKMG bulk) 		GF 28SHP
(HKMG bulk) 		GF 14LPP
(FinFET bulk) 		GF 12LP
(FinFET bulk) 		TSMC N6
(FinFET bulk)
Die area (mm2) 228 246 245 245 250 210[20] 156 180 210 CCD: (2x) 70
cIOD: 122 		178 75 (+ 28 FCH) 107 ? 125 149 ~100
Min TDP (W) 35 17 12 10 15 65 35 4.5 4 3.95 10 6 12 8
Max APU TDP (W) 100 95 65 45 170 54 18 25 6 54 15
Max stock APU base clock (GHz) 3 3.8 4.1 4.1 3.7 3.8 3.6 3.7 3.8 4.0 3.3 4.7 4.3 1.75 2.2 2 2.2 3.2 2.6 1.2 3.35 2.8
Max APUs per node[b] 1 1
Max core dies per CPU 1 2 1 1
Max CCX per core die 1 2 1 1
Max cores per CCX 4 8 2 4 2 4
Max CPU[c] cores per APU 4 8 16 8 2 4 2 4
Max threads per CPU core 1 2 1 2
Integer pipeline structure 3+3 2+2 4+2 4+2+1 1+3+3+1+2 1+1+1+1 2+2 4+2 4+2+1
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF Yes Yes
IOMMU[d] — v2 v1 v2
BMI1, AES-NI, CLMUL, and F16C Yes — Yes
MOVBE — Yes
AVIC, BMI2, RDRAND, and MWAITX/MONITORX — Yes
SME[e], TSME[e], ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing — Yes — Yes
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT — Yes — Yes
MPK, VAES — Yes —
SGX — —
FPUs per core 1 0.5 1 1 0.5 1
Pipes per FPU 2 2
FPU pipe width 128-bit 256-bit 80-bit 128-bit 256-bit
CPU instruction set SIMD level SSE4a[f] AVX AVX2 AVX-512 SSSE3 AVX AVX2
3DNow! 3DNow!+ — —
PREFETCH/PREFETCHW Yes Yes
GFNI — Yes —
AMX —
FMA4, LWP, TBM, and XOP — Yes — — Yes —
FMA3 Yes Yes
AMD XDNA — Yes —
L1 data cache per core (KiB) 64 16 32 32
L1 data cache associativity (ways) 2 4 8 8
L1 instruction caches per core 1 0.5 1 1 0.5 1
Max APU total L1 instruction cache (KiB) 256 128 192 256 512 256 64 128 96 128
L1 instruction cache associativity (ways) 2 3 4 8 2 3 4 8
L2 caches per core 1 0.5 1 1 0.5 1
Max APU total L2 cache (MiB) 4 2 4 16 1 2 1 2
L2 cache associativity (ways) 16 8 16 8
Max on--die L3 cache per CCX (MiB) — 4 16 32 — 4
Max 3D V-Cache per CCD (MiB) — 64 — —
Max total in-CCD L3 cache per APU (MiB) 4 8 16 64 4
Max. total 3D V-Cache per APU (MiB) — 64 — —
Max. board L3 cache per APU (MiB) — —
Max total L3 cache per APU (MiB) 4 8 16 128 4
APU L3 cache associativity (ways) 16 16
L3 cache scheme Victim Victim
Max. L4 cache — —
Max stock DRAM support DDR3-1866 DDR3-2133 DDR3-2133, DDR4-2400 DDR4-2400 DDR4-2933 DDR4-3200, LPDDR4-4266 DDR5-4800, LPDDR5-6400 DDR5-5200 DDR5-5600, LPDDR5x-7500 DDR3L-1333 DDR3L-1600 DDR3L-1866 DDR3-1866, DDR4-2400 DDR4-2400 DDR4-1600 DDR4-3200 LPDDR5-5500
Max DRAM channels per APU 2 1 2 1 2
Max stock DRAM bandwidth (GB/s) per APU 29.866 34.132 38.400 46.932 68.256 102.400 83.200 120.000 10.666 12.800 14.933 19.200 38.400 12.800 51.200 88.000
GPU microarchitecture TeraScale 2 (VLIW5) TeraScale 3 (VLIW4) GCN 2nd gen GCN 3rd gen GCN 5th gen[21] RDNA 2 RDNA 3 TeraScale 2 (VLIW5) GCN 2nd gen GCN 3rd gen[21] GCN 5th gen RDNA 2
GPU instruction set TeraScale instruction set GCN instruction set RDNA instruction set TeraScale instruction set GCN instruction set RDNA instruction set
Max stock GPU base clock (MHz) 600 800 844 866 1108 1250 1400 2100 2400 400 538 600 ? 847 900 1200 600 1300 1900
Max stock GPU base GFLOPS[g] 480 614.4 648.1 886.7 1134.5 1760 1971.2 2150.4 3686.4 102.4 86 ? ? ? 345.6 460.8 230.4 1331.2 486.4
3D engine[h] Up to 400:20:8 Up to 384:24:6 Up to 512:32:8 Up to 704:44:16[22] Up to 512:32:8 768:48:8 128:8:4 80:8:4 128:8:4 Up to 192:12:8 Up to 192:12:4 192:12:4 Up to 512:?:? 128:?:?
IOMMUv1 IOMMUv2 IOMMUv1 ? IOMMUv2
Video decoder UVD 3.0 UVD 4.2 UVD 6.0 VCN 1.0[23] VCN 2.1[24] VCN 2.2[24] VCN 3.1 ? UVD 3.0 UVD 4.0 UVD 4.2 UVD 6.2 VCN 1.0 VCN 3.1
Video encoder — VCE 1.0 VCE 2.0 VCE 3.1 — VCE 2.0 VCE 3.4
AMD Fluid Motion No Yes No No Yes No
GPU power saving PowerPlay PowerTune PowerPlay PowerTune[25]
TrueAudio — Yes[26] ? — Yes
FreeSync 1
2 		1
2
HDCP[i] ? 1.4 2.2 2.3 ? 1.4 2.2 2.3
PlayReady[i] — 3.0 not yet — 3.0 not yet
Supported displays[j] 2–3 2–4 3 3 (desktop)
4 (mobile, embedded)		 4 2 3 4 4
/drm/radeon[k][28][29] Yes — Yes —
/drm/amdgpu[k][30] — Yes[31] — Yes[31]
  1. ^ For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
  2. ^ A PC would be one node.
  3. ^ An APU combines a CPU and a GPU. Both have cores.
  4. ^ Requires firmware support.
  5. ^ a b Requires firmware support.
  6. ^ No SSE4. No SSSE3.
  7. ^ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  8. ^ Unified shaders : texture mapping units : render output units
  9. ^ a b To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
  10. ^ To feed more than two displays, the additional panels must have native DisplayPort support.[27] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
  11. ^ a b DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

APU-branded platforms

For a more comprehensive list, see List of AMD Accelerated Processing Unit microprocessors.

AMD APUs have a unique architecture: they have AMD CPU modules, cache, and a discrete-class graphics processor all on the same die, using the same bus. This architecture allows for the use of graphics accelerators, such as OpenCL, with the integrated graphics processor.[32] The goal is to create a "fully integrated" APU, which, according to AMD will eventually feature 'heterogeneous cores' capable of processing both CPU and GPU work automatically, depending on the workload requirement.[33]

K10 architecture (2011): Llano

Main article: AMD 10h

The first generation APU, released in June 2011, was used in both desktops and laptops. It was based on the K10 architecture and built on a 32 nm process featuring two to four CPU cores on a TDP of 65-100 W, and integrated graphics based on the Radeon HD6000 Series with support for DirectX 11, OpenGL 4.2 and OpenCL 1.2. In performance comparisons against the similarly priced Intel Core i3-2105, the Llano APU was criticised for its poor CPU performance[36] and praised for its better GPU performance.[37][38] AMD was later criticised for abandoning Socket FM1 after one generation.[39]

Bobcat architecture (2011): Ontario, Zacate, Desna, Hondo

Main article: Bobcat (microarchitecture)

The AMD Brazos platform was introduced on January 4, 2011 targeting the subnotebook, netbook and low power small form factor markets.[3] It features the 9-watt AMD C-Series APU (codename: Ontario) for netbooks and low power devices as well as the 18-watt AMD E-Series APU (codename: Zacate) for mainstream and value notebooks, all-in-ones and small form factor desktops. Both APUs feature one or two Bobcat x86 cores and a Radeon Evergreen Series GPU with full DirectX11, DirectCompute and OpenCL support including UVD3 video acceleration for HD video including 1080p.[3]

AMD expanded the Brazos platform on June 5, 2011 with the announcement of the 5.9-watt AMD Z-Series APU (codename: Desna) designed for the Tablet market.[40] The Desna APU is based on the 9-watt Ontario APU, energy savings were achieved by lowering the CPU, GPU and north bridge voltages, reducing the idle clocks of the CPU and GPU as well as introducing a hardware thermal control mode.[40] A bidirectional turbo core mode was also introduced.

AMD announced the Brazos-T platform on October 9, 2012. It comprises the 4.5-watt AMD Z-Series APU (codename: Hondo) and the A55T Fusion Controller Hub (FCH), designed for the tablet computer market.[41][42] The Hondo APU is a redesign of the Desna APU. AMD lowered energy use by optimizing the APU and FCH for tablet computers.[43][44]

The Deccan platform including Krishna and Wichita APUs were cancelled in 2011. AMD originally planned to release them in the second half 2012.[45]

Piledriver architecture (2012): Trinity and Richland

Main article: Piledriver (microarchitecture)

Trinity The first iteration of the second generation platform, released in October 2012, brought improvements to CPU and GPU performance to both desktops and laptops. The platform features 2 to 4 Piledriver CPU cores built on a 32 nm process with a TDP between 65 W and 100 W, and a GPU based on the Radeon HD7000 Series with support for DirectX 11, OpenGL 4.2, and OpenCL 1.2. The Trinity APU was praised for the improvements to CPU performance compared to the Llano APU.[48]

Richland

  • "Enhanced Piledriver" CPU cores[49]
  • Temperature Smart Turbo Core technology. An advancement of the existing Turbo Core technology, which allows internal software to adjust the CPU and GPU clock speed to maximise performance within the constrains of the Thermal design power of the APU.[50]
  • New low-power consumption CPUs with only 45 W TDP[51]

The release of this second iteration of this generation was 12 March 2013 for mobile parts and 5 June 2013 for desktop parts.

Jaguar architecture (2013): Kabini and Temash

Main articles: Jaguar (microarchitecture) and Graphics Core Next

In January 2013 the Jaguar-based Kabini and Temash APUs were unveiled as the successors of the Bobcat-based Ontario, Zacate and Hondo APUs.[52][53][54] The Kabini APU is aimed at the low-power, subnotebook, netbook, ultra-thin and small form factor markets, the Temash APU is aimed at the tablet, ultra-low power and small form factor markets.[54] The two to four Jaguar cores of the Kabini and Temash APUs feature numerous architectural improvements regarding power requirement and performance, such as support for newer x86-instructions, a higher IPC count, a CC6 power state mode and clock gating.[55][56][57] Kabini and Temash are AMD's first, and also the first ever quad-core x86 based SoCs.[58] The integrated Fusion Controller Hubs (FCH) for Kabini and Temash are codenamed "Yangtze" and "Salton" respectively.[59] The Yangtze FCH features support for two USB 3.0 ports, two SATA 6 Gbit/s ports, as well as the xHCI 1.0 and SD/SDIO 3.0 protocols for SD-card support.[59] Both chips feature DirectX 11.1-compliant GCN-based graphics as well as numerous heterogeneous system architecture (HSA) improvements.[52][53] They were fabricated at a 28 nm process in an FT3 BGA package by TSMC, and were released on May 23, 2013.[55][60][61]

The PlayStation 4 and Xbox One were revealed to both be powered by 8-core semi-custom Jaguar-derived APUs.

ARM server architecture (2014): Seattle

A Cortex-A57-based 64-bit server solution SoC will be launched in the second half of 2014 and codenamed "Seattle".[62] The first AMD ARM chip has no GPU and is then not an APU, but later will be. Seattle will feature 8 or 16 core variants, with an expected clockspeed over 2 GHz, and will reportedly deliver up to four times the performance of current Opteron X processors.[63] These ARM processors will incorporate SeaMicro freedom fabric on die, offering up to 10 Gbit/s bandwidth, for server usage; additionally, each ARM processor will support up to 64 GB DRAM.[64]

Steamroller architecture (2014): Kaveri

Main articles: Steamroller (microarchitecture) and Graphics Core Next

The third generation of the platform, codenamed Kaveri, was partly released on January 14, 2014.[67] Kaveri contains up to four Steamroller CPU cores clocked to 3.7 GHz with a turbo mode of 4 GHz, up to a 512-core Graphics Core Next GPU, two decode units per module instead of one (which allows each core to decode four instructions per cycle instead of two), AMD TrueAudio,[68] Mantle API,[69] an on-chip ARM Cortex-A5 MPCore,[70] and will release with a new socket, FM2+.[71] Ian Cutress and Rahul Garg of Anandtech asserted that Kaveri represented the unified system-on-a-chip realisation of AMD's acquisition of ATI. The performance of the 45W A8-7600 Kaveri APU was found to be similar to that of the 100W Richland part, leading to the claim that AMD made significant improvements in on-die graphics performance per watt;[65] however, CPU performance was found to lag behind similarly-specified Intel processors, a lag that was unlikely to be resolved in the Bullzdozer family APUs.[65] The A8-7600 component was delayed from a Q1 launch to an H1 launch because the Steamroller architecture components are alleged to not scale well at higher clock speeds.[72]

AMD announced the release of the Kaveri APU for the mobile market on June 4, 2014 at Computex 2014,[66] shortly after the accidental announcement on the AMD website on May 26, 2014.[73] The announcement included components targeted at the standard voltage, low-voltage, and ultra-low voltage segments of the market. In early-access performance testing of a Kaveri prototype laptop, Ars Technica found that the 35W FX-7600P was competitive with the similarly-priced 17W Intel i7-4500U in synthetic CPU-focused benchmarks, and was significantly better than previous integrated GPU systems on GPU-focused benchmarks.[74] Tom's Hardware reported the performance of the Kaveri FX-7600P against the 35W Intel i7-4702MQ, finding that the i7-4702MQ was significantly better than the FX-7600P in synthetic CPU-focused benchmarks, whereas the FX-7600P was significantly better than the i7-4702MQ's Intel HD 4600 iGPU in the four games that could be tested in the time available to the team.[66]

Puma architecture (2014): Beema and Mullins

Main articles: Puma (microarchitecture) and Graphics Core Next

Excavator architecture (2015): Carrizo

Main articles: Excavator (microarchitecture) and Graphics Core Next

See also

References

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