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Silicon on insulator

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For silicon on insulator optical devices, see silicon photonics.

In semiconductor manufacturing, silicon on insulator (SOI) technology is fabrication of silicon semiconductor devices in a layered silicon–insulator–silicon substrate, to reduce parasitic capacitance within the device, thereby improving performance.[1] SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are called silicon on sapphire, or SOS). The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices.[2] The insulating layer and topmost silicon layer also vary widely with application.[3]

Industry need

SOI technology is one of several manufacturing strategies to allow the continued miniaturization of microelectronic devices, colloquially referred to as "extending Moore's Law" (or "More Moore", abbreviated "MM"). Reported benefits of SOI relative to conventional silicon (bulk CMOS) processing include:[4]

  • Lower parasitic capacitance due to isolation from the bulk silicon, which improves power consumption at matched performance
  • Resistance to latchup due to complete isolation of the n- and p-well structures
  • Higher performance at equivalent VDD. Can work at low VDD's[5]
  • Reduced temperature dependency due to no doping
  • Better yield due to high density, better wafer utilization
  • Reduced antenna issues
  • No body or well taps are needed
  • Lower leakage currents due to isolation thus higher power efficiency
  • Inherently radiation hardened (resistant to soft errors), reducing the need for redundancy

From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The threshold voltage of the transistor depends on the history of operation and applied voltage to it, thus making modeling harder. The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10–15% increase to total manufacturing costs.[6][additional citation(s) needed]

SOI transistors

An SOI MOSFET is a semiconductor device (MOSFET) in which a semiconductor layer such as silicon or germanium is formed on an insulator layer which may be a buried oxide (BOX) layer formed in a semiconductor substrate.[7][8][9] SOI MOSFET devices are adapted for use by the computer industry.[citation needed] The buried oxide layer can be used in SRAM designs.[10] There are two types of SOI devices: PDSOI (partially depleted SOI) and FDSOI (fully depleted SOI) MOSFETs. For an n-type PDSOI MOSFET the sandwiched p-type film between the gate oxide (GOX) and buried oxide (BOX) is large, so the depletion region can't cover the whole p region. So to some extent PDSOI behaves like bulk MOSFET. Obviously there are some advantages over the bulk MOSFETs. The film is very thin in FDSOI devices so that the depletion region covers the whole film. In FDSOI the front gate (GOX) supports less depletion charges than the bulk so an increase in inversion charges occurs resulting in higher switching speeds. The limitation of the depletion charge by the BOX induces a suppression of the depletion capacitance and therefore a substantial reduction of the subthreshold swing allowing FD SOI MOSFETs to work at lower gate bias resulting in lower power operation. The subthreshold swing can reach the minimum theoretical value for MOSFET at 300K, which is 60mV/decade. This ideal value was first demonstrated using numerical simulation.[11][12] Other drawbacks in bulk MOSFETs, like threshold voltage roll off, etc. are reduced in FDSOI since the source and drain electric fields can't interfere due to the BOX. The main problem in PDSOI is the "floating body effect (FBE)" since the film is not connected to any of the supplies.[citation needed]

Manufacture of SOI wafers

SIMOX process
Smart Cut process

SiO2-based SOI wafers can be produced by several methods:

  • SIMOX - Separation by IMplantation of OXygen – uses an oxygen ion beam implantation process followed by high temperature annealing to create a buried SiO2 layer.[13][14]
  • Wafer bonding[15][16] – the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.
    • One prominent example of a wafer bonding process is the Smart Cut method developed by the French firm Soitec which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer.
    • NanoCleave is a technology developed by Silicon Genesis Corporation that separates the silicon via stress at the interface of silicon and silicon-germanium alloy.[17]
    • ELTRAN is a technology developed by Canon which is based on porous silicon and water cut.[18]
  • Seed methods[19] - wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.

An exhaustive review of these various manufacturing processes may be found in reference[1]

Microelectronics industry

Research

The silicon-on-insulator concept dates back to 1964, when it was proposed by C.W. Miller and P.H. Robinson.[20] In 1979, a Texas Instruments research team including A.F. Tasch, T.C. Holloway and Kai Fong Lee fabricated a silicon-on-insulator MOSFET (metal-oxide-semiconductor field-effect transistor).[21] In 1983, a Fujitsu research team led by S. Kawamura fabricated a three-dimensional integrated circuit with SOI CMOS (complementary metal-oxide-semiconductor) structure.[22] In 1984, the same Fujitsu research team fabricated a 3D gate array with vertically-stacked dual SOI/CMOS structure using beam recrystallization.[23] The same year, Electrotechnical Laboratory researchers Toshihiro Sekigawa and Yutaka Hayashi fabricated a double-gate MOSFET, demonstrating that short-channel effects can be significantly reduced by sandwiching a fully depleted SOI device between two gate electrodes connected together.[24][25]

In 1989, Ghavam Shahidi initiated the SOI Research Program at the IBM Thomas J Watson Research Center.[26] He was the chief architect of SOI technology at IBM Microelectronics, where he made fundamental contributions, from materials research to the development of the first commercially viable devices, with the support of his boss Bijan Davari.[27] Shahidi was a key figure in making SOI CMOS technology a manufacturable reality. In the early 1990s, he demonstrated a novel technique of combining silicon epitaxial overgrowth and chemical mechanical polishing to prepare device-quality SOI material for fabricating devices and simple circuits, which led to IBM expanding its research program to include SOI substrates. He was also the first to demonstrate the power-delay advantage of SOI CMOS technology over traditional bulk CMOS in microprocessor applications. He overcame barriers preventing the semiconductor industry's adoption of SOI, and was instrumental in driving SOI substrate development to the quality and cost levels suitable for mass-production.[28]

In 1994, an IBM research team led by Shahidi, Bijan Davari and Robert H. Dennard fabricated the first sub-100 nanometer SOI CMOS devices.[29][30] In 1998, a team of Hitachi, TSMC and UC Berkeley researchers demonstrated the FinFET (fin field-effect transistor),[31] which is a non-planar, double-gate MOSFET built on an SOI substrate.[32] In early 2001, Shahidi used SOI to developed a low-power RF CMOS device, resulting in increased radio frequency, at IBM.[27]

Commercialization

Ghavam Shahidi's research at IBM led to the first commercial use of SOI in mainstream CMOS technology.[26] SOI was first commercialized in 1995, when Shahidi's work on SOI convinced John Kelly, who ran IBM's server division, to adopt SOI in the AS/400 line of server products, which used 220 nm CMOS with copper metallization SOI devices.[27] IBM began to use SOI in the high-end RS64-IV "Istar" PowerPC-AS microprocessor in 2000. Other examples of microprocessors built on SOI technology include AMD's 130 nm, 90 nm, 65 nm, 45 nm and 32 nm single, dual, quad, six and eight core processors since 2001.[33]

In late 2001, IBM was set to introduce 130 nanometer CMOS SOI devices with copper and low-κ dielectric for the back end, based on Shahidi's work.[27] Freescale adopted SOI in their PowerPC 7455 CPU in late 2001. Currently,[when?] Freescale is shipping SOI products in 180 nm, 130 nm, 90 nm and 45 nm lines.[34] The 90 nm PowerPC- and Power ISA-based processors used in the Xbox 360, PlayStation 3, and Wii use SOI technology as well. Competitive offerings from Intel however continue[when?] to use conventional bulk CMOS technology for each process node, instead focusing on other venues such as HKMG and tri-gate transistors to improve transistor performance. In January 2005, Intel researchers reported on an experimental single-chip silicon rib waveguide Raman laser built using SOI.[35]

As for the traditional foundries, on July 2006 TSMC claimed no customer wanted SOI,[36] but Chartered Semiconductor devoted a whole fab to SOI.[37]

Use in high-performance radio frequency (RF) applications

In 1990, Peregrine Semiconductor began development of an SOI process technology utilizing a standard 0.5 μm CMOS node and an enhanced sapphire substrate. Its patented silicon on sapphire (SOS) process is widely used in high-performance RF applications. The intrinsic benefits of the insulating sapphire substrate allow for high isolation, high linearity and electro-static discharge (ESD) tolerance. Multiple other companies have also applied SOI technology to successful RF applications in smartphones and cellular radios.[38][additional citation(s) needed]

Use in photonics

SOI wafers are widely used in silicon photonics.[39] The crystalline silicon layer on insulator can be used to fabricate optical waveguides and other optical devices, either passive or active (e.g. through suitable implantations). The buried insulator enables propagation of infrared light in the silicon layer on the basis of total internal reflection. The top surface of the waveguides can be either left uncovered and exposed to air (e.g. for sensing applications), or covered with a cladding, typically made of silica.[citation needed]

See also

References

  1. ^ a b Celler, G. K.; Cristoloveanu, S. (2003). "Frontiers of silicon-on-insulator" (PDF). J Appl Phys. 93 (9): 4955. doi:10.1063/1.1558223.
  2. ^ Marshall, Andrew; Natarajan, Sreedhar (2002). SOI design: analog, memory and digital techniques. Boston: Kluwer. ISBN 0792376404.
  3. ^ Colinge, Jean-Pierre (1991). Silicon-on-Insulator Technology: Materials to VLSI. Berlin: Springer Verlag. ISBN 978-0-7923-9150-0.
  4. ^ Silicon-on-insulator - SOI technology and ecosystem - Emerging SOI applications by Horacio Mendez, Executive Director of the SOI Industry Consortium, April 9, 2009
  5. ^ "Archived copy" (PDF). Archived from the original (PDF) on 2013-04-18. Retrieved 2014-04-12.{{cite web}}: CS1 maint: archived copy as title (link)
  6. ^ "IBM touts chipmaking technology". cnet.com. 29 March 2001. Retrieved 22 April 2018.
  7. ^ United States Patent 6,835,633 SOI wafers with 30-100 Ang. Buried OX created by wafer bonding using 30-100 Ang. thin oxide as bonding layer
  8. ^ United States Patent 7,002,214 Ultra-thin body super-steep retrograde well (SSRW) FET devices
  9. ^ Ultrathin-body SOI MOSFET for deep-sub-tenth micron era; Yang-Kyu Choi; Asano, K.; Lindert, N.; Subramanian, V.; Tsu-Jae King; Bokor, J.; Chenming Hu; Electron Device Letters, IEEE; Volume 21, Issue 5, May 2000 Page(s):254 - 255
  10. ^ United States Patent 7138685 " Vertical MOSFET SRAM cell" describes SOI buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures.
  11. ^ F. Balestra, Characterization and Simulation of SOI MOSFETs with Back Potential Control, PhD thesis, INP-Grenoble, 1985
  12. ^ F. Balestra, Challenges to Ultralow-Power Semiconductor Device Operation, in "Future Trends in Microelectronics-Journey into the unknown", S. Lury, J. Xu, A. Zaslavsky Eds., J. Wiley & Sons, 2016
  13. ^ U.S. patent 5,888,297 Method of fabricating SOI substrate Atsushi Ogura, Issue date: Mar 30, 1999
  14. ^ U.S. patent 5,061,642 Method of manufacturing semiconductor on insulator Hiroshi Fujioka, Issue date: Oct 29, 1991
  15. ^ "SemiConductor Wafer Bonding: Science and Technology" by Q.-Y. Tong & U. Gösele, Wiley-Interscience, 1998, ISBN 978-0-471-57481-1
  16. ^ U.S. patent 4,771,016 Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor, George Bajor et al., Issue date: Sep 13, 1988
  17. ^ "SIGEN.COM". www.sigen.com. Retrieved 22 April 2018.
  18. ^ ELTRAN - Novel SOI Wafer Technology Archived 2007-09-27 at the Wayback Machine, JSAPI vol.4
  19. ^ U.S. patent 5,417,180
  20. ^ Colinge, J.P. (2003). "Multiplate-Gate Silicon-On-Insulator MOS Transistors". Microelectronics Technology and Devices, SBMICRO 2003: Proceedings of the Eighteenth International Symposium. The Electrochemical Society. pp. 2–17. ISBN 9781566773898.
  21. ^ Tasch, A. F.; Holloway, T. C.; Lee, K. F.; Gibbons, J. F. (1979). "Silicon-on-insulator m.o.s.f.e.t.s fabricated on laser-annealed polysilicon on SiO2". Electronics Letters. 15 (14): 435–437. doi:10.1049/el:19790312.
  22. ^ Kawamura, S.; Sasaki, N.; Iwai, T.; Mukai, R.; Nakano, M.; Takagi, M. (December 1983). "3-Dimensional SOI/CMOS IC's fabricated by beam recrystallization". 1983 International Electron Devices Meeting: 364–367. doi:10.1109/IEDM.1983.190517.
  23. ^ Kawamura, S.; Sasaki, Nobuo; Iwai, T.; Mukai, R.; Nakano, M.; Takagi, M. (1984). "3-Dimensional Gate Array with Vertically Stacked Dual SOI/CMOS Structure Fabricated by Beam Recrystallization". 1984 Symposium on VLSI Technology. Digest of Technical Papers: 44–45.
  24. ^ Colinge, J.P. (2008). FinFETs and Other Multi-Gate Transistors. Springer Science & Business Media. p. 11. ISBN 9780387717517.
  25. ^ Sekigawa, Toshihiro; Hayashi, Yutaka (1 August 1984). "Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate". Solid-State Electronics. 27 (8): 827–828. doi:10.1016/0038-1101(84)90036-4. ISSN 0038-1101.
  26. ^ a b "Ghavam G. Shahidi". IEEE Xplore. Institute of Electrical and Electronics Engineers. Retrieved 16 September 2019.
  27. ^ a b c d "SOI scientist counted among latest IBM fellows". EE Times. 30 May 2001.
  28. ^ "Ghavam Shahidi". Engineering and Technology History. Institute of Electrical and Electronics Engineers. Retrieved 16 September 2019.
  29. ^ Shahidi, Ghavam G.; Davari, Bijan; Dennard, Robert H.; Anderson, C. A.; Chappell, B. A.; et al. (December 1994). "A room temperature 0.1 µm CMOS on SOI". IEEE Transactions on Electron Devices. 41 (12): 2405–2412. doi:10.1109/16.337456.
  30. ^ Critchlow, D. L. (2007). "Recollections on MOSFET Scaling". IEEE Solid-State Circuits Society Newsletter. 12 (1): 19–22. doi:10.1109/N-SSC.2007.4785536.
  31. ^ Tsu‐Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley. Symposium on VLSI Technology Short Course. Retrieved 9 July 2019.
  32. ^ Hisamoto, Digh; Hu, Chenming; Huang, Xuejue; Lee, Wen-Chin; Kuo, C.; et al. (May 2001). "Sub-50 nm P-channel FinFET" (PDF). IEEE Transactions on Electron Devices. 48 (5): 880–886. doi:10.1109/16.918235.
  33. ^ Vries, Hans de. "Chip Architect: Intel and Motorola/AMD's 130 nm processes to be revealed". chip-architect.com. Retrieved 22 April 2018.
  34. ^ "NXP Semiconductors - Automotive, Security, IoT". www.freescale.com. Retrieved 22 April 2018.
  35. ^ "An all-silicon Raman laser" (PDF). Nature. 433: 292–294. January 2005. doi:10.1038/nature03723. {{cite journal}}: Unknown parameter |authors= ignored (help)
  36. ^ "TSMC has no customer demand for SOI technology - Fabtech - The online information source for semiconductor professionals". fabtech.org. Archived from the original on 28 September 2007. Retrieved 22 April 2018.
  37. ^ Chartered expands foundry market access to IBM's 90nm SOI technology
  38. ^ Madden, Joe. "Handset RFFEs: MMPAs, Envelope Tracking, Antenna Tuning, FEMs, and MIMO" (PDF). Mobile Experts. Archived from the original (PDF) on 4 March 2016. Retrieved 2 May 2012.
  39. ^ Reed, Graham T.; Knights, Andrew P. (5 March 2004). "Silicon Photonics: An Introduction". Wiley. Retrieved 22 April 2018 – via Google Books.
  • SOI Industry Consortium - a site with extensive information and education for SOI technology
  • SOI IP portal - A search engine for SOI IP
  • AMDboard - a site with extensive information regarding SOI technology
  • Advanced Substrate News - a newsletter about the SOI industry, produced by Soitec
  • MIGAS '04 - The 7th session of MIGAS International Summer School on Advanced Microelectronics, devoted to SOI technology and devices
  • MIGAS '09 - 12th session of the International Summer School on Advanced Microelectronics: "Silicon on Insulator (SOI) Nanodevices"
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