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Cavium

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Cavium, Inc.
Company typePublic
IndustryProcessors and Boards
Founded2001; 23 years ago (2001)
DefunctJuly 6, 2018; 6 years ago (2018-07-06)
FateAcquired by Marvell Technology Group
Headquarters
San Jose, California
,
United States
Key people
Syed Ali (President & CEO)
Raghib Hussain
Founder & COO
ProductsMicroprocessors, boards
Number of employees
850[1]

Cavium was a fabless semiconductor company based in San Jose, California, specializing in ARM-based and MIPS-based network, video and security processors and SoCs.[2] The company was co-founded by Syed B. Ali and M. Raghib Hussain,[3] who were introduced to each other by a Silicon Valley entrepreneur. Cavium offers processor- and board-level products targeting routers, switches, appliances, storage and servers.

The company went public in May 2007 with about 175 employees. As of 2011, following numerous acquisitions, it had about 850 employees worldwide, of whom about 250 were located at company headquarters in San Jose.

Cavium is owned by Marvell Technology Group since July 2018.[4]

History

Name change

On June 17, 2011, Cavium Networks, Inc. changed their name to Cavium, Inc.[5]

Acquisitions

Date Acquired company Historical product line
August 2008 Star Semiconductor ARM-based systems-on-chip processors[6]
December 2008 W&W Communications Video compression software and hardware[7]
December 2009 MontaVista Software Carrier Grade Linux compliant Linux & embedded systems[8]
January 2011[9] Celestial Semiconductor SoCs for digital media applications, including satellite, cable, and Internet TV[10]
February 2011 Wavesat Telecommunications Semiconductor solutions for carrier and mobile device manufacturers[11]
July 2014 Xpliant, Inc. Switching and SDN Specialist[12]
June 2016 QLogic, Inc. Ethernet and Storage Specialist[13]

Acquisition

In November 2017, Cavium's board of directors agreed to the company's purchase by Marvell Technology Group for $6 billion in cash and stock.[14] The merger was finalized in July 2018.

Products

cnMIPS microarchitecture

The cnMIPS microarchitecture implements the MIPS64 instruction set.

cnMIPS II microarchitecture

cnMIPS III microarchitecture

OCTEON SoCs

[15]

Model Launch Fab (nm) cnMIPS I-cores Notes
# Core clock (MHz) L2 cache
[KB]
CN3005 2002 90 1 300–500 64
CN3010 1 128
CN3110 1 256
CN3120 2 256
CN3630 4 400–600 512
CN3830 4 1024
CN3840 8 1024
CN3850 12 1024
CN3860 16 1024

OCTEON Plus SoCs

[16]

Model Launch Fab (nm) cnMIPS I-cores Notes
# Core clock (MHz) L2 cache
[KB]
CN5010 90 1 300–700 128
CN5020 2 128
CN5220 2 500–800 512
CN5230 4 512
CN5430 4 500–700 1024
CN5434 6 1024
CN5530 4 1024
CN5534 6 1024
CN5640 8 600–800 2048
CN5645 10 2048
CN5650 12 2048
CN5740 8 2048
CN5745 10 2048
CN5750 12 2048
CN5830 4 2048
CN5840 8 2048
CN5850 12 2048
CN5860 16 2048

OCTEON II SoCs

[17]

Model Launch Fab (nm) cnMIPS II-cores Notes
# Core clock (MHz) L2 cache
[KB]
CN6010 65 1 400–800 512
CN6020 2 512
CN6120 2 600–1200 1024
CN6130 4 1024
CN6220 2 800–1000 1024
CN6230 4 1024
CN6320 2 800–1500 2048
CN6330 4 2048
CN6335 6 2048
CN6635 6 2048
CN6645 10 2048
CN6740 8 4096
CN6760 16 4096
CN6860 16 800–1400 4096
CN6870 24 4096
CN6880 32 4096

OCTEON III SoCs

[18] [19]

Model Launch Fab (nm) cnMIPS III-cores Notes
# Core clock (MHz) L2 cache
[KB]
CN7010 28 1 800–1200 512
CN7020 2 512
CN7120 2 800–1600 512
CN7125 3 512
CN7130 4 512
CN7760 16 1600–2500 8192
CN7770 24 8192
CN7870 24 16384
CN7880 32 16384
CN7890 48 16384

ThunderX SoCs

The ThunderX line of SoCs from Cavium were released with up to 48 dual issue, out of order ARMv8 cores.[20][21] These SoCs were targeted at servers in network intensive applications, competing with Intel Xeon products.[22] The ThunderX line is manufactured by Global Foundries at 28 nm and is reported to have a TDP less than 100W.[22]

Model Launch Fab (nm) ARMv8-A-cores Notes
# Core clock (MHz)
CN87xx_xx 2014 28 8–16 Up to 2500
CN88xx_xx 2014 24–48 Up to 2500

Sandia National Laboratories' second generation supercomputer in their Vanguard project called Sullivan was based Cavium's ThunderX processors. The first generation was called Hammer, it was based on X-Gene by Applied Micro.[23]

ThunderX2 SoCs

Cavium announced in 2016 the ThunderX2 line of SoCs, initially as iterative improvement of their ThunderX line.[22][24] The name was later used for the former Vulcan SoC design purchased from Broadcom.[25][26] ThunderX2 has up to 32 custom ARM cores and is manufactured on Global Foundries' 16 nm FinFET process. These and other improvements are reported to offer twice the performance per core of the ThunderX line.

Cray has added "ARM Option" (i.e. CPU blade option, using the ThunderX2) to their XC50 supercomputers, and Cray states that ARM is "a third processor architecture for building next-generation supercomputers", for clients such as the US Department of Energy.[27]

The Cray XC50-series supercomputer for the University of Bristol is called Isambard, named after Isambard Kingdom Brunel. The supercomputer is expected to feature around 160 nodes, each with two 32-core ThunderX2 processors running at 2.1 GHz. Peak theoretical performance of the 10,240 cores and 40,960 threads is 172 teraFLOPS.[28]

The third generation of the Sandia National Laboratories' Vanguard project called Mayer was based on pre-production ThunderX2 and consisted of 47 nodes. The fourth generation also based on ThunderX2 is called Astra and will become operation by November 2018. Each Astra node will feature two 28-core ThunderX2 processors running at 2.0 GHz with 128 GB DDR4. Each rack has 18x Hewlett Packard Enterprise Apollo 70 chassis with 72 compute nodes along with 3 InfiniBand switches. Astra will feature a total of 36 racks. Thus Astra will have 5,184 ThunderX2 processors, 145,152 ThunderX2 cores and 580,608 threads. Astra's peak theoretical performance is 4.644 PFLOPS in Single Precision, and 2.322 PFLOPS in Double Precision and will support 324 TB DDR4.[23] Astra is the first ARM-based Petascale supercomputer to enter the TOP500 list. In November 2018 it is ranked at 204, while as of June 2019 it's ranked at 156 after an upgrade.[29]

ThunderX2/Vulcan core

Microarchitecture[30][28]:

  • ISA: ARMv8.1
  • L1-instruction cache: 32 KB with 8-way associativity and Instruction TLB
  • L1-data cache: 32 KB with 8-way associativity with 64 entries Load buffer and 36 entries Store Buffer & Forwarding
  • Load bandwith: 2x 16B
  • L2 cache: 256 KB with 8-way with associativity and 2048-entry STLB
  • L3 cache: 1 MB/core
  • Fetch Width: 8 instructions (32-byte window)
  • Decode width: 4
  • Sustainable instructions/cycle: 4
  • Loop buffer: 128 entries
  • Instructions in flight: 180-entry ReOrder Buffer (ROB)
  • Scheduler/Issue queue: Unified 60 entries
  • Issue: 6
  • Pipeline: 13–15 stages

CN99XX

Its specs[30]:

  • Up to 32x ThunderX2 cores in ring bus
  • Up to Base Frequency of 2.2 GHz and turbo frequency up to 2.5 GHz
  • Up to 128 threads (SMT4)
  • Up to 32 MB L3 cache
  • Up to 8-channel DDR4
  • Up to 56x PCIe 3.0 lanes
  • TSMC 16 nm
  • Up to TDP: 180W
  • Multiprocessing: 1S and 2S configurations with 600 Gb/s bandwidth using Cavium's Coherent Processor Interconnect 2 (CCPI2)


References

  1. ^ "Cavium Networks Inc. returns to San Jose". Silicon Valley Business News. 8 July 2011. Retrieved 2015-01-08.
  2. ^ New York Times Company Profile for Cavium Inc. Archived March 5, 2016, at the Wayback Machine
  3. ^ "Syed Ali's company Cavium gets acquired for $6 billion". techober.com. Retrieved 2017-11-24.
  4. ^ Shilov, Anton. "Marvell Completes Acquisition of Cavium, Gets CPU, Networking & Security Assets". www.anandtech.com. Retrieved 2019-09-01.
  5. ^ http://biz.yahoo.com/e/110620/cavm8-k.html [dead link‍]
  6. ^ "Cavium Networks Completes Acquisition of Taiwan-Based Star Semiconductor". cavium.com (Press release).
  7. ^ "Cavium Networks Completes Acquisition of W&W Communications". cavium.com.
  8. ^ "Cavium Networks Completes Acquisition of MontaVista Software | embedded virtualization" (Press release). December 18, 2009. Archived from the original on 2016-06-12.
  9. ^ McGrath, Dylan (31 January 2011). "Cavium buys Chinese fabless chip firm". EE Times. Retrieved 17 February 2011.
  10. ^ "Company Overview". Celestial Semiconductor. Archived from the original on 2011-03-09. Retrieved 17 February 2011.
  11. ^ "Wavesat | CrunchBase". www.crunchbase.com. Retrieved 2016-07-10.
  12. ^ "Cavium to Acquire Switching and SDN Specialist Xpliant to Accelerate Deployment of Software Defined Networks" (Press release).
  13. ^ "Company press release: Cavium to Acquire QLogic - Opportunity to drive significant growth at scale in data center and storage markets" (Press release). Archived from the original on 2017-01-14. Retrieved 2017-01-15.
  14. ^ PALLADINO, Valentina (20 November 2017). "Marvell Technology to buy chipmaker Cavium for about $6 billion". Ars Technica. Retrieved 20 November 2017.
  15. ^ Cavium.com: Cavium Octeon SoCs Product Table Archived October 20, 2016, at the Wayback Machine
  16. ^ Cavium.com: Cavium Octeon Plus SoCs Product Table Archived October 20, 2016, at the Wayback Machine
  17. ^ Cavium.com: Cavium Octeon II SoCs Product Table Archived October 20, 2016, at the Wayback Machine
  18. ^ Cavium.com: Cavium Octeon III SoCs Product Table Archived October 20, 2016, at the Wayback Machine
  19. ^ Cavium.com: Cavium Octeon III SoCs Product CN77XX Table Archived October 20, 2016, at the Wayback Machine
  20. ^ De Gelas, Johan (16 December 2014). "ARM Challenging Intel in the Server Market". Anandtech. Retrieved 8 March 2017.
  21. ^ Cavium.com ThunderX product page Archived November 24, 2016, at the Wayback Machine
  22. ^ a b c De Gelas, Johan (15 June 2016). "Investigating the Cavium ThunderX". Anandtech. Retrieved 8 March 2017.
  23. ^ a b Schor, David (2018-08-25). "Cavium Takes ARM to Petascale with Astra". WikiChip Fuse. Retrieved 2019-05-27.
  24. ^ Russell, John (31 May 2016). "Cavium Unveils ThunderX2 Plans, Reports ARM Traction is Growing". HPC Wire. Retrieved 8 March 2017.
  25. ^ "⚙ D30510 Vulcan is now ThunderX2T99". reviews.llvm.org.
  26. ^ Kampman, Jeff (5 January 2018). "Scaling Raven Ridge with David Kanter: The TR Podcast 191". Tech Report. Retrieved 5 January 2018.
  27. ^ "Cray Adds ARM Option to XC50 Supercomputer | TOP500 Supercomputer Sites". www.top500.org. Retrieved 2017-11-14. Cray claims its ARM compiler demonstrated better performance in two-thirds of 135 benchmarks, and much better performance – 20 percent or more – in one-third of them, compared to open source ARM compilers from LLVM and GNU. The Cray ThunderX2 blades can be mixed with other XC50 blades outfitted with Intel Xeon-SP or Xeon Phi processors and NVIDIA Tesla GPUs. Both air-cooled and liquid-cooled options are available. Cray already has one customer lined up for the ThunderX2-powered XC50: the Great Western 4 (GW4) Alliance, a research consortium of four UK universities (Bristol, Bath, Cardiff and Exeter). In January 2017, the alliance announced it had contracted Cray to build "Isambard", a 10,000-core ARM-based supercomputer, which will provide a Tier 2 HPC service. The UK's Met Office was also involved on the deal, since it was interested in seeing how its weather and climate codes would run on such a machine. The system will be paid for out of a £3 million award from the Engineering and Physical Sciences Research Council (EPSRC). It's scheduled to be fully deployed by the end of this year.
  28. ^ a b "A Look at Cavium's New High-Performance ARM Microprocessors and the Isambard Supercomputer". WikiChip Fuse. 2018-06-03. Retrieved 2019-05-27.
  29. ^ "Astra - Apollo 70, Cavium ThunderX2 CN9975-2000 28C 2GHz, 4xEDR Infiniband | TOP500 Supercomputer Sites". www.top500.org. Retrieved 2019-08-17.
  30. ^ a b Gelas, Johan De. "Assessing Cavium's ThunderX2: The Arm Server Dream Realized At Last". www.anandtech.com. Retrieved 2019-05-27.
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