Wallace tree

basic principle known from manual multiplication. Image shows a manual example of multiplying 345(top) by 12(side).

Example of reduction on an 8x8 multiplier.

A Wallace tree is an efficient hardware implementation of a digital circuit that multiplies two integers. It was devised by the Australian computer scientist Chris Wallace in 1964.

The Wallace tree has three steps:

1. Multiply each bit of one of the arguments, by each bit of the other.
2. Reduce the number of partial products to two by layers of full and half adders.
3. Group the wires in two numbers, and add them with a conventional adder.

The benefit of the Wallace tree is that there are only $O(\log n)$ reduction layers, and each layer has $O(1)$ propagation delay. As making the partial products is $O(1)$ and the final addition is $O(\log n)$, the multiplication is only $O(\log n)$, not much slower than addition (however, much more expensive in the gate count). Naively adding partial products with regular adders would require $O(\log ^{2}n)$ time. From a complexity theoretic perspective, the Wallace tree algorithm puts multiplication in the class NC¹.

These computations only consider gate delays and don't deal with wire delays, which can also be very substantial.

The Wallace tree can be also represented by a tree of 3/2 or 4/2 adders.

It is sometimes combined with Booth encoding.

Detailed explanation

The Wallace tree is a variant of long_multiplication. The first step is to multiply each digit (each bit) of one factor by each digit of the other. Each of this partial products has weight equal to the product of its factors. The final product is calculated by the weighted sum of all partial these partial products.

The first step, as said above, is to multiply each bit of one number by each bit of the other, which is accomplished as a simple and gate, resulting in $2^{n}$ bits; the partial product of bits $a_{m}$ by $b_{n}$ has weight $2^{(}m+n)$

In the second step, the resulting bits are reduced to two numbers; this is accomplished as follows: As long as there are three or more wires with the same weight add a following layer:-

• Take any three wires with the same weights and input them into a full adder. The result will be an output wire of the same weight and an output wire with a higher weight for each three input wires.
• If there are two wires of the same weight left, input them into a half adder.
• If there is just one wire left, connect it to the next layer.

In the third and final step, the two resulting numbers are fed to a adder, obtaining the final product

Example

$n=4$, multiplying $a_{3}a_{2}a_{1}a_{0}$ by $b_{3}b_{2}b_{1}b_{0}$:

1. First we multiply every bit by every bit:
   • weight 1 – $a_{0}b_{0}$
   • weight 2 – $a_{0}b_{1}$, $a_{1}b_{0}$
   • weight 4 – $a_{0}b_{2}$, $a_{1}b_{1}$, $a_{2}b_{0}$
   • weight 8 – $a_{0}b_{3}$, $a_{1}b_{2}$, $a_{2}b_{1}$, $a_{3}b_{0}$
   • weight 16 – $a_{1}b_{3}$, $a_{2}b_{2}$, $a_{3}b_{1}$
   • weight 32 – $a_{2}b_{3}$, $a_{3}b_{2}$
   • weight 64 – $a_{3}b_{3}$
2. Reduction layer 1:
   • Pass the only weight-1 wire through, output: 1 weight-1 wire
   • Add a half adder for weight 2, outputs: 1 weight-2 wire, 1 weight-4 wire
   • Add a full adder for weight 4, outputs: 1 weight-4 wire, 1 weight-8 wire
   • Add a full adder for weight 8, and pass the remaining wire through, outputs: 2 weight-8 wires, 1 weight-16 wire
   • Add a full adder for weight 16, outputs: 1 weight-16 wire, 1 weight-32 wire
   • Add a half adder for weight 32, outputs: 1 weight-32 wire, 1 weight-64 wire
   • Pass the only weight-64 wire through, output: 1 weight-64 wire
3. Wires at the output of reduction layer 1:
   • weight 1 – 1
   • weight 2 – 1
   • weight 4 – 2
   • weight 8 – 3
   • weight 16 – 2
   • weight 32 – 2
   • weight 64 – 2
4. Reduction layer 2:
   • Add a full adder for weight 8, and half adders for weights 4, 16, 32, 64
5. Outputs:
   • weight 1 – 1
   • weight 2 – 1
   • weight 4 – 1
   • weight 8 – 2
   • weight 16 – 2
   • weight 32 – 2
   • weight 64 – 2
   • weight 128 – 1
6. Group the wires into a pair of integers and an adder to add them.

See also

• Dadda tree

Further reading

• Savard, John J. G. (2018) [2006]. "Advanced Arithmetic Techniques". quadibloc. Archived from the original on 2018-07-03. Retrieved 2018-07-16.

External links

• Generic VHDL Implementation of Wallace Tree Multiplier.