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List of Intel CPU microarchitectures

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The following is a partial list of Intel CPU microarchitectures. The list is incomplete. Additional details can be found in Intel's Tick-Tock model and Process-Architecture-Optimization model.

x86 microarchitectures

Note: Intel Atom processors are in italic.

Year Micro-architecture Pipeline stages Max
Clock

[MHz]

Tech
process

[nm]

1978 8086 (8086, 8088) 2 5 3000
1982 186 (80186, 80188) 2 25 3000
1982 286 (80286) 3 25 1500
1985 386 (80386) 3 33 1500
1989 486 (80486) 5 100 1000
1993 P5 (Pentium) 5 200 800, 600, 350
1995 P6 (Pentium Pro, Pentium II) 14 (17 with load & store/retire) 450 500, 350, 250
1997 P5 (Pentium MMX) 6 233 350
1999 P6 (Pentium III) 12 (15 with load & store/retire) 1400 250, 180, 130
2000 NetBurst (Pentium 4)
(Willamette) 		20 unified with branch prediction 2000 180
2002 NetBurst (Pentium 4)
(Northwood, Gallatin) 		3466 130
2003 Pentium M (Banias, Dothan)
Enhanced Pentium M (Yonah) 		10 (12 with fetch/retire) 2333 130, 90, 65
2004 NetBurst (Pentium 4)
(Prescott) 		31 unified with branch prediction 3800 90
2006 Intel Core 12 (14 with fetch/retire) 3000 65
2007 Penryn (die shrink) 3333 45
2008 Nehalem 20 unified (14 without miss prediction) 3600
Bonnell 16 (20 with prediction miss) 2100
2010 Westmere (die shrink) 20 unified (14 without miss prediction) 3730 32
2011 Saltwell (die shrink) 16 (20 with prediction miss) 2130
Sandy Bridge 14 (16 with fetch/retire) 4000
2012 Ivy Bridge (die shrink) 4100 22
2013 Silvermont 14–17 (16–19 with fetch/retire) 2670
Haswell 14 (16 with fetch/retire) 4400
2014 Broadwell (die shrink) 3700 14
2015 Airmont (die shrink) 14–17 (16–19 with fetch/retire) 2640
Skylake 14 (16 with fetch/retire) 4200
2016 Goldmont 20 unified with branch prediction 2600
Kaby Lake 14 (16 with fetch/retire) 4500
2017 Coffee Lake 5000
Goldmont Plus ? 20 unified with branch prediction ? 2800
2018 Cannon Lake (die shrink?) 14 (16 with fetch/retire) 3200 10
Whiskey Lake 4800 14
Amber Lake 4200
2019 Cascade Lake 4400
Comet Lake 5300
Sunny Cove (Ice Lake) 14–20 3900 10
2020 Tremont (Lakefield, Snow Ridge,
Jacobsville, Elkhart Lake, Jasper Lake)
Cooper Lake 14 (16 with fetch/retire) 14
Willow Cove (Tiger Lake) 10
(2021) Golden Cove (Alder Lake) 10
(2021) Gracemont 10
(2022) Meteor Lake 7
8086
first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80. 8088 version, with an 8-bit bus, used in the original IBM Personal Computer.
186
included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions. The 80188 was a version with an 8-bit bus.
286
first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3...4 over 8086. Included instructions relating to protected mode.
i386
first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.
i486
Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.
P5
original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction.
P6
used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, RISC μop decode scheme, integrated register renaming and out-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension (PAE)".
NetBurst
commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to implement executable-space protection.
Pentium M
updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache.
Intel Core
reengineered P6-based microarchitecture used in Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.
  • Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, SSE4.1 instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file.
Nehalem
released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2.
  • Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.
Bonnell
45 nm, low-power, in-order microarchitecture for use in Atom processors.
  • Saltwell: 32 nm shrink of the Bonnell microarchitecture.
Larrabee (cancelled 2010)
multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core).
Sandy Bridge
32 nm microarchitecture, released January 9, 2011. Formerly called Gesher but renamed in 2007.[1] First x86 to introduce 256 bit AVX instruction set and implementation of YMM register.
  • Ivy Bridge: successor to Sandy Bridge, using 22 nm process, released in April 2012.
Silvermont
22 nm, out-of-order microarchitecture for use in Atom processors, released May 6, 2013.
  • Airmont: 14 nm shrink of the Silvermont microarchitecture.
Haswell
22 nm microarchitecture, released June 3, 2013. Added a number of new instructions, including FMA.
  • Broadwell: 14 nm shrink of the Haswell microarchitecture, released in September 2014. Formerly called Rockwell.
Skylake
14 nm microarchitecture, released August 5, 2015.
  • Kaby Lake: successor to Skylake, released in August 2016, broke Intel's Tick-Tock schedule due to delays with the 10 nm process.
    • Amber Lake: ultra low power, mobile-only successor to Kaby Lake, using 14+ nm process, released in August 2018 (no architecture changes)[2]
    • Whiskey Lake: mobile-only successor to Kaby Lake Refresh, using 14++ nm process, released in August 2018 (has hardware mitigations for some vulnerabilities)[2]
  • Coffee Lake: successor to Kaby Lake, using 14+ nm process, released in October 2017
  • Cascade Lake: server and high-end desktop successor to Kaby Lake-X, using 14 nm process, released in April 2019
  • Comet Lake: successor to Coffee Lake, using 14++ nm process, released in August 2019
  • Cooper Lake: server-only architecture, optimized for AI oriented workloads using bfloat16, with limited availability only to Intel priority partners, using 14++ nm process, to be released in 2020[3][4]
Goldmont
14 nm Atom microarchitecture iteration after Silvermont but borrows heavily from Skylake processors (e.g., GPU), released April 2016.[5][6]
  • Goldmont Plus: successor to Goldmont microarchitecture, still based on the 14 nm process, released December 11, 2017.
Tremont
10 nm Atom microarchitecture iteration after Goldmont Plus.[7]
Palm Cove
After releasing the Palm Cove core, Intel has changed their microarchitecture naming scheme, decoupling the CPU cores from their manufacturing nodes.[8][additional citation(s) needed]
Successor to the Skylake core, first consumer core to include the AVX-512 instruction set.[9][better source needed] (That's if you don't count Skylake-X as consumer core, which also has AVX-512 and appeared on the market 11 months before Cannon Lake.)
  • Cannon Lake: mobile-only successor of Kaby Lake, using 10 nm process, first and only microarchitecture to implement the Palm Cove core, released in May 2018. Formerly called Skymont, discontinued in December 2019.[10]
Sunny Cove
Successor to the Palm Cove core, first core to include hardware acceleration for SHA hashing algorithms.[11]
  • Ice Lake: low power, mobile-only successor to Whiskey Lake, using 10+ nm process, released in September 2019
  • Ice Lake-SP: server-only successor to Cascade Lake, using 10+ nm process, to be released in 2020[12]
Willow Cove
Successor to the Sunny Cove core, includes new security features and redesigns the cache subsystem.[13]
  • Tiger Lake: successor to Ice Lake, using 10++ nm process, released in Q4 2020
  • Rocket Lake: successor to Comet Lake, using 14++ nm process, to be released in 2H 2020[14][15][16]
  • Sapphire Rapids: server-only, successor to Ice Lake-SP, using 10++ nm process, to be released in 2021[17]
Golden Cove
Successor to the Willow Cove core, includes improvements to single threaded performance, AI performance, network and 5G performance and new security features.[18]
  • Alder Lake: successor to Tiger Lake, using 10++ nm process, to be released in 2021[19]
Ocean Cove
Successor to the Golden Cove core.

Itanium microarchitectures

Merced
original Itanium microarchitecture. Used only in the first Itanium microprocessors.
McKinley
enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor.
Montecito
enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements.
Tukwila
enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, SMT, an integrated memory controller, QuickPath Interconnect, and other improvements.
Poulson
Itanium processor featuring a new microarchitecture.[20]
Kittson
the last Itanium microarchitecture. It has slightly higher clock speed than Poulson.

Roadmap

Pentium 4 / Core lines

Pentium 4 / Core roadmap
Fabrication
process 		Micro-
architecture 		Code
names 		Core i
generation 		Release
date 		Processors
Desktop Mobile Enthusiast/WS 2P
Server/WS 		4P/8P
Server
180 nm P6,
NetBurst 		Willamette N/A 2000-11-20 Willamette Foster
130 nm Northwood/
Mobile Pentium 4
Banias
 2002-01-07 Northwood Northwood Mobile
Banias
 Northwood-XE Prestonia
Gallatin
90 nm Prescott
Dothan
 2004-02-01 Prescott
Smithfield 		Dothan
 Prescott 2M-XE
Smithfield-XE 		Nocona
Irwindale
Paxville
Cranford
Potomac
65 nm Cedar Mill
Yonah
Presler 		2006-01-05 Cedar Mill
Presler 		Yonah Presler-XE Dempsey
Sossaman 		Tulsa
Core Merom[21] 2006-07-27
[22][23] 		Conroe Merom Kentsfield Woodcrest
Clovertown 		Tigerton
45 nm Penryn 2007-11-11
[24] 		Wolfdale Penryn Yorkfield Harpertown Dunnington
Nehalem Nehalem Previous[25] 2008-11-17
[26] 		Lynnfield Clarksfield Bloomfield Gainestown Beckton
32 nm Westmere 2010-01-04
[27][28] 		Clarkdale Arrandale Gulftown Westmere-EP Westmere-EX
Sandy
Bridge 		Sandy Bridge 2 2011-01-09
[29] 		Sandy Bridge Sandy Bridge-M Sandy Bridge-E Sandy Bridge-EP –[30]
22 nm Ivy Bridge 3 2012-04-29 Ivy Bridge Ivy Bridge-M Ivy Bridge-E
[31] 		Ivy Bridge-EP
[32] 		Ivy Bridge-EX
[32]
Haswell Haswell 4 2013-06-02 Haswell-DT
[33] 		Haswell-MB
(37–57W TDP, PGA package)
Haswell-H
(47W TDP, BGA package)
Haswell-ULP/ULX
(11.5–15W TDP)[33] 		Haswell-E Haswell-EP Haswell-EX
Devil's
Canyon 		2014-06 Haswell-DT N/A
14 nm Broadwell 5 2014-09-05 Broadwell-DT Broadwell-H (37–47W TDP)
Broadwell-U (15–28W TDP)
Broadwell-Y (4.5W TDP) 		Broadwell-E Broadwell-EP
[34] 		Broadwell-EX
[34]
Skylake Skylake 6 2015-08-05
[35] 		Skylake-S Skylake-H (35–45W TDP)
Skylake-U (15–28W TDP)
Skylake-Y (4.5W TDP) 		Skylake-X[36]
Skylake-W 		Skylake-SP
(formerly Skylake-EP/-EX)[37]
Kaby Lake 7 / 8 2016-10 Kaby Lake-S Kaby Lake-G (65–100W TDP)
Kaby Lake-H (35–45W TDP)
Kaby Lake-U (15–28W TDP)
Kaby Lake-Y (4.5W TDP) 		Kaby Lake-X
[36] 		N/A
Coffee Lake 8 / 9 2017-10
[38] 		Coffee Lake-S Coffee Lake-B (65W TDP)
Coffee Lake-H (35–45W TDP)
Coffee Lake-U (15–28W TDP) 		N/A
Whiskey Lake 8 2018-08-28 N/A Whiskey Lake-U (15W TDP)
Amber Lake 8 / 10 Amber Lake-Y (5–7W TDP)
Skylake + DLBoost Cascade Lake N/A 2019-04-02 N/A Cascade Lake-X

Cascade Lake-W

Cascade Lake-SP

Cascade Lake-SP
Skylake Comet Lake 10 2019-09[a] Comet Lake-S Comet Lake-H (45W TDP)

Comet Lake-U (15W TDP)[39]
Comet Lake-Y (7W TDP)[39]

N/A
Skylake + DLBoost Cooper Lake N/A 2020 N/A[40][41] Cooper Lake-SP
? Rocket Lake[42] ? 2020 / 2021 Rocket Lake-S Rocket Lake-U N/A
10 nm Palm Cove Cannon Lake 8 2018-05[a] N/A Cannon Lake-U (15W TDP) N/A
Sunny Cove[43] Ice Lake 10 2019-09[a] N/A Ice Lake-U (15–28W TDP)[44]
Ice Lake-Y (9W TDP)[44] 		N/A Ice Lake-SP[45]
Willow Cove Tiger Lake 11 2020-09 N/A Tiger Lake-UP3 (12-28 W)
Tiger Lake-UP4 (7-15 W) 		N/A
Willow Cove[46] Sapphire Rapids N/A 2021[47] N/A Sapphire Rapids-SP
Golden Cove[48] Alder Lake

(hybrid)

? 2021[48]
7 nm ? Meteor Lake ? 2022 / 2023
Granite Rapids 2023[49] Granite Rapids –SP
Fabrication
process 		Micro-
architecture 		Code
names 		Core i
generation 		Release
date 		Desktop Mobile Enthusiast/
WS 		2P
Server/WS 		4P/8P
Server
Processors
  1. ^ a b c retail availability

Hybrid

Hybrid roadmap
Fabrication
processes 		Microarchitectures Code
names 		Release
date 		Processors/SoCs
Compute die Base die Package Core Atom MID, smartphone Tablet Mobile Server
10 nm 14 nm 3D Foveros Sunny Cove Tremont Lakefield 2020 Lakefield —
Lakefield-R
Ryefield 2021/2022

Atom lines

Atom roadmap[50]
Fabri-
cation
process 		Micro-
archi-
tecture 		Release
date 		Processors/SoCs
MID, smartphone Tablet Netbook Nettop Embedded Server Communication CE
45 nm Bonnell 2008 Silverthorne — Diamondville Tunnel Creek,
Stellarton 		— Sodaville
2010 Lincroft Pineview Groveland
32 nm Saltwell 2011 Medfield (Penwell & Lexington),
Clover Trail+ (Cloverview) 		Clover Trail (Cloverview) Cedar Trail (Cedarview) Un­known Centerton & Briarwood Un­known Berryville
22 nm Silvermont 2013 Merrifield (Tangier),[51] Slayton,
Moorefield (Anniedale)[52] 		Bay Trail-T
(Valleyview) 		Bay Trail-M
(Valleyview) 		Bay Trail-D
(Valleyview) 		Bay Trail-I
(Valleyview) 		Avoton Rangeley Un­known
14 nm[50] Airmont 2014 Binghamton & Riverton Cherry Trail-T (Cherryview)[53] Braswell[54] Denverton Cancelled Un­known Un­known
Goldmont
[55] 		2016 Broxton Cancelled Willow Trail Cancelled
Apollo Lake 		Apollo Lake[56] Denverton[57] Un­known Un­known
Goldmont
Plus[58] 		2017 Un­known Un­known Gemini Lake[59]
Gemini Lake Refresh[60] 		Un­known Un­known Un­known
10 nm Tremont[7] 2020 Un­known Lakefield (hybrid) Lakefield (hybrid)
Elkhart Lake
Jasper Lake 		Jacobsville
Snow Ridge[61] 		Un­known Un­known
Gracemont 2021[48] Grand Ridge

See also

References

  1. ^ "An Update On Our Graphics-related Programs". May 25, 2010.
  2. ^ a b Cutress, Ian. "Spectre and Meltdown in Hardware: Intel Clarifies Whiskey Lake and Amber Lake". Retrieved 2018-09-02.
  3. ^ Cutress, Dr Ian. "Intel's Cooper Lake Plans: The Chip That Wasn't Meant to Exist, Fades Away". www.anandtech.com. Retrieved 2020-03-18.
  4. ^ Kennedy, Patrick (2020-03-16). "Intel Cooper Lake Rationalized Still Launching 1H 2020". ServeTheHome. Retrieved 2020-03-18.
  5. ^ "Intel Software Development Emulator".
  6. ^ ""Goldmont"- the sequel to Silvermont Atom?". Retrieved 2020-03-02.
  7. ^ a b Cutress, Dr Ian. "Intel's new Atom Microarchitecture: The Tremont Core in Lakefield". AnandTech. Retrieved 2019-11-17.
  8. ^ Schor, David (December 23, 2018). "Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips". WikiChip Fuse.
  9. ^ "Palm Cove - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2020-01-05.
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  12. ^ Cutress, Dr Ian. "Intel's Cooper Lake Plans: The Chip That Wasn't Meant to Exist, Fades Away". www.anandtech.com. Retrieved 2020-03-18.
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  14. ^ "Intel i225 "Foxville" 2.5GbE PHY Has a Flaw Affecting Performance, "Rocket Lake-S" 2H-2020 Production Confirmed | TechPowerUp}". www.techpowerup.com. Retrieved 2020-04-28.
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  16. ^ btarunr (December 2, 2019). "Intel "Rocket Lake" an Adaptation of "Willow Cove" CPU Cores on 14nm?". TechPowerUp.
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  19. ^ Cutress, Dr. Ian (April 1, 2020). "Intel Updates ISA Manual: New Instructions for Alder Lake, also BF16 for Sapphire Rapids". AnandTech.
  20. ^ Anton Shilov (June 19, 2007). "Intel Plans to change Itanium Micro-Architecture". X-bit Labs. Archived from the original on October 5, 2007. Retrieved 2007-10-05.
  21. ^ Crothers, Brooke (2009-02-10). "Intel moves up rollout of new chips | Nanotech - The Circuits Blog - CNET News". News.cnet.com. Retrieved 2014-02-25.
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  25. ^ "ARK | Your source for information on Intel products". Intel. 2013-05-30. Archived from the original on 2013-05-30. Retrieved 2013-05-30.
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  30. ^ Pop, Sebastian. "Intel Ivy Bridge CPU Range Complete by Next Year".
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  33. ^ a b "Leaked specifications of Haswell GT1/GT2/GT3 IGP". Tech News Pedia. 2012-05-20. Archived from the original on 2012-09-19. Retrieved 2014-02-25.
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  60. ^ "Products (Formerly Gemini Lake Refresh)". Intel ARK (Product Specs). Retrieved 4 November 2019.
  61. ^ "Products formerly Snow Ridge". Intel ARK (Product Specs).
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