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Page title without namespace (`page_title`)	'Via (electronics)'
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Edit summary/reason (`summary`)	'CE. Restored some recently removed contents and refs. Don't remove this without adding corresponding better-quality contents to the article. Rome wasn't built in a day.'
Old content model (`old_content_model`)	'wikitext'
New content model (`new_content_model`)	'wikitext'
Old page wikitext, before the edit (`old_wikitext`)	'{{Short description\|Type of electrical connection}} {{More footnotes\|date=December 2017}} {{For\|the via in integrated circuits\|Through-silicon via}} {{Anchor\|Tented via\|Covered annular ring\|Castellated hole\|DVIA\|Plugged via\|Stacked via\|Staggered via\|Filled via\|Capped via\|Via-in-pad\|Covered via\|Filled microvia\|Blind microvia\|In IC}}<!-- parked anchors from redirects --> A '''via''' (Latin for ''path'' or ''way'') is an [[electrical connection]] between copper layers in a [[printed circuit board]]. Essentially a small drilled hole that goes through two or more adjacent layers, the hole is plated with copper that forms electrical connection through the insulation that separates the copper layers. =={{anchor\|Buried via\|Blind via\|Thermal via\|Through via\|Non-through via}} In printed circuit boards == [[File:Via Types.svg\|thumb\|Different types of vias:<br/> ('''1''') [[Through hole]].<br/> ('''2''') Blind via.<br/> ('''3''') Buried via.<br/>The gray and green layers are nonconducting, while the thin orange layers and red vias are conductive.]] [[File:ViaCurrentCapacity.png\|thumb\|PCB Via current capacity chart showing 1mil Plating Via Current Capacity & Resistance vs Diameter on a 1.6mm PCB]] In [[printed circuit board]] (PCB) design, a via consists of two pads in corresponding positions on different layers of the board, that are electrically connected by a hole through the board. The hole is made conductive by [[electroplating]], or is lined with a tube or a [[rivet]]. High-density multilayer PCBs may have [[microvia]]s: '''blind vias''' are exposed only on one side of the board, while '''buried vias''' connect internal layers without being exposed on either surface. '''Thermal vias''' carry heat away from power devices and are typically used in arrays of about a dozen.<ref>{{Cite news\|title=PCB design: A close look at facts and myths about thermal vias\|url=https://www.edn.com/pcb-design-a-close-look-at-facts-and-myths-about-thermal-vias/}}</ref> A via consists of: # Barrel — conductive tube filling the drilled hole # Pad — connects each end of the barrel to the component, plane, or trace # Antipad — clearance hole between barrel and metal layer to which it is not connected A via, sometimes called PTV or plated-through-via, should not be confused with a plated through hole (PTH). Via is used as an interconnection between copper layers on a PCB while the PTH is generally made larger than vias and is used as a plated hole for acceptance of component leads - such as non-SMT resistors, capacitors, and DIP package IC. PTH can also be used as holes for mechanical connection while vias may not. Another usage of PTH is known as a '''castellated hole''' where the PTH is aligned at the edge of the board so that it is cut in half when the board is milled out of the panel - the main usage is for allowing one PCB to be soldered to another in a stack - thus acting both as a fastener and also as a connector.<ref name="Castell"/> Three major kinds of vias are shown in right figure. The basic steps of making a PCB are: making the substrate material and stacking it in layers; through-drilling of plating the vias; and copper trace patterning using photolithography and etching. With this standard procedure, possible via configurations are limited to through-holes.{{efn\|Well, through-holes per core. It is possible, though more expensive, to create blind or buried vias by using additional cores and lamination steps. It is also possible to backdrill and remove the plating from one side through to the desired layer, which leaves the physical hole as a through-hole, but creates the electrical equivalent of a blind via. That said, if a PCB needs enough layers to justify blind and buried vias, it is probably also using small enough traces packed tightly enough to require (laser-drilled) microvias anyhow.}} Depth-controlled drilling techniques such as using lasers can allow for more varied via types. (Laser drills can also be used for smaller and more precisely positioned holes than mechanical drills produce.) PCB manufacturing typically starts with a so-called core, a basic double-sided PCB. Layers beyond the first two are stacked from this basic building block. If two more layers are consecutively stacked from bottom of core, you can have a 1-2 via, a 1-3 via and a [[through hole]]. Each type of via is made by drilling at each stacking stage. If one layer is stacked on top of the core and other is stacked from the bottom, the possible via configurations are 1-3, 2-3 and through hole. The user must gather information about the PCB manufacturer's allowed methods of stacking and possible vias. For cheaper boards, only through holes are made and antipad (or clearance) is placed on layers which are supposed not to be contacted to vias. == Failure behavior == If well made, PCB vias will primarily fail due to differential expansion and contraction between the copper plating and the PCB in the out of plane direction (Z). This differential expansion and contraction will induce cyclic fatigue in the copper plating, eventually resulting in crack propagation and an electrical open circuit. Various design, material, and environmental parameters will influence the rate of this degradation.<ref>C. Hillman, Understanding plated through via failures, Global SMT & Packaging – November 2013, pp 26-28, https://www.dfrsolutions.com/hubfs/Resources/services/Understanding_Plated_Through_Via_Failures.pdf?t=1514473946162</ref><ref>C. Hillman, Reliable Plated Through Via Design and Fabrication, http://resources.dfrsolutions.com/White-Papers/Reliability/Reliable-Plated-Through-Via-Design-and-Fabrication1.pdf</ref> To ensure via robustness, [[IPC (electronics)\|IPC]] sponsored a round-robin exercise that developed a time to failure calculator.<ref name="Calculator"/> == Gallery == {{Gallery\|width=200\|lines=4 \|File:Durchkontaktierung IMGP3005.jpg\| Plated-through holes, in this section there are eight on a multilayer board (magnified) \|File:Lp3b.png\| Double layered plating in CAD. Vias makes [[Placement (EDA)\|EDA placement]] possible.<br/> {{fontcolor\|red\|Bottom layer – Red}}<br/> {{fontcolor\|blue\|Top layer – Blue}} \|File:dldklpcb.jpg\| Plating of plated-through holes:<br/>Above – Top layer<br/>Down – Bottom layer }} {{Gallery\|width=200 \|File:Bga und via IMGP4531 wp.jpg\| Cross-cut section of a multilayer via \|File:PCB Spectrum.jpg\| The small metallic circles are vias }} ==See also== {{Wikibooks\|Practical Electronics\|PCB Layout#Holes}} * [[Through-hole technology]] (THT) * [[Surface-mount technology]] (SMT) * [[Through-silicon via]] (TSV) * [[Via fence]] * [[Feedthrough]] ==References== {{notelist}} {{Reflist\|refs= <ref name="Calculator">{{cite web \|url=http://www.dfrsolutions.com/reliability-calculators/plated-through-hole-calculator \|title=Plated Through Hole (PTH) Fatigue calculator \|publisher=DfR Solutions \|access-date=2017-12-17}}</ref> <ref name="Castell">{{cite web \|title=Castellated Holes / Edge Plating PCB / Castellations \|publisher=Hi-Tech Corp. \|date=2011 \|url=http://www.hitech.com.mk/en/technology/castell \|url-status=dead \|archive-url=https://web.archive.org/web/20160526042501/http://www.hitech.com.mk/en/technology/castell \|archive-date=2016-05-26 \|access-date=2013-01-02 }}</ref> }} ==External links== *{{cite web \|title=Tips for PCB Vias Design \|publisher=Quick-teck \|type=Technical note \|id=EN-00417 \|date=2014 \|url=http://www.quick-teck.co.uk/TechArticleDoc/19895134801360697091.pdf \|access-date=2017-12-18 }} {{Authority control}} {{DEFAULTSORT:Via (Electronics)}} [[Category:Electronic design]] [[Category:Electronics manufacturing]] [[Category:Printed circuit board manufacturing]]'
New page wikitext, after the edit (`new_wikitext`)	'{{Short description\|Type of electrical connection}} {{More footnotes\|date=December 2017}} {{Use dmy dates\|\|date=February 2022\|cs1-dates=y}} {{Use list-defined references\|date=February 2022}} {{Anchor\|Tented via\|Covered annular ring\|Castellated hole\|DVIA\|Plugged via\|Stacked via\|Staggered via\|Filled via\|Capped via\|Via-in-pad\|Covered via\|Filled microvia\|Blind microvia}}<!-- parked anchors from redirects --> A '''via''' (Latin for ''path'' or ''way'') is an [[electrical connection]] between copper layers in a [[printed circuit board]]. Essentially a via is a small drilled hole that goes through two or more adjacent layers; the hole is plated with copper that forms electrical connection through the insulation that separates the copper layers. Vias are important for PCB manufacturing.<ref name="Epiccolo"/> This is because the vias are drilled with certain tolerances and may be fabricated off their designated locations, so some allowance for errors in drill position must be made prior to manufacturing or else the manufacturing yield can decrease due to non-conforming boards (according to some reference standard) or even due to failing boards. In addition, regular through hole vias are considered fragile structures as they are long and narrow; the manufacturer must ensure that the vias are plated properly throughout the barrel and this in turn causes several processing steps. =={{anchor\|Buried via\|Blind via\|Thermal via\|Through via\|Non-through via}} In printed circuit boards == [[File:Via Types.svg\|thumb\|Different types of vias:<br/> ('''1''') [[Through hole]].<br/> ('''2''') Blind via.<br/> ('''3''') Buried via.<br/>The gray and green layers are nonconducting, while the thin orange layers and red vias are conductive.]] [[File:ViaCurrentCapacity.png\|thumb\|PCB via current capacity chart showing 1 mil plating via current capacity & resistance versus diameter on a 1.6 mm PCB.]] In [[printed circuit board]] (PCB) design, a via consists of two pads in corresponding positions on different layers of the board, that are electrically connected by a hole through the board. The hole is made conductive by [[electroplating]], or is lined with a tube or a [[rivet]]. High-density multilayer PCBs may have [[microvia]]s: '''blind vias''' are exposed only on one side of the board, while '''buried vias''' connect internal layers without being exposed on either surface. '''Thermal vias''' carry heat away from power devices and are typically used in arrays of about a dozen.<ref name="EDN"/> A via consists of: # Barrel — conductive tube filling the drilled hole # Pad — connects each end of the barrel to the component, plane, or trace # Antipad — clearance hole between barrel and metal layer to which it is not connected A via, sometimes called PTV or plated-through-via, should not be confused with a plated through hole (PTH). Via is used as an interconnection between copper layers on a PCB while the PTH is generally made larger than vias and is used as a plated hole for acceptance of component leads - such as non-SMT resistors, capacitors, and DIP package IC. PTH can also be used as holes for mechanical connection while vias may not. Another usage of PTH is known as a '''castellated hole''' where the PTH is aligned at the edge of the board so that it is cut in half when the board is milled out of the panel - the main usage is for allowing one PCB to be soldered to another in a stack - thus acting both as a fastener and also as a connector.<ref name="Castell"/> Three major kinds of vias are shown in right figure. The basic steps of making a PCB are: making the substrate material and stacking it in layers; through-drilling of plating the vias; and copper trace patterning using photolithography and etching. With this standard procedure, possible via configurations are limited to through-holes.{{efn\|Through-holes per core. It is possible, though more expensive, to create blind or buried vias by using additional cores and lamination steps. It is also possible to backdrill and remove the plating from one side through to the desired layer, which leaves the physical hole as a through-hole, but creates the electrical equivalent of a blind via. If a PCB needs enough layers to justify blind and buried vias, it is probably also using small enough traces packed tightly enough to require (laser-drilled) microvias.}} Depth-controlled drilling techniques such as using lasers can allow for more varied via types. (Laser drills can also be used for smaller and more precisely positioned holes than mechanical drills produce.) PCB manufacturing typically starts with a so-called core, a basic double-sided PCB. Layers beyond the first two are stacked from this basic building block. If two more layers are consecutively stacked from bottom of core, you can have a 1-2 via, a 1-3 via and a [[through hole]]. Each type of via is made by drilling at each stacking stage. If one layer is stacked on top of the core and other is stacked from the bottom, the possible via configurations are 1-3, 2-3 and through hole. The user must gather information about the PCB manufacturer's allowed methods of stacking and possible vias. For cheaper boards, only through holes are made and antipad (or clearance) is placed on layers which are supposed not to be contacted to vias. == Failure behavior == If well made, PCB vias will primarily fail due to differential expansion and contraction between the copper plating and the PCB in the out of plane direction (Z). This differential expansion and contraction will induce cyclic fatigue in the copper plating, eventually resulting in crack propagation and an electrical open circuit. Various design, material, and environmental parameters will influence the rate of this degradation.<ref name="Hillman_2013"/><ref name="Hillman"/> To ensure via robustness, [[IPC (electronics)\|IPC]] sponsored a round-robin exercise that developed a time to failure calculator.<ref name="Calculator"/> == {{anchor\|In IC}}Vias in integrated circuits == {{Main\|Through-silicon via}} In [[integrated circuit]] (IC) design, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers. A via on an integrated circuit that passes completely through a [[silicon wafer]] or [[die (integrated circuit)\|die]] is called a [[through-chip via]] or [[through-silicon via]] (TSV). '''Through-glass vias''' ('''TGV''') have been studied by [[Corning Glass]] for semiconductor packaging, due to the reduced electrical loss of glass versus silicon packaging.<ref name="Corning_2019"/> A via connecting the lowest layer of metal to diffusion or poly<!--???--> is typically called a "contact". == Gallery == {{Gallery\|width=200\|lines=4 \|File:Durchkontaktierung IMGP3005.jpg\| Plated-through holes, in this section there are eight on a multilayer board (magnified) \|File:Lp3b.png\| Double layered plating in CAD. Vias makes [[Placement (EDA)\|EDA placement]] possible.<br/> {{fontcolor\|red\|Bottom layer – Red}}<br/> {{fontcolor\|blue\|Top layer – Blue}} \|File:dldklpcb.jpg\| Plating of plated-through holes:<br/>Above – Top layer<br/>Down – Bottom layer }} {{Gallery\|width=200 \|File:Bga und via IMGP4531 wp.jpg\| Cross-cut section of a multilayer via \|File:PCB Spectrum.jpg\| The small metallic circles are vias }} ==See also== {{Wikibooks\|Practical Electronics\|PCB Layout#Holes}} * [[Through-hole technology]] (THT) * [[Surface-mount technology]] (SMT) * [[Through-silicon via]] (TSV) * [[Via fence]] * [[Feedthrough]] ==Notes== {{notelist}} ==References== {{Reflist\|refs= <ref name="Calculator">{{cite web \|url=http://www.dfrsolutions.com/reliability-calculators/plated-through-hole-calculator \|title=Plated Through Hole (PTH) Fatigue calculator \|publisher=DfR Solutions \|access-date=2017-12-17}}</ref> <ref name="Castell">{{cite web \|title=Castellated Holes / Edge Plating PCB / Castellations \|publisher=Hi-Tech Corp. \|date=2011 \|url=http://www.hitech.com.mk/en/technology/castell \|url-status=dead \|archive-url=https://web.archive.org/web/20160526042501/http://www.hitech.com.mk/en/technology/castell \|archive-date=2016-05-26 \|access-date=2013-01-02}}</ref> <ref name="Epiccolo">{{Cite web \|title=PCB Vias: An In-Depth Guide \|url=https://www.epiccolo.com/articles/pcb-vias-guide \|website=ePiccolo Engineering}}</ref> <ref name="EDN">{{Cite news \|title=PCB design: A close look at facts and myths about thermal vias \|url=https://www.edn.com/pcb-design-a-close-look-at-facts-and-myths-about-thermal-vias/}}</ref> <ref name="Hillman_2013">C. Hillman, Understanding plated through via failures, Global SMT & Packaging – November 2013, pp 26-28, https://www.dfrsolutions.com/hubfs/Resources/services/Understanding_Plated_Through_Via_Failures.pdf?t=1514473946162</ref> <ref name="Hillman">C. Hillman, Reliable Plated Through Via Design and Fabrication, http://resources.dfrsolutions.com/White-Papers/Reliability/Reliable-Plated-Through-Via-Design-and-Fabrication1.pdf</ref> <ref name="Corning_2019">{{cite web \|url=https://www.corning.com/media/worldwide/cdt/documents/IMAPs_Corning_TGV_FINAL.pdf \|title=Progress and Application of Through Glass Via (TGV) Technology \|website=corning.com \|access-date=2019-08-08}}</ref> }} ==Further reading== * {{cite web \|title=Tips for PCB Vias Design \|publisher=Quick-teck \|type=Technical note \|id=EN-00417 \|date=2014 \|url=http://www.quick-teck.co.uk/TechArticleDoc/19895134801360697091.pdf \|access-date=2017-12-18}} * {{cite web \|title=Via Tenting - Overview of the variations \|at=Printed Circuit Boards > Layout > Design Tip > Tenting \|publisher=[[Würth Elektronik GmbH & Co. KG]] \|website=[[WE Online]] \|date=2014 \|url=http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/tenting/tenting_3.php \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218141422/http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/tenting/tenting_3.php \|archive-date=2017-12-18}} * {{cite web \|title=Via Plugging - Overview of the variations \|at=Printed Circuit Boards > Layout > Design Tip > Plugging \|publisher=[[Würth Elektronik GmbH & Co. KG]] \|website=[[WE Online]] \|date=2014 \|url=http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/plugging/plugging_1.php \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218141631/http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/plugging/plugging_1.php \|archive-date=2017-12-18}} * {{cite web \|title=Via Filling - Overview of the variations \|at=Printed Circuit Boards > Layout > Design Tip > Filling \|publisher=[[Würth Elektronik GmbH & Co. KG]] \|website=[[WE Online]] \|date=2013 \|url=http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/filling/filling_1.php \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218141821/http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/filling/filling_1.php \|archive-date=2017-12-18}} * {{cite web \|title=Microvia Filling \|at=Printed Circuit Boards > Layout > Design Tip > Microvia Filling \|publisher=[[Würth Elektronik GmbH & Co. KG]] \|website=[[WE Online]] \|date=2015 \|url=http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/microvia_filling/microvia_filling.php \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218141843/http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/microvia_filling/microvia_filling.php \|archive-date=2017-12-18}} * {{cite web \|author-first=Klaus \|author-last1=Dingler \|author-first2=Markus \|author-last2=Musewski \|title=Pluggen / Plugging \|language=de \|date=2009-03-18 \|publisher=Fachverband Elektronik-Design e.V. (FED) \|location=Berlin, Germany \|website=FED-Wiki \|url=http://wiki.fed.de/index.php/Pluggen_/_Plugging \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218135704/http://wiki.fed.de/index.php/Pluggen_/_Plugging \|archive-date=2017-12-18}} * {{cite web \|title=Via Optimization Techniques for High-Speed Channel Designs \|publisher=[[Altera Corporation]] \|date=May 2008 \|version=1.0 \|type=Application note \|id=AN-529-1.0 \|url=https://www.altera.com/en_US/pdfs/literature/an/an529.pdf \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218142832/https://www.altera.com/en_US/pdfs/literature/an/an529.pdf \|archive-date=2017-12-18}} * {{cite web \|title=Controlled Depth Drilling, or Back Drilling \|work=Online Documentation for Altium Products \|publisher=[[Altium]] \|author-first=Jun \|author-last=Chu \|date=2017-04-11 \|url=http://www.altium.com/documentation/17.0/display/ADES/((Controlled+Depth+Drilling,+or+Back+Drilling))_AD \|access-date=2017-12-18 \|url-status=live \|archive-url=https://archive.today/20171218143321/http://www.altium.com/documentation/17.0/display/ADES/((Controlled%20Depth%20Drilling,%20or%20Back%20Drilling))_AD \|archive-date=2017-12-18}} * {{cite web \|title=Removing Unused Pads and Adding Teardrops \|work=Online Documentation for Altium Products \|publisher=[[Altium]] \|author-first=Phil \|author-last=Loughhead \|date=2017-05-30 \|url=http://www.altium.com/documentation/17.1/display/ADES/((Removing+Unused+Pads+and+Adding+Teardrops))_AD \|access-date=2017-12-18 \|url-status=live \|archive-url=https://archive.today/20171218143719/http://www.altium.com/documentation/17.1/display/ADES/((Removing%20Unused%20Pads%20and%20Adding%20Teardrops))_AD \|archive-date=2017-12-18}} * {{cite book \|author-last1=Brooks \|author-first1=Douglas G. \|author-last2=Adam \|author-first2=Johannes \|title=PCB Trace and Via Temperatures: The Complete Analysis \|edition=2nd \|publisher=CreateSpace Independent Publishing Platform \|date=2017-02-09 \|isbn=978-1541213524}} ==External links== * [https://pcbtoolbox.net/pcb-tools/ Online Via Calculator] (Ampacity, Capacitance, Impedance, Power Dissipation Calculation). {{Authority control}} {{DEFAULTSORT:Via (Electronics)}} [[Category:Electronic design]] [[Category:Electronics manufacturing]] [[Category:Printed circuit board manufacturing]]'
Unified diff of changes made by edit (`edit_diff`)	'@@ -1,13 +1,16 @@ {{Short description\|Type of electrical connection}} {{More footnotes\|date=December 2017}} -{{For\|the via in integrated circuits\|Through-silicon via}} -{{Anchor\|Tented via\|Covered annular ring\|Castellated hole\|DVIA\|Plugged via\|Stacked via\|Staggered via\|Filled via\|Capped via\|Via-in-pad\|Covered via\|Filled microvia\|Blind microvia\|In IC}}<!-- parked anchors from redirects --> -A '''via''' (Latin for ''path'' or ''way'') is an [[electrical connection]] between copper layers in a [[printed circuit board]]. Essentially a small drilled hole that goes through two or more adjacent layers, the hole is plated with copper that forms electrical connection through the insulation that separates the copper layers. +{{Use dmy dates\|\|date=February 2022\|cs1-dates=y}} +{{Use list-defined references\|date=February 2022}} +{{Anchor\|Tented via\|Covered annular ring\|Castellated hole\|DVIA\|Plugged via\|Stacked via\|Staggered via\|Filled via\|Capped via\|Via-in-pad\|Covered via\|Filled microvia\|Blind microvia}}<!-- parked anchors from redirects --> +A '''via''' (Latin for ''path'' or ''way'') is an [[electrical connection]] between copper layers in a [[printed circuit board]]. Essentially a via is a small drilled hole that goes through two or more adjacent layers; the hole is plated with copper that forms electrical connection through the insulation that separates the copper layers. + +Vias are important for PCB manufacturing.<ref name="Epiccolo"/> This is because the vias are drilled with certain tolerances and may be fabricated off their designated locations, so some allowance for errors in drill position must be made prior to manufacturing or else the manufacturing yield can decrease due to non-conforming boards (according to some reference standard) or even due to failing boards. In addition, regular through hole vias are considered fragile structures as they are long and narrow; the manufacturer must ensure that the vias are plated properly throughout the barrel and this in turn causes several processing steps. =={{anchor\|Buried via\|Blind via\|Thermal via\|Through via\|Non-through via}} In printed circuit boards == [[File:Via Types.svg\|thumb\|Different types of vias:<br/> ('''1''') [[Through hole]].<br/> ('''2''') Blind via.<br/> ('''3''') Buried via.<br/>The gray and green layers are nonconducting, while the thin orange layers and red vias are conductive.]] -[[File:ViaCurrentCapacity.png\|thumb\|PCB Via current capacity chart showing 1mil Plating Via Current Capacity & Resistance vs Diameter on a 1.6mm PCB]] +[[File:ViaCurrentCapacity.png\|thumb\|PCB via current capacity chart showing 1 mil plating via current capacity & resistance versus diameter on a 1.6 mm PCB.]] -In [[printed circuit board]] (PCB) design, a via consists of two pads in corresponding positions on different layers of the board, that are electrically connected by a hole through the board. The hole is made conductive by [[electroplating]], or is lined with a tube or a [[rivet]]. High-density multilayer PCBs may have [[microvia]]s: '''blind vias''' are exposed only on one side of the board, while '''buried vias''' connect internal layers without being exposed on either surface. '''Thermal vias''' carry heat away from power devices and are typically used in arrays of about a dozen.<ref>{{Cite news\|title=PCB design: A close look at facts and myths about thermal vias\|url=https://www.edn.com/pcb-design-a-close-look-at-facts-and-myths-about-thermal-vias/}}</ref> +In [[printed circuit board]] (PCB) design, a via consists of two pads in corresponding positions on different layers of the board, that are electrically connected by a hole through the board. The hole is made conductive by [[electroplating]], or is lined with a tube or a [[rivet]]. High-density multilayer PCBs may have [[microvia]]s: '''blind vias''' are exposed only on one side of the board, while '''buried vias''' connect internal layers without being exposed on either surface. '''Thermal vias''' carry heat away from power devices and are typically used in arrays of about a dozen.<ref name="EDN"/> A via consists of: @@ -18,8 +21,12 @@ A via, sometimes called PTV or plated-through-via, should not be confused with a plated through hole (PTH). Via is used as an interconnection between copper layers on a PCB while the PTH is generally made larger than vias and is used as a plated hole for acceptance of component leads - such as non-SMT resistors, capacitors, and DIP package IC. PTH can also be used as holes for mechanical connection while vias may not. Another usage of PTH is known as a '''castellated hole''' where the PTH is aligned at the edge of the board so that it is cut in half when the board is milled out of the panel - the main usage is for allowing one PCB to be soldered to another in a stack - thus acting both as a fastener and also as a connector.<ref name="Castell"/> -Three major kinds of vias are shown in right figure. The basic steps of making a PCB are: making the substrate material and stacking it in layers; through-drilling of plating the vias; and copper trace patterning using photolithography and etching. With this standard procedure, possible via configurations are limited to through-holes.{{efn\|Well, through-holes per core. It is possible, though more expensive, to create blind or buried vias by using additional cores and lamination steps. It is also possible to backdrill and remove the plating from one side through to the desired layer, which leaves the physical hole as a through-hole, but creates the electrical equivalent of a blind via. That said, if a PCB needs enough layers to justify blind and buried vias, it is probably also using small enough traces packed tightly enough to require (laser-drilled) microvias anyhow.}} Depth-controlled drilling techniques such as using lasers can allow for more varied via types. (Laser drills can also be used for smaller and more precisely positioned holes than mechanical drills produce.) PCB manufacturing typically starts with a so-called core, a basic double-sided PCB. Layers beyond the first two are stacked from this basic building block. If two more layers are consecutively stacked from bottom of core, you can have a 1-2 via, a 1-3 via and a [[through hole]]. Each type of via is made by drilling at each stacking stage. If one layer is stacked on top of the core and other is stacked from the bottom, the possible via configurations are 1-3, 2-3 and through hole. The user must gather information about the PCB manufacturer's allowed methods of stacking and possible vias. For cheaper boards, only through holes are made and antipad (or clearance) is placed on layers which are supposed not to be contacted to vias. +Three major kinds of vias are shown in right figure. The basic steps of making a PCB are: making the substrate material and stacking it in layers; through-drilling of plating the vias; and copper trace patterning using photolithography and etching. With this standard procedure, possible via configurations are limited to through-holes.{{efn\|Through-holes per core. It is possible, though more expensive, to create blind or buried vias by using additional cores and lamination steps. It is also possible to backdrill and remove the plating from one side through to the desired layer, which leaves the physical hole as a through-hole, but creates the electrical equivalent of a blind via. If a PCB needs enough layers to justify blind and buried vias, it is probably also using small enough traces packed tightly enough to require (laser-drilled) microvias.}} Depth-controlled drilling techniques such as using lasers can allow for more varied via types. (Laser drills can also be used for smaller and more precisely positioned holes than mechanical drills produce.) PCB manufacturing typically starts with a so-called core, a basic double-sided PCB. Layers beyond the first two are stacked from this basic building block. If two more layers are consecutively stacked from bottom of core, you can have a 1-2 via, a 1-3 via and a [[through hole]]. Each type of via is made by drilling at each stacking stage. If one layer is stacked on top of the core and other is stacked from the bottom, the possible via configurations are 1-3, 2-3 and through hole. The user must gather information about the PCB manufacturer's allowed methods of stacking and possible vias. For cheaper boards, only through holes are made and antipad (or clearance) is placed on layers which are supposed not to be contacted to vias. == Failure behavior == -If well made, PCB vias will primarily fail due to differential expansion and contraction between the copper plating and the PCB in the out of plane direction (Z). This differential expansion and contraction will induce cyclic fatigue in the copper plating, eventually resulting in crack propagation and an electrical open circuit. Various design, material, and environmental parameters will influence the rate of this degradation.<ref>C. Hillman, Understanding plated through via failures, Global SMT & Packaging – November 2013, pp 26-28, https://www.dfrsolutions.com/hubfs/Resources/services/Understanding_Plated_Through_Via_Failures.pdf?t=1514473946162</ref><ref>C. Hillman, Reliable Plated Through Via Design and Fabrication, http://resources.dfrsolutions.com/White-Papers/Reliability/Reliable-Plated-Through-Via-Design-and-Fabrication1.pdf</ref> To ensure via robustness, [[IPC (electronics)\|IPC]] sponsored a round-robin exercise that developed a time to failure calculator.<ref name="Calculator"/> +If well made, PCB vias will primarily fail due to differential expansion and contraction between the copper plating and the PCB in the out of plane direction (Z). This differential expansion and contraction will induce cyclic fatigue in the copper plating, eventually resulting in crack propagation and an electrical open circuit. Various design, material, and environmental parameters will influence the rate of this degradation.<ref name="Hillman_2013"/><ref name="Hillman"/> To ensure via robustness, [[IPC (electronics)\|IPC]] sponsored a round-robin exercise that developed a time to failure calculator.<ref name="Calculator"/> + +== {{anchor\|In IC}}Vias in integrated circuits == +{{Main\|Through-silicon via}} +In [[integrated circuit]] (IC) design, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers. A via on an integrated circuit that passes completely through a [[silicon wafer]] or [[die (integrated circuit)\|die]] is called a [[through-chip via]] or [[through-silicon via]] (TSV). '''Through-glass vias''' ('''TGV''') have been studied by [[Corning Glass]] for semiconductor packaging, due to the reduced electrical loss of glass versus silicon packaging.<ref name="Corning_2019"/> A via connecting the lowest layer of metal to diffusion or poly<!--???--> is typically called a "contact". == Gallery == @@ -42,14 +49,32 @@ * [[Feedthrough]] -==References== +==Notes== {{notelist}} +==References== {{Reflist\|refs= <ref name="Calculator">{{cite web \|url=http://www.dfrsolutions.com/reliability-calculators/plated-through-hole-calculator \|title=Plated Through Hole (PTH) Fatigue calculator \|publisher=DfR Solutions \|access-date=2017-12-17}}</ref> -<ref name="Castell">{{cite web \|title=Castellated Holes / Edge Plating PCB / Castellations \|publisher=Hi-Tech Corp. \|date=2011 \|url=http://www.hitech.com.mk/en/technology/castell \|url-status=dead \|archive-url=https://web.archive.org/web/20160526042501/http://www.hitech.com.mk/en/technology/castell \|archive-date=2016-05-26 \|access-date=2013-01-02 }}</ref> +<ref name="Castell">{{cite web \|title=Castellated Holes / Edge Plating PCB / Castellations \|publisher=Hi-Tech Corp. \|date=2011 \|url=http://www.hitech.com.mk/en/technology/castell \|url-status=dead \|archive-url=https://web.archive.org/web/20160526042501/http://www.hitech.com.mk/en/technology/castell \|archive-date=2016-05-26 \|access-date=2013-01-02}}</ref> +<ref name="Epiccolo">{{Cite web \|title=PCB Vias: An In-Depth Guide \|url=https://www.epiccolo.com/articles/pcb-vias-guide \|website=ePiccolo Engineering}}</ref> +<ref name="EDN">{{Cite news \|title=PCB design: A close look at facts and myths about thermal vias \|url=https://www.edn.com/pcb-design-a-close-look-at-facts-and-myths-about-thermal-vias/}}</ref> +<ref name="Hillman_2013">C. Hillman, Understanding plated through via failures, Global SMT & Packaging – November 2013, pp 26-28, https://www.dfrsolutions.com/hubfs/Resources/services/Understanding_Plated_Through_Via_Failures.pdf?t=1514473946162</ref> +<ref name="Hillman">C. Hillman, Reliable Plated Through Via Design and Fabrication, http://resources.dfrsolutions.com/White-Papers/Reliability/Reliable-Plated-Through-Via-Design-and-Fabrication1.pdf</ref> +<ref name="Corning_2019">{{cite web \|url=https://www.corning.com/media/worldwide/cdt/documents/IMAPs_Corning_TGV_FINAL.pdf \|title=Progress and Application of Through Glass Via (TGV) Technology \|website=corning.com \|access-date=2019-08-08}}</ref> }} + +==Further reading== +* {{cite web \|title=Tips for PCB Vias Design \|publisher=Quick-teck \|type=Technical note \|id=EN-00417 \|date=2014 \|url=http://www.quick-teck.co.uk/TechArticleDoc/19895134801360697091.pdf \|access-date=2017-12-18}} +* {{cite web \|title=Via Tenting - Overview of the variations \|at=Printed Circuit Boards > Layout > Design Tip > Tenting \|publisher=[[Würth Elektronik GmbH & Co. KG]] \|website=[[WE Online]] \|date=2014 \|url=http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/tenting/tenting_3.php \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218141422/http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/tenting/tenting_3.php \|archive-date=2017-12-18}} +* {{cite web \|title=Via Plugging - Overview of the variations \|at=Printed Circuit Boards > Layout > Design Tip > Plugging \|publisher=[[Würth Elektronik GmbH & Co. KG]] \|website=[[WE Online]] \|date=2014 \|url=http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/plugging/plugging_1.php \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218141631/http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/plugging/plugging_1.php \|archive-date=2017-12-18}} +* {{cite web \|title=Via Filling - Overview of the variations \|at=Printed Circuit Boards > Layout > Design Tip > Filling \|publisher=[[Würth Elektronik GmbH & Co. KG]] \|website=[[WE Online]] \|date=2013 \|url=http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/filling/filling_1.php \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218141821/http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/filling/filling_1.php \|archive-date=2017-12-18}} +* {{cite web \|title=Microvia Filling \|at=Printed Circuit Boards > Layout > Design Tip > Microvia Filling \|publisher=[[Würth Elektronik GmbH & Co. KG]] \|website=[[WE Online]] \|date=2015 \|url=http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/microvia_filling/microvia_filling.php \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218141843/http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/microvia_filling/microvia_filling.php \|archive-date=2017-12-18}} +* {{cite web \|author-first=Klaus \|author-last1=Dingler \|author-first2=Markus \|author-last2=Musewski \|title=Pluggen / Plugging \|language=de \|date=2009-03-18 \|publisher=Fachverband Elektronik-Design e.V. (FED) \|location=Berlin, Germany \|website=FED-Wiki \|url=http://wiki.fed.de/index.php/Pluggen_/_Plugging \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218135704/http://wiki.fed.de/index.php/Pluggen_/_Plugging \|archive-date=2017-12-18}} +* {{cite web \|title=Via Optimization Techniques for High-Speed Channel Designs \|publisher=[[Altera Corporation]] \|date=May 2008 \|version=1.0 \|type=Application note \|id=AN-529-1.0 \|url=https://www.altera.com/en_US/pdfs/literature/an/an529.pdf \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218142832/https://www.altera.com/en_US/pdfs/literature/an/an529.pdf \|archive-date=2017-12-18}} +* {{cite web \|title=Controlled Depth Drilling, or Back Drilling \|work=Online Documentation for Altium Products \|publisher=[[Altium]] \|author-first=Jun \|author-last=Chu \|date=2017-04-11 \|url=http://www.altium.com/documentation/17.0/display/ADES/((Controlled+Depth+Drilling,+or+Back+Drilling))_AD \|access-date=2017-12-18 \|url-status=live \|archive-url=https://archive.today/20171218143321/http://www.altium.com/documentation/17.0/display/ADES/((Controlled%20Depth%20Drilling,%20or%20Back%20Drilling))_AD \|archive-date=2017-12-18}} +* {{cite web \|title=Removing Unused Pads and Adding Teardrops \|work=Online Documentation for Altium Products \|publisher=[[Altium]] \|author-first=Phil \|author-last=Loughhead \|date=2017-05-30 \|url=http://www.altium.com/documentation/17.1/display/ADES/((Removing+Unused+Pads+and+Adding+Teardrops))_AD \|access-date=2017-12-18 \|url-status=live \|archive-url=https://archive.today/20171218143719/http://www.altium.com/documentation/17.1/display/ADES/((Removing%20Unused%20Pads%20and%20Adding%20Teardrops))_AD \|archive-date=2017-12-18}} +* {{cite book \|author-last1=Brooks \|author-first1=Douglas G. \|author-last2=Adam \|author-first2=Johannes \|title=PCB Trace and Via Temperatures: The Complete Analysis \|edition=2nd \|publisher=CreateSpace Independent Publishing Platform \|date=2017-02-09 \|isbn=978-1541213524}} ==External links== -{{cite web \|title=Tips for PCB Vias Design \|publisher=Quick-teck \|type=Technical note \|id=EN-00417 \|date=2014 \|url=http://www.quick-teck.co.uk/TechArticleDoc/19895134801360697091.pdf \|access-date=2017-12-18 }} + [https://pcbtoolbox.net/pcb-tools/ Online Via Calculator] (Ampacity, Capacitance, Impedance, Power Dissipation Calculation). {{Authority control}} '
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Lines added in edit (`added_lines`)	[ 0 => '{{Use dmy dates\|\|date=February 2022\|cs1-dates=y}}', 1 => '{{Use list-defined references\|date=February 2022}}', 2 => '{{Anchor\|Tented via\|Covered annular ring\|Castellated hole\|DVIA\|Plugged via\|Stacked via\|Staggered via\|Filled via\|Capped via\|Via-in-pad\|Covered via\|Filled microvia\|Blind microvia}}<!-- parked anchors from redirects -->', 3 => 'A '''via''' (Latin for ''path'' or ''way'') is an [[electrical connection]] between copper layers in a [[printed circuit board]]. Essentially a via is a small drilled hole that goes through two or more adjacent layers; the hole is plated with copper that forms electrical connection through the insulation that separates the copper layers.', 4 => '', 5 => 'Vias are important for PCB manufacturing.<ref name="Epiccolo"/> This is because the vias are drilled with certain tolerances and may be fabricated off their designated locations, so some allowance for errors in drill position must be made prior to manufacturing or else the manufacturing yield can decrease due to non-conforming boards (according to some reference standard) or even due to failing boards. In addition, regular through hole vias are considered fragile structures as they are long and narrow; the manufacturer must ensure that the vias are plated properly throughout the barrel and this in turn causes several processing steps.', 6 => '[[File:ViaCurrentCapacity.png\|thumb\|PCB via current capacity chart showing 1 mil plating via current capacity & resistance versus diameter on a 1.6 mm PCB.]]', 7 => 'In [[printed circuit board]] (PCB) design, a via consists of two pads in corresponding positions on different layers of the board, that are electrically connected by a hole through the board. The hole is made conductive by [[electroplating]], or is lined with a tube or a [[rivet]]. High-density multilayer PCBs may have [[microvia]]s: '''blind vias''' are exposed only on one side of the board, while '''buried vias''' connect internal layers without being exposed on either surface. '''Thermal vias''' carry heat away from power devices and are typically used in arrays of about a dozen.<ref name="EDN"/>', 8 => 'Three major kinds of vias are shown in right figure. The basic steps of making a PCB are: making the substrate material and stacking it in layers; through-drilling of plating the vias; and copper trace patterning using photolithography and etching. With this standard procedure, possible via configurations are limited to through-holes.{{efn\|Through-holes per core. It is possible, though more expensive, to create blind or buried vias by using additional cores and lamination steps. It is also possible to backdrill and remove the plating from one side through to the desired layer, which leaves the physical hole as a through-hole, but creates the electrical equivalent of a blind via. If a PCB needs enough layers to justify blind and buried vias, it is probably also using small enough traces packed tightly enough to require (laser-drilled) microvias.}} Depth-controlled drilling techniques such as using lasers can allow for more varied via types. (Laser drills can also be used for smaller and more precisely positioned holes than mechanical drills produce.) PCB manufacturing typically starts with a so-called core, a basic double-sided PCB. Layers beyond the first two are stacked from this basic building block. If two more layers are consecutively stacked from bottom of core, you can have a 1-2 via, a 1-3 via and a [[through hole]]. Each type of via is made by drilling at each stacking stage. If one layer is stacked on top of the core and other is stacked from the bottom, the possible via configurations are 1-3, 2-3 and through hole. The user must gather information about the PCB manufacturer's allowed methods of stacking and possible vias. For cheaper boards, only through holes are made and antipad (or clearance) is placed on layers which are supposed not to be contacted to vias.', 9 => 'If well made, PCB vias will primarily fail due to differential expansion and contraction between the copper plating and the PCB in the out of plane direction (Z). This differential expansion and contraction will induce cyclic fatigue in the copper plating, eventually resulting in crack propagation and an electrical open circuit. Various design, material, and environmental parameters will influence the rate of this degradation.<ref name="Hillman_2013"/><ref name="Hillman"/> To ensure via robustness, [[IPC (electronics)\|IPC]] sponsored a round-robin exercise that developed a time to failure calculator.<ref name="Calculator"/>', 10 => '', 11 => '== {{anchor\|In IC}}Vias in integrated circuits ==', 12 => '{{Main\|Through-silicon via}}', 13 => 'In [[integrated circuit]] (IC) design, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers. A via on an integrated circuit that passes completely through a [[silicon wafer]] or [[die (integrated circuit)\|die]] is called a [[through-chip via]] or [[through-silicon via]] (TSV). '''Through-glass vias''' ('''TGV''') have been studied by [[Corning Glass]] for semiconductor packaging, due to the reduced electrical loss of glass versus silicon packaging.<ref name="Corning_2019"/> A via connecting the lowest layer of metal to diffusion or poly<!--???--> is typically called a "contact".', 14 => '==Notes==', 15 => '==References==', 16 => '<ref name="Castell">{{cite web \|title=Castellated Holes / Edge Plating PCB / Castellations \|publisher=Hi-Tech Corp. \|date=2011 \|url=http://www.hitech.com.mk/en/technology/castell \|url-status=dead \|archive-url=https://web.archive.org/web/20160526042501/http://www.hitech.com.mk/en/technology/castell \|archive-date=2016-05-26 \|access-date=2013-01-02}}</ref>', 17 => '<ref name="Epiccolo">{{Cite web \|title=PCB Vias: An In-Depth Guide \|url=https://www.epiccolo.com/articles/pcb-vias-guide \|website=ePiccolo Engineering}}</ref>', 18 => '<ref name="EDN">{{Cite news \|title=PCB design: A close look at facts and myths about thermal vias \|url=https://www.edn.com/pcb-design-a-close-look-at-facts-and-myths-about-thermal-vias/}}</ref>', 19 => '<ref name="Hillman_2013">C. Hillman, Understanding plated through via failures, Global SMT & Packaging – November 2013, pp 26-28, https://www.dfrsolutions.com/hubfs/Resources/services/Understanding_Plated_Through_Via_Failures.pdf?t=1514473946162</ref>', 20 => '<ref name="Hillman">C. Hillman, Reliable Plated Through Via Design and Fabrication, http://resources.dfrsolutions.com/White-Papers/Reliability/Reliable-Plated-Through-Via-Design-and-Fabrication1.pdf</ref>', 21 => '<ref name="Corning_2019">{{cite web \|url=https://www.corning.com/media/worldwide/cdt/documents/IMAPs_Corning_TGV_FINAL.pdf \|title=Progress and Application of Through Glass Via (TGV) Technology \|website=corning.com \|access-date=2019-08-08}}</ref>', 22 => '', 23 => '==Further reading==', 24 => '* {{cite web \|title=Tips for PCB Vias Design \|publisher=Quick-teck \|type=Technical note \|id=EN-00417 \|date=2014 \|url=http://www.quick-teck.co.uk/TechArticleDoc/19895134801360697091.pdf \|access-date=2017-12-18}}', 25 => '* {{cite web \|title=Via Tenting - Overview of the variations \|at=Printed Circuit Boards > Layout > Design Tip > Tenting \|publisher=[[Würth Elektronik GmbH & Co. KG]] \|website=[[WE Online]] \|date=2014 \|url=http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/tenting/tenting_3.php \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218141422/http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/tenting/tenting_3.php \|archive-date=2017-12-18}} ', 26 => '* {{cite web \|title=Via Plugging - Overview of the variations \|at=Printed Circuit Boards > Layout > Design Tip > Plugging \|publisher=[[Würth Elektronik GmbH & Co. KG]] \|website=[[WE Online]] \|date=2014 \|url=http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/plugging/plugging_1.php \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218141631/http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/plugging/plugging_1.php \|archive-date=2017-12-18}} ', 27 => '* {{cite web \|title=Via Filling - Overview of the variations \|at=Printed Circuit Boards > Layout > Design Tip > Filling \|publisher=[[Würth Elektronik GmbH & Co. KG]] \|website=[[WE Online]] \|date=2013 \|url=http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/filling/filling_1.php \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218141821/http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/filling/filling_1.php \|archive-date=2017-12-18}} ', 28 => '* {{cite web \|title=Microvia Filling \|at=Printed Circuit Boards > Layout > Design Tip > Microvia Filling \|publisher=[[Würth Elektronik GmbH & Co. KG]] \|website=[[WE Online]] \|date=2015 \|url=http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/microvia_filling/microvia_filling.php \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218141843/http://www.we-online.com/web/en/leiterplatten/layout/design_tipp/microvia_filling/microvia_filling.php \|archive-date=2017-12-18}} ', 29 => '* {{cite web \|author-first=Klaus \|author-last1=Dingler \|author-first2=Markus \|author-last2=Musewski \|title=Pluggen / Plugging \|language=de \|date=2009-03-18 \|publisher=Fachverband Elektronik-Design e.V. (FED) \|location=Berlin, Germany \|website=FED-Wiki \|url=http://wiki.fed.de/index.php/Pluggen_/_Plugging \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218135704/http://wiki.fed.de/index.php/Pluggen_/_Plugging \|archive-date=2017-12-18}} ', 30 => '* {{cite web \|title=Via Optimization Techniques for High-Speed Channel Designs \|publisher=[[Altera Corporation]] \|date=May 2008 \|version=1.0 \|type=Application note \|id=AN-529-1.0 \|url=https://www.altera.com/en_US/pdfs/literature/an/an529.pdf \|access-date=2017-12-18 \|url-status=live \|archive-url=https://web.archive.org/web/20171218142832/https://www.altera.com/en_US/pdfs/literature/an/an529.pdf \|archive-date=2017-12-18}} ', 31 => '* {{cite web \|title=Controlled Depth Drilling, or Back Drilling \|work=Online Documentation for Altium Products \|publisher=[[Altium]] \|author-first=Jun \|author-last=Chu \|date=2017-04-11 \|url=http://www.altium.com/documentation/17.0/display/ADES/((Controlled+Depth+Drilling,+or+Back+Drilling))_AD \|access-date=2017-12-18 \|url-status=live \|archive-url=https://archive.today/20171218143321/http://www.altium.com/documentation/17.0/display/ADES/((Controlled%20Depth%20Drilling,%20or%20Back%20Drilling))_AD \|archive-date=2017-12-18}} ', 32 => '* {{cite web \|title=Removing Unused Pads and Adding Teardrops \|work=Online Documentation for Altium Products \|publisher=[[Altium]] \|author-first=Phil \|author-last=Loughhead \|date=2017-05-30 \|url=http://www.altium.com/documentation/17.1/display/ADES/((Removing+Unused+Pads+and+Adding+Teardrops))_AD \|access-date=2017-12-18 \|url-status=live \|archive-url=https://archive.today/20171218143719/http://www.altium.com/documentation/17.1/display/ADES/((Removing%20Unused%20Pads%20and%20Adding%20Teardrops))_AD \|archive-date=2017-12-18}} ', 33 => '* {{cite book \|author-last1=Brooks \|author-first1=Douglas G. \|author-last2=Adam \|author-first2=Johannes \|title=PCB Trace and Via Temperatures: The Complete Analysis \|edition=2nd \|publisher=CreateSpace Independent Publishing Platform \|date=2017-02-09 \|isbn=978-1541213524}}', 34 => '* [https://pcbtoolbox.net/pcb-tools/ Online Via Calculator] (Ampacity, Capacitance, Impedance, Power Dissipation Calculation).' ]
Lines removed in edit (`removed_lines`)	[ 0 => '{{For\|the via in integrated circuits\|Through-silicon via}}', 1 => '{{Anchor\|Tented via\|Covered annular ring\|Castellated hole\|DVIA\|Plugged via\|Stacked via\|Staggered via\|Filled via\|Capped via\|Via-in-pad\|Covered via\|Filled microvia\|Blind microvia\|In IC}}<!-- parked anchors from redirects -->', 2 => 'A '''via''' (Latin for ''path'' or ''way'') is an [[electrical connection]] between copper layers in a [[printed circuit board]]. Essentially a small drilled hole that goes through two or more adjacent layers, the hole is plated with copper that forms electrical connection through the insulation that separates the copper layers.', 3 => '[[File:ViaCurrentCapacity.png\|thumb\|PCB Via current capacity chart showing 1mil Plating Via Current Capacity & Resistance vs Diameter on a 1.6mm PCB]]', 4 => 'In [[printed circuit board]] (PCB) design, a via consists of two pads in corresponding positions on different layers of the board, that are electrically connected by a hole through the board. The hole is made conductive by [[electroplating]], or is lined with a tube or a [[rivet]]. High-density multilayer PCBs may have [[microvia]]s: '''blind vias''' are exposed only on one side of the board, while '''buried vias''' connect internal layers without being exposed on either surface. '''Thermal vias''' carry heat away from power devices and are typically used in arrays of about a dozen.<ref>{{Cite news\|title=PCB design: A close look at facts and myths about thermal vias\|url=https://www.edn.com/pcb-design-a-close-look-at-facts-and-myths-about-thermal-vias/}}</ref>', 5 => 'Three major kinds of vias are shown in right figure. The basic steps of making a PCB are: making the substrate material and stacking it in layers; through-drilling of plating the vias; and copper trace patterning using photolithography and etching. With this standard procedure, possible via configurations are limited to through-holes.{{efn\|Well, through-holes per core. It is possible, though more expensive, to create blind or buried vias by using additional cores and lamination steps. It is also possible to backdrill and remove the plating from one side through to the desired layer, which leaves the physical hole as a through-hole, but creates the electrical equivalent of a blind via. That said, if a PCB needs enough layers to justify blind and buried vias, it is probably also using small enough traces packed tightly enough to require (laser-drilled) microvias anyhow.}} Depth-controlled drilling techniques such as using lasers can allow for more varied via types. (Laser drills can also be used for smaller and more precisely positioned holes than mechanical drills produce.) PCB manufacturing typically starts with a so-called core, a basic double-sided PCB. Layers beyond the first two are stacked from this basic building block. If two more layers are consecutively stacked from bottom of core, you can have a 1-2 via, a 1-3 via and a [[through hole]]. Each type of via is made by drilling at each stacking stage. If one layer is stacked on top of the core and other is stacked from the bottom, the possible via configurations are 1-3, 2-3 and through hole. The user must gather information about the PCB manufacturer's allowed methods of stacking and possible vias. For cheaper boards, only through holes are made and antipad (or clearance) is placed on layers which are supposed not to be contacted to vias.', 6 => 'If well made, PCB vias will primarily fail due to differential expansion and contraction between the copper plating and the PCB in the out of plane direction (Z). This differential expansion and contraction will induce cyclic fatigue in the copper plating, eventually resulting in crack propagation and an electrical open circuit. Various design, material, and environmental parameters will influence the rate of this degradation.<ref>C. Hillman, Understanding plated through via failures, Global SMT & Packaging – November 2013, pp 26-28, https://www.dfrsolutions.com/hubfs/Resources/services/Understanding_Plated_Through_Via_Failures.pdf?t=1514473946162</ref><ref>C. Hillman, Reliable Plated Through Via Design and Fabrication, http://resources.dfrsolutions.com/White-Papers/Reliability/Reliable-Plated-Through-Via-Design-and-Fabrication1.pdf</ref> To ensure via robustness, [[IPC (electronics)\|IPC]] sponsored a round-robin exercise that developed a time to failure calculator.<ref name="Calculator"/>', 7 => '==References==', 8 => '<ref name="Castell">{{cite web \|title=Castellated Holes / Edge Plating PCB / Castellations \|publisher=Hi-Tech Corp. \|date=2011 \|url=http://www.hitech.com.mk/en/technology/castell \|url-status=dead \|archive-url=https://web.archive.org/web/20160526042501/http://www.hitech.com.mk/en/technology/castell \|archive-date=2016-05-26 \|access-date=2013-01-02 }}</ref>', 9 => '*{{cite web \|title=Tips for PCB Vias Design \|publisher=Quick-teck \|type=Technical note \|id=EN-00417 \|date=2014 \|url=http://www.quick-teck.co.uk/TechArticleDoc/19895134801360697091.pdf \|access-date=2017-12-18 }}' ]
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Links in the page, before the edit (`old_links`)	[ 0 => 'http://resources.dfrsolutions.com/White-Papers/Reliability/Reliable-Plated-Through-Via-Design-and-Fabrication1.pdf', 1 => 'http://www.dfrsolutions.com/reliability-calculators/plated-through-hole-calculator', 2 => 'http://www.hitech.com.mk/en/technology/castell', 3 => 'http://www.quick-teck.co.uk/TechArticleDoc/19895134801360697091.pdf', 4 => 'https://d-nb.info/gnd/4150891-9', 5 => 'https://web.archive.org/web/20160526042501/http://www.hitech.com.mk/en/technology/castell', 6 => 'https://www.dfrsolutions.com/hubfs/Resources/services/Understanding_Plated_Through_Via_Failures.pdf?t=1514473946162', 7 => 'https://www.edn.com/pcb-design-a-close-look-at-facts-and-myths-about-thermal-vias/', 8 => 'https://www.wikidata.org/wiki/Q374105#identifiers' ]
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