Examine individual changes

'{{Short description|None}} {{Multiple issues|{{Citation style|date=October 2018|details=Some footnotes, some raw references (as below)}} {{Overly detailed|date=May 2023}} {{More citations needed|date=May 2023}}}} [[File:2 Duo T7500 Processor.jpg|thumb|Front side of an Intel Core 2 Duo T7500 Processor]] The [[Core 2]] brand refers to [[Intel]]'s [[x86]] and [[x86-64]] [[processor (computing)|processor]]s with the [[Intel Core (microarchitecture)|Core microarchitecture]] made for the consumer and business markets (except servers) above [[Pentium]]. The [[Core 2 Solo]] branch covered single-core CPUs for notebook computers, [[Core 2 Duo]] – dual-core CPUs for desktop and notebook computers, [[Core 2 Quad]] – quad-core CPUs for desktop and notebook computers, and [[Core 2 Extreme]] – dual-core and quad-core CPUs for desktop and notebook computers. ==Desktop processors== ===Dual-Core Desktop processors=== ====Core 2 Duo==== =====[[Conroe (microprocessor)#Allendale|"Allendale"]] (65 nm, 800 MT/s) {{anchor|"Allendale" (65 nm)}} ===== *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2)''{{ref|NoTXT|a}} * [[Die (integrated circuit)|Die]] size: 111&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 65nm process|L2]]{{ref|MoreAgressiveHaltStateL2|b}}, [[Intel Core (microarchitecture)#Steppings using 65nm process|M0]]{{ref|MoreAgressiveHaltStateM0|c}}, [[Intel Core (microarchitecture)#Steppings using 65nm process|G0]]{{ref|MoreAgressiveHaltStateG0|d}} {{cpulist|core|head}}<!-- edit Template:cpulist to modify the style of this table --> {{cpulist|core|conroe|model=Core 2 Duo E4300|mult=9|l2=2|fsb=800 |vmin=0.85 |vmax=1.5|date=January 2007|price=$163|links=1 |sspec1=SL9TB|step1=L2|part1=HH80557PG0332M |sspec2=SLA99|step2=M0|part2=BX80557E4300 |sspec3=SLA5G|step3=}} {{cpulist|core|conroe|model=Core 2 Duo E4400 |mult=10|l2=2|fsb=800 |vmin=0.85 |vmax=1.5|date=April 2007|price=$133 |sspec1=SLA3F|step1=L2|part1=HH80557PG0412M |sspec2=SLA98|step2=M0|part2=BX80557E4400 |sspec3=SLA5F|step3=}} {{cpulist|core|conroe|model=Core 2 Duo E4500 |mult=11|l2=2|fsb=800 |vmin=0.85 |vmax=1.5|date=July 2007|price=$133 |sspec1=SLA95|step1=M0|part1=HH80557PG0492M |part2=BX80557E4500}} {{cpulist|core|conroe|model=Core 2 Duo E4600 |mult=12|l2=2|fsb=800 |vmin=1.162 |vmax=1.312|date=October 2007|price=$133 |sspec1=SLA94|step1=M0|part1=HH80557PG0562M |part2=BX80557E4600}} {{cpulist|core|conroe|model=Core 2 Duo E4700 |mult=13|l2=2|fsb=800 |vmin=1.162 |vmax=1.312|date=March 2008|price=$133 |sspec1=SLALT|step1=G0|part1=HH80557PG0642M |part2=BX80557E4700}} {{end}} {{note|MoreAgressiveHaltStateM0|c}} Note: The [[Intel Core (microarchitecture)#Steppings using 65nm process|M0 and G0 Steppings]] have better optimizations to lower idle power consumption from 12W to 8W. =====[[Conroe (microprocessor)#Conroe|"Conroe"]] (65 nm, 1066 MT/s) {{anchor|"Conroe" (65 nm)}} ===== *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2)''{{ref|NoTXT|a}} * All models support: [[Intel VT-x]] * [[Die (integrated circuit)|Die]] size: 143&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 65nm process|B2]], [[Intel Core (microarchitecture)#Steppings using 65nm process|G0]] {{cpulist|core|head}}<!-- edit Template:cpulist to modify the style of this table --> {{cpulist|core|conroe|model=Core 2 Duo E6300 |l2=2|fsb=1066|mult=7 |vmin=0.85 |vmax=1.5|date=July 2006|price=$183 |sspec1=SL9SA|step1=B2|part1=HH80557PH0362M |sspec2=SL9TA|step2=L2|part2=BX80557E6300 |sspec3=SLA2L|step3=?|part3=BX80557E6300T2 |sspec4=SLA5E|step4=?}} {{cpulist|core|conroe|model=Core 2 Duo E6320|l2=4|fsb=1066|mult=7 |vmin=0.85 |vmax=1.5|date=April 2007|price=$163 |sspec1=SLA4U|step1=B2|part1=HH80557PH0364M |part2=BX80557E6320}} {{cpulist|core|conroe|model=Core 2 Duo E6400 |l2=2|fsb=1066|mult=8 |vmin=0.85 |vmax=1.5|date=July 2006|price=$224 |sspec1=SL9S9|step1=B2|part1=HH80557PH0462M |sspec2=SLA5D|step2=?|part2=BX80557E6400 |sspec3=SL9T9|step3=L2 |sspec4=SLA97|step4=M0}} {{cpulist|core|conroe|model=Core 2 Duo E6420 |l2=4|fsb=1066|mult=8 |vmin=0.85 |vmax=1.5|date=April 2007|price=$183 |sspec1=SLA4T|step1=B2|part1=HH80557PH0464M |part2=BX80557E6420}} {{cpulist|core|conroe|model=Core 2 Duo E6600 |l2=4|fsb=1066|mult=9 |vmin=0.85 |vmax=1.5|date=July 2006|price=$316 |sspec1=SL9S8|step1=B2|part1=HH80557PH0564M |sspec2=SL9ZL|step2=B2|part2=BX80557E6600}} {{cpulist|core|conroe|model=Core 2 Duo E6700 |l2=4|fsb=1066|mult=10 |vmin=0.85 |vmax=1.5|date=July 2006|price=$530 |sspec1=SL9S7|step1=B2|part1=HH80557PH0674M |sspec2=SL9ZF|step2=B2|part2=BX80557E6700}} {{end}} {{note|NoTXT|a}}Note: of the E6000 series processors, only models E6550, E6750, and E6850 support Intel's [[Trusted Execution Technology]] (TXT).<ref name="E6xxxCompare">{{cite web |url=http://ark.intel.com/Compare.aspx?ids=30785,27251,30784,27248,29754,27249,29755,30782,30783,27250 |publisher=Intel Corporation |access-date=12 February 2010 |title=Advanced Technologies}}</ref> {{note|MoreAgressiveHaltStateL2|b}} Note: The [[Intel Core (microarchitecture)#Steppings using 65nm process|L2 Stepping]], and models with sSpec SL9ZL, SL9ZF, SLA4U, SLA4T, have better optimizations to lower idle power consumption from 22W to 12W.<ref name="moreagressivehaltstate">[http://www.behardware.com/news/8499/less-power-greedy-core-2-duo.html Less power greedy Core 2 Duo], BeHardware 15 November 2006</ref> {{note|MoreAgressiveHaltStateM0|c}} Note: The [[Intel Core (microarchitecture)#Steppings using 65nm process|M0 and G0 Steppings]] have better optimizations to lower idle power consumption from 12W to 8W. =====[[Conroe (microprocessor)#Conroe|"Conroe"]] (65 nm, 1333 MT/s) {{anchor|"Conroe" (65 nm)}} ===== *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2)''{{ref|NoTXT|a}} * All models support: [[Intel VT-x]] * All E6x50 models support: [[Intel VT-x]], [[Trusted Execution Technology]] (TXT) * [[Die (integrated circuit)|Die]] size: 143&nbsp;mm² * [[Transistor count]]: 291 million * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 65nm process|B2]], [[Intel Core (microarchitecture)#Steppings using 65nm process|G0]] {{cpulist|core|head}}<!-- edit Template:cpulist to modify the style of this table --> {{cpulist|core|conroe|model=Core 2 Duo E6540 |l2=4|fsb=1333|mult=7 |vmin=0.85 |vmax=1.5|date=July 2007|price=$163 |sspec1=SLAA5|step1=G0|part1=HH80557PJ0534M}} {{cpulist|core|conroe|model=Core 2 Duo E6550 |l2=4|fsb=1333|mult=7 |vmin=0.85 |vmax=1.5|date=July 2007|price=$163 |sspec1=SLA9X|step1=G0|part1=HH80557PJ0534MG |sspec2=SLAAT|step2=?|part2=BX80557E6550 |part3=BX80557E6550R}} {{cpulist|core|conroe|model=Core 2 Duo E6750 |l2=4|fsb=1333|mult=8 |vmin=0.85 |vmax=1.5|date=July 2007|price=$183 |sspec1=SLA9V|step1=G0|part1=HH80557PJ0674MG |step2=?|part2=BX80557E6750 |part3=BX80557E6750R|sspec2=SLAAR}} {{cpulist|core|conroe|model=Core 2 Duo E6850 |l2=4|fsb=1333|mult=9 |vmin=0.85 |vmax=1.5|date=July 2007|price=$266 |sspec1=SLA9U|step1=G0|part1=HH80557PJ0804MG |part2=BX80557E6850}} {{end}} {{note|NoTXT|a}}Note: of the E6000 series processors, only models E6550, E6750, and E6850 support Intel's [[Trusted Execution Technology]] (TXT).<ref name="E6xxxCompare"/> {{note|MoreAgressiveHaltStateL2|b}} Note: The [[Intel Core (microarchitecture)#Steppings using 65nm process|L2 Stepping]], and models with sSpec SL9ZL, SL9ZF, SLA4U, SLA4T, have better optimizations to lower idle power consumption from 22W to 12W.<ref name="moreagressivehaltstate"/> {{note|MoreAgressiveHaltStateM0|c}} Note: The [[Intel Core (microarchitecture)#Steppings using 65nm process|M0 and G0 Steppings]] have better optimizations to lower idle power consumption from 12W to 8W. =====[[Conroe (microprocessor)#Conroe-CL|"Conroe-CL"]] (65 nm, 1066 MT/s)===== *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]], [[Trusted Execution Technology]] (TXT)'' * [[Die (integrated circuit)|Die]] size: 111&nbsp;mm² (Conroe) * [[Stepping level|Steppings]]: ? {{cpulist|core|head}} {{cpulist|core|conroe|model=Core 2 Duo E6305 |l2=2|fsb=1066|mult=7|sock=[[LGA 771]]|links=1 |sspec1=SLAGF|part1=HH80557KH036F}} {{cpulist|core|conroe|model=Core 2 Duo E6405 |l2=2|fsb=1066|mult=8|sock=[[LGA 771]] |sspec1=SLAGG|part1=HH80557KH046F}} {{end}} =====[[Wolfdale (microprocessor)#Wolfdale-3M|"Wolfdale-3M"]] (45 nm, 1066 MT/s)===== * All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]].1, Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2)'' * [[Die (integrated circuit)|Die]] size: 82&nbsp;mm² * Transistor Count: 230 million * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|M0, R0]] * Models with a part number ending in "ML" instead of "M" support [[Intel VT-x]] {{cpulist|core|head}} {{cpulist|core|wolfdale|model=Core 2 Duo E7200 |l2=3|fsb=1066|mult=9.5 |vmin=0.85 |vmax=1.3625|date=April 2008|price=$133|links=1 |sspec1=SLAPC|step1=M0|part1=EU80571PH0613M |sspec2=SLAVN|step2=M0|part2=BX80571E7200 |sspec3=SLB9W|step3=?}} {{cpulist|core|wolfdale|model=Core 2 Duo E7300 |l2=3|fsb=1066|mult=10 |vmin=0.85 |vmax=1.3625|date=August 2008|price=$133 |sspec1=SLAPB|step1=M0|part1=EU80571PH0673M |sspec2=SLB9X|step2=R0|part2=AT80571PH0673M |sspec3=SLGA9|step3=R0<!-- also AT80571PH0673M, no VT version --> |part3=BX80571E7300}} {{cpulist|core|wolfdale|model=Core 2 Duo E7400 |l2=3|fsb=1066|mult=10.5 |vmin=0.85 |vmax=1.3625|date=October 2008|price=$133 |sspec1=SLB9Y|step1=R0|part1=AT80571PH0723M |sspec2=SLGQ8|step2=R0<!-- also AT80571PH0723M --> |sspec3=SLGW3|step3=R0, with VT|part2=AT80571PH0723ML|part3=BX80571E7400}} {{cpulist|core|wolfdale|model=Core 2 Duo E7500 |l2=3|fsb=1066|mult=11 |vmin=0.85 |vmax=1.3625|date=January 2009|price=$133 |sspec1=SLB9Z|step1=R0|part1=AT80571PH0773M |sspec2=SLGTE|step2=R0, with VT|part2=AT80571PH0773ML|part3=BX80571E7500}} {{cpulist|core|wolfdale|model=Core 2 Duo E7600 |l2=3|fsb=1066|mult=11.5 |vmin=0.85 |vmax=1.3625|date=May 2009|price=$133 |sspec1=SLGTD|step1=R0, with VT|part1=AT80571PH0833ML|part2=BX80571E7600}} {{end}} =====[[Wolfdale (microprocessor)#Wolfdale|"Wolfdale"]] (45 nm, 1333 MT/s)===== *All models(except E8190) support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]].1, Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 ([[Intel Active Management Technology]]), [[Intel VT-x]] {{ref label|NoVT-x|a|a}}, [[Intel VT-d]] {{ref label|NoVT-d|b|b}}, [[Trusted Execution Technology]] (TXT)'' * [[Die (integrated circuit)|Die]] size: 107&nbsp;mm² * Transistor Count: 410 million * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|C0, E0]] {{cpulist|core|head}} {{cpulist|core|wolfdale|model=Core 2 Duo E8190 |l2=6|fsb=1333|mult=8 |vmin=0.85 |vmax=1.3625|date=January 2008|price=$163|links=1 |sspec1=SLAQR|step1=C0|part1=EU80570PJ0676MN}} {{cpulist|core|wolfdale|model=Core 2 Duo E8200 |l2=6|fsb=1333|mult=8 |vmin=0.85 |vmax=1.3625|date=January 2008|price=$163 |sspec1=SLAPP|step1=C0|part1=EU80570PJ0676M |part2=BX80570E8200}} {{cpulist|core|wolfdale|model=Core 2 Duo E8290<ref>{{cite web |url=http://www.cpu-world.com/CPUs/Core_2/Intel-Core%202%20Duo%20E8290%20EU80570PJ0736MN.html |title=Intel Core 2 Duo E8290 - EU80570PJ0736MN}}</ref> |l2=6|fsb=1333|mult=8.5 |vmin=0.85 |vmax=1.3625|date=?|price=? |sspec1=SLAQQ|step1=?|part1=EU80570PJ0736MN}} {{cpulist|core|wolfdale|model=Core 2 Duo E8300 |l2=6|fsb=1333|mult=8.5 |vmin=0.85 |vmax=1.3625|date=April 2008|price=$163 |sspec1=SLAPJ|step1=C0|part1=EU80570AJ0736M |sspec2=SLAPN|step2=C0|part2=EU80570PJ0736M}} {{cpulist|core|wolfdale|model=Core 2 Duo E8400 |l2=6|fsb=1333|mult=9 |vmin=0.85 |vmax=1.3625|date=January 2008|price=$183 |sspec1=SLAPL|step1=C0|part1=EU80570PJ0806M |sspec2=SLB9J|step2=E0|part2=AT80570PJ0806M |part3=BX80570E8400}} {{cpulist|core|wolfdale|model=Core 2 Duo E8500 |l2=6|fsb=1333|mult=9.5 |vmin=0.85 |vmax=1.3625|date=January 2008|price=$266 |sspec1=SLAPK|step1=C0|part1=EU80570PJ0876M |sspec2=SLB9K|step2=E0|part2=AT80570PJ0876M |part3=BX80570E8500}} {{cpulist|core|wolfdale|model=Core 2 Duo E8600 |l2=6|fsb=1333|mult=10 |vmin=0.85 |vmax=1.3625|date=August 2008|price=$266 |sspec1=SLB9L|step1=E0|part1=AT80570PJ0876M |part2=BX80570E8600}} {{cpulist|core|wolfdale|model=Core 2 Duo E8700 |l2=6|fsb=1333|mult=10.5 |vmin=0.85 |vmax=1.3625|date=December 2009|price=NA |sspec1=SLB9E|step1=E0|part1=AT80570PJ1006M(OEM) |part2=}} {{end}} {{note label|NoVT-d|a|a}}Note: The E8190 and E8290 do not support Intel VT-d. See also: Versions of the same Wolfdale core in an LGA 771 are available under the [[List of Intel Xeon microprocessors#"Wolfdale-DP" (standard-voltage, 45 nm)|Dual-Core Xeon]] brand. ====Core 2 Extreme==== =====[[Conroe (microprocessor)#Conroe XE|"Conroe XE"]] (65 nm)===== <ref name="conroespeculation">{{cite web |url=http://www.theinquirer.net/default.aspx?article=29504 |title=Details regarding Conroe models |date=6 February 2006 |work=[[The Inquirer]] |url-status=unfit |archive-url=https://web.archive.org/web/20061231025917/http://www.theinquirer.net/default.aspx?article=29504 |archive-date=2006-12-31}}</ref><ref name="x6900">[http://www.dailytech.com/article.aspx?newsid=2625 DailyTech article on upcoming Core 2 Extreme CPUs] {{Webarchive|url=https://web.archive.org/web/20060615031921/http://www.dailytech.com/article.aspx?newsid=2625 |date=2006-06-15 }}, 31 May 2006</ref> ''These models feature an [[CPU locking|unlocked]] [[clock multiplier]]'' *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]], [[Trusted Execution Technology]] (TXT)'' * [[Die (integrated circuit)|Die]] size: 143&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 65nm process|B1, B2]] * The X6900 was never publicly released. {{cpulist|core|head}} {{cpulist|core|conroe|model=Core 2 Extreme X6800 |l2=4|fsb=1066|mult=11 |vmin=0.85 |vmax=1.5|tdp=75|date=July 2006|price=$999|links=1 |sspec1=SL9S5|step1=B2|part1=HH80557PH0677M |sspec2=QPHV|step2=B1|part2=BX80557X6800}} {{cpulist|core|conroe|model=Core 2 Extreme X6900<ref>{{cite web |url=http://www.cpu-world.com/sspec/QT/QTOM.html |title = QTOM (Intel Core 2 Duo 3.2 GHZ)}}</ref><ref>{{cite web|url=http://www.cpu-world.com/forum/viewtopic.php?t=13930 |title=forums :: View topic - Need help with identifying a Core 2 (TM) CPU (ES) processor |publisher=Cpu-world.com |date= |accessdate=2022-04-04}}</ref> |l2=4|fsb=1066|mult=12 |vmin=0.85 |vmax=1.5|tdp=75|date=N/A|price=N/A|links=1 |sspec1=QTOM|step1=B2|part1=HH80557PH0884M |sspec2=SL9S4|step2=B2}} {{end}} ===Quad-Core Desktop processors=== ====Core 2 Quad==== =====[[Kentsfield (microprocessor)#Kentsfield|"Kentsfield"]] (65 nm)===== <ref name="q6600">[http://www.dailytech.com/article.aspx?newsid=4217 Intel Core 2 Quad Announced Internally] {{Webarchive|url=https://web.archive.org/web/20060921090718/http://www.dailytech.com/article.aspx?newsid=4217 |date=2006-09-21 }}, DailyTech, 19 September 2006</ref><ref name="q6600rel">[http://www.dailytech.com/article.aspx?newsid=5595 Intel Hard-Launches Three New Quad-core Processors] {{Webarchive|url=https://web.archive.org/web/20160405061432/http://www.dailytech.com/article.aspx?newsid=5595 |date=2016-04-05 }}, DailyTech, 7 January 2007</ref> *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]]'' * [[Die (integrated circuit)|Die]] size: 2 ×143&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 65nm process|B3, G0]] {{cpulist|core|head}} {{cpulist|core|kentsfield|model=Core 2 Quad Q6400<ref>{{cite web|url=http://www.cpu-world.com/sspec/SL/SL9UN.html|access-date=2018-10-27|title=SL9UN (Intel Core 2 Quad Q6400)|work=CPU-World}}</ref> |l2=8|fsb=1066|mult=8|tdp=105 |vmin=0.8500 |vmax=1.500|price=OEM|links=1 |sspec1=SL9UN|step1=B3|part1=HH80562PH0468M}} {{cpulist|core|kentsfield|model=Core 2 Quad Q6600 |l2=8|fsb=1066|mult=9 |vmin=0.8500 |vmax=1.500|date=January 2007|price=$851 |sspec1=SL9UM|step1=B3|tdp1=105|part1=HH80562PH0568M |sspec2=SLACR|step2=G0|tdp2=95|part2=BX80562Q6600 |part3=BXC80562Q6600}} {{cpulist|core|kentsfield|model=Core 2 Quad Q6700 |l2=8|fsb=1066|mult=10|tdp=95 |vmin=0.8500 |vmax=1.500|date=July 2007|price=$530 |sspec1=SLACQ|step1=G0|part1=HH80562PH0678M |part2=BX80562Q6700 |part3=BXC80562Q6700}} {{end}} =====[[Yorkfield (microprocessor)#Yorkfield-6M|"Yorkfield-6M"]] (45 nm)===== *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]].1, Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]] {{ref label|NoVT-x|a|a}}, [[Intel VT-d]] {{ref label|NoVT-d|b|b}}, [[Trusted Execution Technology]] (TXT) {{ref label|NoTXT|c|c}}'' * [[Die (integrated circuit)|Die]] size: 2 × 82&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|M0, M1, R0]] * All Q8xxx models are Yorkfield-6M MCMs with only 2 × 2 MB L2 cache enabled. {{cpulist|core|head}} {{cpulist|core|yorkfield|model=Core 2 Quad Q8200 |l2=4|fsb=1333|mult=7 |vmin=0.85 |vmax=1.3625|tdp=95|date=August 2008|price=$224|links=1 |sspec1=SLB5M|step1=M1|part1=EU80580PJ0534MN |sspec2=SLG9S|step2=R0|part2=AT80580PJ0534MN}} {{cpulist|core|yorkfield|model=Core 2 Quad Q8200S |l2=4|fsb=1333|mult=7 |vmin=0.85 |vmax=1.3625|tdp=65|date=January 2009|price=$245 |sspec1=SLG9T|step1=R0|part1=AT80580AJ0534MN |sspec2=SLGSS|step2=R0, with Intel VT-x|part2=AT80580AJ0534ML}} {{cpulist|core|yorkfield|model=Core 2 Quad Q8300 |l2=4|fsb=1333|mult=7.5 |vmin=0.85 |vmax=1.3625|tdp=95|date=November 2008|price=$224 |sspec1=SLB5W|step1=R0|part1=AT80580PJ0604MN |sspec2=SLGUR|step2=R0, with Intel VT-x|part2=AT80580PJ0604ML}} {{cpulist|core|yorkfield|model=Core 2 Quad Q8400 |l2=4|fsb=1333|mult=8 |vmin=0.85 |vmax=1.3625|tdp=95|date=April 2009|price=$183 |sspec1=SLGT6|step1=R0, with Intel VT-x|part1=AT80580PJ0674ML}} {{cpulist|core|yorkfield|model=Core 2 Quad Q8400S |l2=4|fsb=1333|mult=8 |vmin=0.85 |vmax=1.3625|tdp=65|date=April 2009|price=$245 |sspec1=SLGT7|step1=R0, with Intel VT-x|part1=AT80580AJ0674ML}} {{cpulist|core|yorkfield|model=Core 2 Quad Q9300 |l2=6|fsb=1333|mult=7.5 |vmin=0.85 |vmax=1.3625|tdp=95|date=March 2008|price=$266 |sspec1=SLAMX|step1=M0|part1=EU80580PJ0606M |sspec2=SLAWE|step2=M1}} {{cpulist|core|yorkfield|model=Core 2 Quad Q9400 |l2=6|fsb=1333|mult=8 |vmin=0.85 |vmax=1.3625|tdp=95|date=August 2008|price=$266 |sspec1=SLB6B|step1=R0|part1=AT80580PJ0676M}} {{cpulist|core|yorkfield|model=Core 2 Quad Q9400S |l2=6|fsb=1333|mult=8 |vmin=0.85 |vmax=1.3625|tdp=65|date=January 2009|price=$320 |sspec1=SLG9U|step1=R0|part1=AT80580AJ0676M}} {{cpulist|core|yorkfield|model=Core 2 Quad Q9500 |l2=6|fsb=1333|mult=8.5 |vmin=0.85 |vmax=1.3625|tdp=95|date=January 2010|price=$183 |sspec1=SLGZ4|step1=R0|part1=AT80580PJ0736ML}} {{cpulist|core|yorkfield|model=Core 2 Quad Q9505 |l2=6|fsb=1333|mult=8.5 |vmin=0.85 |vmax=1.3625|tdp=95|date=August 2009|price=$213 |sspec1=SLGYY|step1=R0|part1=AT80580PJ0736MG}} {{cpulist|core|yorkfield|model=Core 2 Quad Q9505S |l2=6|fsb=1333|mult=8.5 |vmin=0.85 |vmax=1.3625|tdp=65|date=August 2009|price=$277 |sspec1=SLGYZ|step1=R0|part1=AT80580AJ0736MG}} {{end}} {{note label|NoVT-x|a|a}}Note: Q8200, Q8200S, Q8300 SLB5W does not support Intel VT-x. {{note label|NoVT-d|b|b}}Note: Q8200, Q8200S, Q8300, Q8400, Q8400S, Q9500 does not support Intel VT-d. {{note label|NoTXT|c|c}}Note: Q8200, Q8200S, Q8300, Q8400, Q8400S does not support TXT. =====[[Yorkfield#Yorkfield|Yorkfield]] (45 nm)===== * All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]].1, Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]], [[Intel VT-d]], [[Trusted Execution Technology]] (TXT)'' * [[Die (integrated circuit)|Die]] size: 2 × 107&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|C0, C1, E0]] {{cpulist|core|head}} {{cpulist|core|yorkfield|model=Core 2 Quad Q9450|l2=12|fsb=1333|mult=8 |vmin=0.85 |vmax=1.3625|tdp=95|date=March 2008|price=$316|links=1 |sspec1=SLAN6|step1=C0|part1=EU80569PJ067N |sspec2=SLAWR|step2=C1}} {{cpulist|core|yorkfield|model=Core 2 Quad Q9550|l2=12|fsb=1333|mult=8.5 |vmin=0.85 |vmax=1.3625|tdp=95|date=March 2008|price=$530 |sspec1=SLAN4|step1=C0|part1=EU80569PJ073N |sspec2=SLAWQ|step2=C1|part2=AT80569PJ073N |sspec3=SLB8V|step3=E0}} {{cpulist|core|yorkfield|model=Core 2 Quad Q9550S|l2=12|fsb=1333|mult=8.5 |vmin=0.85 |vmax=1.3625|tdp=65|date=January 2009|price=$369 |sspec1=SLGAE|step1=E0|part1=AT80569AJ073N}} {{cpulist|core|yorkfield|model=Core 2 Quad Q9650|l2=12|fsb=1333|mult=9 |vmin=0.85 |vmax=1.3625|tdp=95|date=August 2008|price=$530 |sspec1=SLB8W|step1=E0|part1=AT80569PJ080N |part2=BX80569Q9650}} {{end}} ====Core 2 Extreme==== =====[[Kentsfield (microprocessor)#Kentsfield XE|"Kentsfield XE"]] (65 nm)===== <ref name="qx6700">[http://www.dailytech.com/article.aspx?newsid=3829 "Kentsfield" to Debut at 2.66 GHz] {{Webarchive|url=https://web.archive.org/web/20061021081154/http://www.dailytech.com/article.aspx?newsid=3829 |date=2006-10-21 }}, DailyTech, 16 August 2006</ref> ''These models feature an [[CPU locking|unlocked]] [[clock multiplier]]'' *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]]'' * [[Die (integrated circuit)|Die]] size: 2 ×143&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 65nm process|B3, G0]] {{cpulist|core|head}} {{cpulist|core|kentsfield|model=Core 2 Extreme QX6700|l2=8|fsb=1066|mult=10 |vmin=0.8500 |vmax=1.500|tdp=130|date=November 2006|price=$999|links=1 |sspec1=SL9UL|step1=B3|part1=HH80562PH0678M}} {{cpulist|core|kentsfield|model=Core 2 Extreme QX6800|l2=8|fsb=1066|mult=11 |vmin=0.8500 |vmax=1.500|tdp=130|date=April 2007|price=$1199 |sspec1=SL9UK|step1=B3|part1=HH80562PH0778M |sspec2=SLACP|step2=G0|part2=HH80562XH0778M}} {{cpulist|core|kentsfield|model=Core 2 Extreme QX6850|l2=8|fsb=1333|mult=9 |vmin=0.8500 |vmax=1.500|tdp=130|date=July 2007|price=$999 |sspec1=SLAFN|step1=G0|part1=HH80562XJ0808M}} {{end}} =====[[Yorkfield (microprocessor)#Yorkfield XE|"Yorkfield XE"]] (45 nm)===== *These models feature an [[CPU locking|unlocked]] [[clock multiplier]] *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]].1, Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]]'' * I/O Acceleration Technology (Intel I/OAT) supported by: QX9775 * Intel VT-d supported by: QX9650<ref>{{cite web|url=https://ark.intel.com/content/www/us/en/ark/products/35428/intel-core-2-quad-processor-q9650-12m-cache-3-00-ghz-1333-mhz-fsb.html|title=Intel Core2 Quad Processor Q9650 (12M Cache, 3.00 GHz, 1333 MHz FSB) Product Specifications|website=ark.intel.com|access-date=26 June 2019}}</ref> * [[Die (integrated circuit)|Die]] size: 2 × 107&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|C0, C1, E0]] * The QX9750 was never publicly released. Engineering samples have surfaced along with claims that Intel gave them away to employees sometime in 2009.<ref>{{cite web |url=https://forums.guru3d.com/threads/qx9750.299053/ |title=Qx9750!!! :)}}</ref><ref>{{cite web |url=https://forums.anandtech.com/threads/building-around-my-new-qx-9750.295480/ |title=Building around my new QX-9750}}</ref><ref>{{cite web |url=https://hardforum.com/threads/my-new-chip-woo-hoo.1411896/ |title = My new chip WOO HOO!!!}}</ref> {{cpulist|core|head}} {{cpulist|core|yorkfield|model=Core 2 Extreme QX9650|l2=12|fsb=1333|mult=9 |vmin=0.85 |vmax=1.3625|tdp=130|date=November 2007<ref name="channelregister-071116">{{cite web |url=http://www.intel.com/pressroom/archive/releases/2007/20071111comp.htm |title=Intel's Fundamental Advance in Transistor Design Extends Moore's Law, Computing Performance |date=11 November 2007 |author=Intel Corporation}}</ref>|price=$999|links=1 |sspec1=SLAN3|step1=C0|part1=EU80569XJ080NL |sspec2=SLAWN|step2=C1|part2=BX80569QX9650}} {{cpulist|core|yorkfield|model=Core 2 Extreme QX9750<ref>{{cite web |url=http://www.cpu-world.com/CPUs/Core_2/Intel-Core%202%20Extreme%20QX9750.html |title=Intel Core 2 Extreme QX9750 AT80569XJ087NL}}</ref> |l2=12|fsb=1333|mult=9.5 |vmin=0.85 |vmax=1.3625|tdp=130|date=N/A|price=N/A |sspec1=QJEE|step1=E0|part1=AT80569XL087NL |sspec2=SLBBU|step2=E0}} {{cpulist|core|yorkfield|model=Core 2 Extreme QX9770|l2=12|fsb=1600|mult=8 |vmin=0.85 |vmax=1.3625|tdp=136|date=March 2008|price=$1399 |sspec1=SLAN2|step1=C0|part1=EU80569XL088NL |sspec2=SLAWM|step2=C1|part2=BX80569QX9770}} {{cpulist|core|yorkfield|model=Core 2 Extreme QX9775|l2=12|fsb=1600|mult=8 |vmin=0.85 |vmax=1.35|tdp=150|sock=LGA 771|date=March 2008|price=$1499 |sspec1=SLANY|step1=C0|part1=EU80574XL088N|part2=BX80574QX9775}} {{end}} ==Notebook (mobile) processors== ===Single-Core Notebook processors=== ====Core 2 Solo==== =====[[Merom (microprocessor)#Merom-L|"Merom-L"]] (65 nm) {{anchor|"Merom-L" (ultra-low-voltage, 65 nm)}} ===== *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]], [[Trusted Execution Technology]] (TXT)'' * [[Die (integrated circuit)|Die]] size: 81&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 65nm process|A1]] {{cpulist|core|head}} {{cpulist|core|section=ultra-low voltage}} {{cpulist|core|merom|model=Core 2 Solo ULV U2100|l2=1|fsb=533|mult=8 |vmin=0.86 |vmax=0.975|tdp=5.5|sock=[[Micro-FCBGA]]|date=September 2007|price=$241|links=1 |sspec1=SLAGM|cores=1|step1=A1|part1=LE80537UE0041M}} {{cpulist|core|merom|model=Core 2 Solo ULV U2200|l2=1|fsb=533|mult=9 |vmin=0.86 |vmax=0.975|tdp=5.5|sock=Micro-FCBGA|date=September 2007|price=$262 |sspec1=SLAGL|cores=1|step1=A1|part1=LE80537UE0091M}} {{end}} =====[[Penryn (microprocessor)#Penryn-L|"Penryn-L"]] (45 nm) {{anchor|"Penryn-L" (ultra-low-voltage, 45 nm, Small Form Factor)}} ===== * All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]].1, Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]], [[Trusted Execution Technology]] (TXT), Intel Dynamic Acceleration (IDA)'' * [[Socket P]] processors can throttle the [[front-side bus]] (FSB) anywhere between 400 and 800 MT/s as needed. * [[Die (integrated circuit)|Die]] size: 82&nbsp;mm² * 228 million transistors * Package size: 22&nbsp;mm × 22&nbsp;mm * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|M0, R0]] {{cpulist|core|head}} {{cpulist|core|section=Small Form Factor, ultra-low voltage}} {{cpulist|core|penrynulv|model=Core 2 Solo SU3300|sspec1=SLGAR|cores=1|step1=M0|sspec2=SLGAJ|step2=R0|mult=6|fsb=800|l2=3 |vmin=1.05 |vmax=1.15|tdp=5.5|date=May 2008|part1=AV80585UG0093M|price=$262|links=1}} {{cpulist|core|penrynulv|model=Core 2 Solo SU3500|sspec1=SLGFM|cores=1|step1=R0|mult=7|fsb=800|l2=3 |vmin=1.05 |vmax=1.15|tdp=5.5|date=Q2 2009|part1=AV80585UG0173M|price=$262}} {{end}} ===Dual-Core Notebook processors=== ====Core 2 Duo==== [[File:Laptop-intel-core2duo-t5500.jpg|thumb|150px|Inside of old Sony VAIO laptop (VGN-C140G)]] =====[[Merom (microprocessor)#Merom|"Merom"]], [[Merom (microprocessor)#Merom-2M|"Merom-2M"]] (standard-voltage, 65 nm) {{anchor|"Merom-2M" (standard-voltage, 65 nm)|"Merom" (standard-voltage, 65 nm)|T7600}} ===== *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2)'' * Model T7600G features an unlocked clock multiplier. Only sold OEM in the [[Dell XPS]] M1710. * ''[[Intel VT-x]]'': Supported by T5500 (L2), T5600 and all T7xxx * ''Intel Dynamic Front Side Bus Frequency Switching'': Supported by [[Intel Core (microarchitecture)#Steppings using 65nm process|E1, G0, G2, M0 Steppings]] * Socket P processors can throttle the [[front-side bus]] (FSB) anywhere between 400 and 800 MT/s as needed. * [[Die (integrated circuit)|Die]] size: 143&nbsp;mm² (Merom), 111&nbsp;mm² (Merom-2M) * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 65nm process|B2, E1, G0, G2]] (Merom), [[Intel Core (microarchitecture)#Steppings using 65nm process|L2, M0]] (Merom-2M) * All models of stepping B2 released in July 2006, stepping L2 released in January 2007. {{cpulist|core|head}} {{cpulist|core|merom|model=Core 2 Duo T5200|l2=2|fsb=533|mult=12 |vmin=0.95 |vmax=1.175|tdp=34|sock=[[Socket M]]|date=October 2006|price=[[Original equipment manufacturer|OEM]]|links=1 |sspec1=SL9VP|step1=B2|part1=LF80537GE0252M}} {{cpulist|core|merom|model=Core 2 Duo T5250|l2=2|fsb=667|mult=9 |vmin=0.95 |vmax=1.175|tdp=35|sock=[[Socket P]]|date=Q2 2007|price=OEM |sspec1=SLA9S|step1=M0|part1=LF80537GF0212M}} {{cpulist|core|merom|model=Core 2 Duo T5270|l2=2|fsb=800|mult=7 |vmin=0.95 |vmax=1.175|tdp=35|sock=Socket P|date=October 2007|price=OEM |sspec1=SLALK|step1=M0|part1=LF80537GG0172M}} {{cpulist|core|merom|model=Core 2 Duo T5300|l2=2|fsb=533|mult=13 |vmin=0.95 |vmax=1.175|tdp=34|sock=Socket M|date=Q1 2007|price=OEM |sspec1=SL9WE|step1=L2|part1=LF80537GE0302M}} {{cpulist|core|merom|model=Core 2 Duo T5450|l2=2|fsb=667|mult=10 |vmin=0.95 |vmax=1.175|tdp=35|sock=Socket P|date=Q2 2007|price=OEM |sspec1=SLA4F|step1=M0|part1=LF80537GF0282MT}} {{cpulist|core|merom|model=Core 2 Duo T5470|l2=2|fsb=800|mult=8 |vmin=0.95 |vmax=1.175|tdp=35|sock=Socket P|date=July 2007|price=OEM |sspec1=SLAEB|step1=M0|part1=LF80537GG0252M}} {{cpulist|core|merom|model=Core 2 Duo T5500|l2=2|fsb=667|mult=10 |vmin=0.95 |vmax=1.175|tdp=34|sock=Socket M|date=28 August 2006|price=$209 |sspec1=SL9SH|step1=B2|part1=LF80537GF0282M |sspec2=SLGFK|step2=G2 |sspec3=SL9U4|step3=L2}} {{cpulist|core|merom|model=Core 2 Duo T5500|l2=2|fsb=667|mult=10 |vmin=0.95 |vmax=1.175|tdp=34|sock=BGA479|date=August 2006|price=$209 |sspec1=SL9SQ|step1=B2|part1=LE80537GF0282M |sspec2=SL9U8|step2=L2}} {{cpulist|core|merom|model=Core 2 Duo T5550|l2=2|fsb=667|mult=11 |vmin=0.95 |vmax=1.175|tdp=35|sock=Socket P|date=January 2008|price=OEM |sspec1=SLA4E|step1=M0|part1=LF80537GF0342MT}} {{cpulist|core|merom|model=Core 2 Duo T5600|l2=2|fsb=667|mult=11 |vmin=0.95 |vmax=1.175|tdp=34|sock=Socket M|date=August 2006|price=$241 |sspec1=SL9SG|step1=B2|part1=LF80537GF0342M |sspec2=SL9U3|step2=L2}} {{cpulist|core|merom|model=Core 2 Duo T5600|l2=2|fsb=667|mult=11 |vmin=0.95 |vmax=1.175|tdp=34|sock=BGA479|date=August 2006|price=$241 |sspec1=SL9SP|step1=B2|part1=LE80537GF0342M |sspec2=SL9U7|step2=L2}} {{cpulist|core|merom|model=Core 2 Duo T5670|l2=2|fsb=800|mult=9 |vmin=0.95 |vmax=1.175|tdp=35|sock=Socket P|date=Q2 2008|price=OEM |sspec1=SLAJ5|step1=M0|part1=LF80537GG0332MN}} {{cpulist|core|merom|model=Core 2 Duo T5750|l2=2|fsb=667|mult=12 |vmin=0.95 |vmax=1.175|tdp=35|sock=Socket P|date=January 2008|price=OEM |sspec1=SLA4D|step1=M0|part1=LF80537GF0412M}} {{cpulist|core|merom|model=Core 2 Duo T5800|l2=2|fsb=800|mult=10 |vmin=0.95 |vmax=1.175|tdp=35|sock=Socket P|date=Q4 2008|price=OEM |sspec1=SLB6E|step1=M0|part1=LF80537GG041F}} {{cpulist|core|merom|model=Core 2 Duo T5850<ref>{{cite web|url=http://www.cpu-world.com/sspec/SL/SLA4C.html|title=SLA4C (Intel Core 2 Duo T5850)|access-date=2018-10-27|work=CPU-World}}</ref> |l2=2|fsb=667|mult=13 |vmin=0.95 |vmax=1.175|tdp=35|sock=Socket P|date=Q4 2008|price=OEM |sspec1=SLA4C|step1=M0|part1=LF80537GF0482M}} {{cpulist|core|merom|model=Core 2 Duo T5870|l2=2|fsb=800|mult=10 |vmin=0.95 |vmax=1.175|tdp=35|sock=Socket P|date=2008|price=OEM |sspec1=SLAZR|step1=M0|part1=LF80537GG0412MN}} {{cpulist|core|merom|model=Core 2 Duo T5900<ref>{{cite web|url=http://www.cpu-world.com/sspec/SL/SLB6D.html|title=SLB6D (Intel Core 2 Duo T5900)|access-date=2018-10-27|work=CPU-World}}</ref> |l2=2|fsb=800|mult=11 |vmin=0.95 |vmax=1.175|tdp=35|sock=Socket P|date=July 2008|price=OEM |sspec1=SLB6D|step1=M0|part1=LF80537GG049F}} {{cpulist|core|merom|model=Core 2 Duo T7100|l2=2|fsb=800|mult=9 |vmin=0.95 |vmax=1.175|tdp=35|date=May 2007|price=$209 |sspec1=SLA4A|step1=M0|sock1=Socket P|part1=LF80537GG0332M }} {{cpulist|core|merom|model=Core 2 Duo T7100|l2=2|fsb=800|mult=9 |vmin=0.95 |vmax=1.175|tdp=35|date=May 2007|price=$209 |sspec1=SLA3U|step1=M1|sock1=FCBGA6|part1=LE80537GG0332M }} {{cpulist|core|merom|model=Core 2 Duo T7200|l2=4|fsb=667|mult=12 |vmin=0.95 |vmax=1.175|tdp=34|date=August 2006|price=$294 |sspec1=SL9SF|step1=B2|sock1=Socket M|part1=LF80537GF0414M }} {{cpulist|core|merom|model=Core 2 Duo T7200|l2=4|fsb=667|mult=12 |vmin=0.95 |vmax=1.175|tdp=34|date=August 2006|price=$294 |sspec1=SL9SL|step1=B2|sock1=FCBGA6|part1=LE80537GF0414M }} {{cpulist|core|merom|model=Core 2 Duo T7250|l2=2|fsb=800|mult=10 |vmin=0.95 |vmax=1.175|tdp=35|date=September 2007|price=$290 |sspec1=SLA49|step1=M0|sock1=Socket P|part1=LF80537GG0412M |sspec2=SLAXH|step2=M0 }} {{cpulist|core|merom|model=Core 2 Duo T7250|l2=2|fsb=800|mult=10 |vmin=0.95 |vmax=1.175|tdp=35|date=September 2007|price=$290 |sspec1=SLA3T|step1=M1|sock1=FCBGA6|part1=LE80537GG0412M }} {{cpulist|core|merom|model=Core 2 Duo T7300|l2=4|fsb=800|mult=10 |vmin=0.95 |vmax=1.175|tdp=35|date=May 2007|price=$241 |sspec1=SLAMD|step1=G0|sock1=Socket P|part1=LF80537GG0414M |sspec2=SLA45|step2=E1|part2=LF80537GG0414M }} {{cpulist|core|merom|model=Core 2 Duo T7300|l2=4|fsb=800|mult=10 |vmin=0.95 |vmax=1.175|tdp=35|date=May 2007|price=$241 |sspec1=SLA3P|step1=E1|sock1=FCBGA6|part1=LE80537GG0414M |sspec2=SLAMF|step2=G0 }} {{cpulist|core|merom|model=Core 2 Duo T7400|2166&nbsp;MHz |l2=4|fsb=667|mult=13 |vmin=0.95 |vmax=1.175|tdp=34|date=August 2006|price=$423 |sspec1=SL9SE|step1=B2|sock1=Socket M|part1=LF80537GF0484M |sspec2=SLGFJ|step2=G2 }} {{cpulist|core|merom|model=Core 2 Duo T7400|2166&nbsp;MHz |l2=4|fsb=667|mult=13 |vmin=0.95 |vmax=1.175|tdp=34|date=August 2006|price=$423 |sspec1=SL9SK|step1=B2|sock1=FCBGA6|part1=LE80537GF0484M |sspec2=SLGFV|step2=G2 }} {{cpulist|core|merom|model=Core 2 Duo T7500|2200&nbsp;MHz |l2=4|fsb=800|mult=11 |vmin=0.95 |vmax=1.175|tdp=35|date=May 2007|price=$316 |sspec1=SLA44|step1=E1|sock1=Socket P|part1=LF80537GG0494M |sspec2=SLAF8|step2=G0 }} {{cpulist|core|merom|model=Core 2 Duo T7500|2200&nbsp;MHz |l2=4|fsb=800|mult=11 |vmin=0.95 |vmax=1.175|tdp=35|date=May 2007|price=$316 |sspec1=SLA3N|step1=E1|sock1=FCBGA6|part1=LE80537GG0494M |sspec2=SLADM|step2=G0 }} {{cpulist|core|merom|model=Core 2 Duo T7600|l2=4|fsb=667|mult=14 |vmin=0.95 |vmax=1.175|tdp=34|date=August 2006|price=$637 |sspec1=SL9SD|step1=B2|sock1=Socket M|part1=LF80537GF0534M }} {{cpulist|core|merom|model=Core 2 Duo T7600|l2=4|fsb=667|mult=14 |vmin=0.95 |vmax=1.175|tdp=34|date=August 2006|price=$637 |sspec1=SL9SJ|step1=B2|sock1=FCBGA6|part1=LE80537GF0534M }} {{cpulist|core|merom|model=Core 2 Duo T7600G<ref>{{cite web|url=http://www.cpu-world.com/sspec/SL/SL9U5.html|work=CPU-World |access-date=2018-10-27|title=SL9U5 (Intel Core 2 Duo T7600G)}}</ref> |l2=4|fsb=667|mult=14 |vmin=0.95 |vmax=1.175|tdp=34|date=December 2006|price= |sspec1=SL9U5|step1=B2|sock1=Socket M|part1=LF80537GF0534MU }} {{cpulist|core|merom|model=Core 2 Duo T7700|2400&nbsp;MHz |l2=4|fsb=800|mult=12 |vmin=0.95 |vmax=1.175|tdp=35|date=May 2007|price=$530 |sspec1=SLA43|step1=E1|sock1=Socket P|part1=LF80537GG0564M |sspec2=SLAF7|step2=G0 }} {{cpulist|core|merom|model=Core 2 Duo T7700|2400&nbsp;MHz |l2=4|fsb=800|mult=12 |vmin=0.95 |vmax=1.175|tdp=35|date=May 2007|price=$530 |sspec1=SLA3M|step1=E1|sock1=FCBGA6|part1=LE80537GG0564M |sspec2=SLADL|step2=G0 }} {{cpulist|core|merom|model=Core 2 Duo T7800|l2=4|fsb=800|mult=13 |vmin=0.95 |vmax=1.175|tdp=35|date=September 2007|price=$530 |sspec1=SLAF6|step1=G0|sock1=Socket P|part1=LF80537GG0644ML }} {{cpulist|core|merom|model=Core 2 Duo T7800|l2=4|fsb=800|mult=13 |vmin=0.95 |vmax=1.175|tdp=35|date=September 2007|price=$530 |sspec1=SLA75|step1=G0|sock1=FCBGA6|part1=LE80537GG0644M }} {{end}} See also: Versions of the same Merom-2M core with half the L2 cache disabled are available under the [[List of Intel Pentium Dual-Core microprocessors#"Merom-M", "Merom-2M" (65 nm)|Pentium Dual-Core]] brand. =====[[Merom (microprocessor)#Merom|"Merom"]] (low-voltage, 65 nm)===== [[File:Intel Core 2 Duo L7500.jpg|150px|thumb|Intel Core 2 Duo L7500]] *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]], [[Trusted Execution Technology]] (TXT)'' * ''Intel Dynamic Front Side Bus Frequency Switching'': Supported by [[Intel Core (microarchitecture)#Steppings using 65nm process|E1, G0, G2 Steppings]] * [[Die (integrated circuit)|Die]] size: 143&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 65nm process|B2, E1, G0, G2]] {{cpulist|core|head}} {{cpulist|core|merom|model=Core 2 Duo SL7100<ref>{{cite web|url=https://www.infoworld.com/article/2650885/computer-hardware/intel-develops-processor-similar-to-macbook-air-chip.html|title=Intel develops processor similar to MacBook Air chip|date=2008-02-11|work=[[InfoWorld]]|access-date=2018-10-27|first1=Agam|last1=Shah}}</ref> |l2=4|fsb=800|mult=6|tdp=12|sock=[[μFC-BGA 956]]|price=OEM|links=1 |sspec1=SLAJD|sspec2=SLAT4|part1=SY80537LG0094M}} {{cpulist|core|merom|model=Core 2 Duo L7200|l2=4|fsb=667|mult=8 |vmin=0.9 |vmax=1.2|tdp=17|sock=FCBGA6|date=Q1 2007|price=$284 |sspec1=SL9SN|step1=B2|part1=LE80537LF0144M}} {{cpulist|core|merom|model=Core 2 Duo L7300|l2=4|fsb=800|mult=7 |vmin=0.9 |vmax=1.1|tdp=17|sock=FCBGA6|date=May 2007|price=$284 |sspec1=SLA3S|step1=E1|part1=LE80537LG0174M}} {{cpulist|core|merom|model=Core 2 Duo L7400|l2=4|fsb=667|mult=9 |vmin=0.9 |vmax=1.2|tdp=17|sock=FCBGA6|date=Q1 2007|price=$316 |sspec1=SL9SM|step1=B2|part1=LE80537LF0214M |sspec2=SLGFX|step2=G2}} {{cpulist|core|merom|model=Core 2 Duo L7500|l2=4|fsb=800|mult=8 |vmin=0.9 |vmax=1.1|tdp=17|sock=FCBGA6|date=May 2007|price=$316 |sspec1=SLA3R|step1=E1|part1=LE80537LG0254M |sspec2=SLAET|step2=G0}} {{cpulist|core|merom|model=Core 2 Duo SP7500<ref name="intel.com">{{cite web|url=https://www.intel.com/content/www/us/en/support/products/873/processors.html|title=Support for Intel Processors|website=Intel|access-date=26 June 2019}}</ref>{{failed verification|date=October 2018}}<ref>{{cite web|url=http://www.anandtech.com/mac/showdoc.aspx?i=3203|title=The MacBook Air CPU Mystery: More Details Revealed|work=[[AnandTech]]|date=2008-01-17|first1=Anand Lai|last1=Shimpi|access-date=2018-10-27}}</ref> |l2=4|fsb=800|mult=8 |vmin=1.0 |vmax=1.25|tdp=20|sock=μFC-BGA 956|price=OEM |sspec1=SLAT2|step1=|part1=SY80537GG0254M |sspec2=SLAEV|step2=|noanchor=yes}} {{cpulist|core|merom|model=Core 2 Duo L7700|l2=4|fsb=800|mult=9 |vmin=0.9 |vmax=1.1|tdp=17|sock=FCBGA6|date=September 2007|price=$316 |sspec1=SLAES|step1=G0|part1=LE80537LG0334M}} {{cpulist|core|merom|model=Core 2 Duo SP7700<ref name="intel.com"/>{{failed verification|date=October 2018}} |l2=4|fsb=800|mult=9 |vmin=1.0 |vmax=1.25|tdp=20|sock=μFC-BGA 956|price=OEM |sspec1=SLALQ|sspec2=SLALR|sspec3=SLASZ|step1=|part1=SY80537GG0334M|part2=SY80537GG0334ML|noanchor=yes}} {{end}} =====[[Merom (microprocessor)#Merom-2M|"Merom-2M"]] (ultra-low-voltage, 65 nm)===== *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]]'' * [[Die (integrated circuit)|Die]] size: 111&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 65nm process|L2, M0]] {{cpulist|core|head}} {{cpulist|core|merom|model=Core 2 Duo U7500|l2=2|fsb=533|mult=8 |vmin=0.8 |vmax=0.975|tdp=10|sock=FCBGA6 (Socket&nbsp;M)|date=April 2007|price=$262|links=1 |sspec1=SLA2V|step1=L2|part1=LE80537UE0042M |sspec2=SLAUT|step2=M0}} {{cpulist|core|merom|model=Core 2 Duo U7500|l2=2|fsb=533|mult=8 |vmin=0.8 |vmax=0.975|tdp=10|sock=FCBGA6 (Socket&nbsp;P)|date=February 2008|price=$262 |sspec1=SLV3X|step1=M0|part1=LE80537UE0042ML}} {{cpulist|core|merom|model=Core 2 Duo U7600|l2=2|fsb=533|mult=9 |vmin=0.8 |vmax=0.975|tdp=10|sock=FCBGA6 (Socket&nbsp;M)|date=April 2007|price=$289 |sspec1=SLA2U|step1=L2|part1=LE80537UE0092M |sspec2=SLAUS|step2=M0}} {{cpulist|core|merom|model=Core 2 Duo U7600|l2=2|fsb=533|mult=9 |vmin=0.8 |vmax=0.975|tdp=10|sock=FCBGA6 (Socket&nbsp;P)|date=April 2007|price=$289 |sspec1=SLV3W|step1=M0|part1=LE80537UE0092ML}} {{cpulist|core|merom|model=Core 2 Duo U7700 |l2=2|fsb=533|mult=10 |vmin=0.8 |vmax=0.975|tdp=10|sock=FCBGA6 (Socket&nbsp;M)|date=December 2007|price=$289 |sspec1=SLA6X|step1=L2|part1=LE80537UE0142M |sspec2=SLAUR|step2=M0}} {{cpulist|core|merom|model=Core 2 Duo U7700|l2=2|fsb=533|mult=10 |vmin=0.8 |vmax=0.975|tdp=10|sock=FCBGA6 (Socket&nbsp;P)|date=February 2008|price=$289 |sspec1=SLV3V|step1=M0|part1=LE80537UE0142ML}} {{end}} ====="[[Penryn (microprocessor)#Penryn|Penryn]]" (Apple iMac specific, 45 nm)===== * [[Die (integrated circuit)|Die]] size: 107&nbsp;mm² * The 2008 20" iMac used the E8135 and E8335 CPUs at a lower than specified clock frequency, explaining why the same model is used at different frequencies. This list shows the frequencies used by Apple. * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|C0, E0]] {{cpulist|core|head}} {{cpulist|core|penryn|model=Core 2 Duo E8135|fsb=1066|l2=6|mult=9|tdp=44|sock=[[Socket P]]|date=April 2008| sspec1=SLAQA|step1=C0|part1=FF80576E8135|part2=FF80576GH0676M|links=1}} {{cpulist|core|penryn|model=Core 2 Duo E8135|fsb=1066|l2=6|mult=10|tdp=44|sock=Socket P|date=March 2009| sspec1=SLG8W|step1=E0|part1=AW80576GH0676M|part2=AW80576E8135}} {{cpulist|core|penryn|model=Core 2 Duo E8135|fsb=1066|l2=6|mult=10|tdp=35|sock=Socket P|date=March 2009| sspec1=SLGED|step1=E0|part1=AW80576GH0676M}} {{cpulist|core|penryn|model=Core 2 Duo E8235|fsb=1066|l2=6|mult=10.5|tdp=44|sock=Socket P|date=April 2008| sspec1=SLAQB|step1=C0|part1=FF80576GH0726M}} {{cpulist|core|penryn|model=Core 2 Duo E8335|fsb=1066|l2=6|mult=11|tdp=44|sock=Socket P|date=April 2008| sspec1=SLAQC|step1=C0|part1=FF80576GH0776M}} {{cpulist|core|penryn|model=Core 2 Duo E8335|fsb=1066|l2=6|mult=11 |vmin=1.0500 |vmax=1.2250|tdp=35|sock=Socket P|date=March 2009| sspec1=SLGEB|step1=E0|part1=AW80576GH0776M}} {{cpulist|core|penryn|model=Core 2 Duo E8435|fsb=1066|l2=6|mult=11.5 |vmin=1.0500 |vmax=1.2375|tdp=55|sock=Socket P|date=April 2008| sspec1=SLAQD|step1=C0|part1=FF80576GH0836M}} {{cpulist|core|penryn|model=Core 2 Duo E8435|fsb=1066|l2=6|mult=11.5|tdp=44|sock=Socket P|date=March 2009| sspec1=SLGEA|step1=E0|part1=AW80576GH0836M}} {{end}} =====[[Penryn (microprocessor)#Penryn|"Penryn"]], [[Penryn (microprocessor)#Penryn-3M|"Penryn-3M]]" (standard-voltage, 45 nm) {{anchor|"Penryn-2M" (standard-voltage, 45 nm)|"Penryn-3M" (standard-voltage, 45 nm)|"Penryn" (standard-voltage, 45 nm)|Penryn-2M really does not exist}} ===== *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]].1, Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), Intel Dynamic Acceleration (IDA)''<ref name="T6xxx">{{cite web |url=http://ark.intel.com/cpu.aspx?groupID=40479&code=t6400 |publisher=Intel Corporation |access-date=6 February 2009 |title=Intel Core2 Duo Processor T6400 (2M Cache, 2.00&nbsp;GHz, 800&nbsp;MHz FSB) |url-status=dead |archive-url=https://web.archive.org/web/20090212072827/http://ark.intel.com/cpu.aspx?groupID=40479&code=t6400 |archive-date=12 February 2009 }}</ref> * T6570,<ref name="T6570">{{cite web |url=http://ark.intel.com/Product.aspx?id=42841 |publisher=Intel Corporation |access-date=20 March 2010 |title=Intel Core2 Duo Processor T6570 (2M Cache, 2.10&nbsp;GHz, 800&nbsp;MHz FSB)}}</ref> T6670, all T8xxx and T9xxx models support [[Intel VT-x]] * All T9xxx models support [[Trusted Execution Technology]] (TXT) * T6xxx models are Penryn-3M processors with 1 MB L2 cache disabled. Note that models T8100, T8300, T9300, T9500 are Penryn processors designed for Santa Rosa Refresh platforms with maximum FSB of 800 MT/s, whereas the rest of the Penryn processors are designed for Montevina platforms that can go up to maximum FSB of 1066 MT/s. Penryn processors support Dynamic Front Side Bus Throttling between 400–800MT/s. * [[Die (integrated circuit)|Die]] size: 107&nbsp;mm² (Penryn), 82&nbsp;mm² (Penryn-3M) * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|C0, E0]] (Penryn) [[Intel Core (microarchitecture)#Steppings using 45nm process|M0, R0]] (Penryn-3M)<ref name="T6xxx" /> {{cpulist|core|head}} {{cpulist|core|penryn|model=Core 2 Duo T6400|l2=2|fsb=800 |mult=10 |vmin=1.00 |vmax=1.250 |tdp=35 |sock1=[[Socket P]] |date=January 2009 |price=OEM |links=1 |sspec1=SLGJ4|step1=R0 |part1=AW80577GG0412MA}} {{cpulist|core|penryn|model=Core 2 Duo T6500|l2=2|fsb=800 |mult=10.5 |vmin=1.00 |vmax=1.250 |tdp=35 |sock=Socket P |date=January 2009 |price=OEM |sspec1=SLGF4|step1=R0 |part1=AW80577GG0452ML |part2=AW80577GG0452MA}} {{cpulist|core|penryn|model=Core 2 Duo T6570|l2=2|fsb=800 |mult=10.5 |vmin=1.00 |vmax=1.250 |tdp=35 |sock=Socket P |date=Q3 2009 |price=OEM |sspec1=SLGLL|step1=R0 |part1=AW80577GG0452MH}} {{cpulist|core|penryn|model=Core 2 Duo T6600|l2=2|fsb=800 |mult=11 |vmin=1.00 |vmax=1.250 |tdp=35 |sock=Socket P |date=January 2009 |price=OEM |sspec1=SLGJ9|step1=R0 |part1=AW80577GG0492MA |sspec2=SLGF5|step2=R0 |part2=AW80577GG0492ML}} {{cpulist|core|penryn|model=Core 2 Duo T6670|l2=2|fsb=800 |mult=11 |vmin=1.00 |vmax=1.250 |tdp=35 |sock=Socket P |date=Q3 2009 |price=OEM |sspec1=SLGLK|step1=R0|part1=AW80577GG0492MH |sspec2=SLGLJ|step2=R0}} {{cpulist|core|penryn|model=Core 2 Duo T6900|l2=2|fsb=800 |mult=12.5 |vmin=1.00 |vmax=1.250 |tdp=35 |sock=Socket P |date=?|price=OEM |sspec1=SLGHZ|step1=?|part1=AW80577GG0602MA}} {{cpulist|core|penryn|model=Core 2 Duo T6970|l2=2|fsb=800 |mult=12.5 |vmin=1.00 |vmax=1.250 |tdp=35 |sock=Socket P |date=?|price=OEM |sspec1=SLGLJ|step1=R0|part1=AW80577GG0602MH}} {{cpulist|core|penryn|model=Core 2 Duo T8100|l2=3|fsb=800 |mult=10.5 |vmin=1.000 |vmax=1.250 |tdp=35 |sock=Socket P |date=January 2008 |price=$209 |sspec1=SLAP9|step1=M0 |part1=FF80577GG0453M (M0) |sspec2=SLAVJ|step2=M0 |part2=FF80577GG0453MN |sspec3=SLAYP|step3=M0 |sspec4=SLAYZ|step4=C0 |part3=FF80576GG0453M (C0) |sspec5=SLAUU|step5=C0 |part4=BX80577T8100}} {{cpulist|core|penryn|model=Core 2 Duo T8100|l2=3|fsb=800 |mult=10.5 |vmin=1.000 |vmax=1.250 |tdp=35 |sock=FCBGA6 |date=January 2008 |price=$209 |sspec1=SLAPS|step1=M0|part1=EC80577GG0453M (M0) |sspec2=SLAXG|step2=M0 |sspec3=SLAPT|step3=C0|part3=EC80576GG0453M (C0) |sspec4=SLAZD|step4=C0}} {{cpulist|core|penryn|model=Core 2 Duo T8300|l2=3|fsb=800 |mult=12 |vmin=1.00 |vmax=1.250 |tdp=35 |sock=Socket P |date=January 2008 |price=$241 |sspec1=SLAPA|step1=M0|part1=FF80577GG0563M |sspec2=SLAYQ|step2=M0 |part2=BX80577T8300}} {{cpulist|core|penryn|model=Core 2 Duo T8300|l2=3|fsb=800 |mult=12 |vmin=1.00 |vmax=1.250 |tdp=35 |sock=FCBGA6 |date=January 2008 |price=$241 |sspec1=SLAPR|step1=M0|part1=EC80577GG0563M (M0) |sspec2=SLAPU|step2=C0|part2=EC80576GG0563M (C0) |sspec3=SLAZC|step3=C0}} {{cpulist|core|penryn|model=Core 2 Duo T9300|l2=6|fsb=800 |mult=12.5 |vmin=1.000 |vmax=1.250 |tdp=35 |sock=Socket P |date=January 2008 |price=$316 |sspec1=SLAQG|step1=C0|part1=FF80576GG0606M |sspec2=SLAYY|step2=C0}} {{cpulist|core|penryn|model=Core 2 Duo T9300|l2=6|fsb=800 |mult=12.5 |vmin=1.000 |vmax=1.250 |tdp=35 |sock=FCBGA6 |date=January 2008 |price=$316 |sspec1=SLAPV|step1=C0|part1=EC80576GG0606M |sspec2=SLAZB|step2=C0}} {{cpulist|core|penryn|model=Core 2 Duo T9400|l2=6|fsb=1066|mult= 9.5 |vmin=1.050 |vmax=1.162 |tdp=35 |sock=Socket P |date=July 2008 |price=$316 |sspec1=SLB46|step1=C0|part1=AW80576GH0616M |sspec2=SLB4D|step2=C0 |sspec3=SLGE5|step3=E0}} {{cpulist|core|penryn|model=Core 2 Duo T9400|l2=6|fsb=1066|mult= 9.5 |vmin=1.050 |vmax=1.162 |tdp=35 |sock=FCBGA6 |date=July 2008 |price=$316 |sspec1=SL3BX|step1=C0|part1=AV80576GH0616M |sspec2=SLGEK|step2=E0}} {{cpulist|core|penryn|model=Core 2 Duo T9500|l2=6|fsb=800 |mult=13 |vmin=1.000 |vmax=1.250 |tdp=35 |sock=Socket P |date=January 2008 |price=$530 |sspec1=SLAQH|step1=C0|part1=FF80576GG0646M |sspec2=SLAYX|step2=C0}} {{cpulist|core|penryn|model=Core 2 Duo T9500|l2=6|fsb=800 |mult=13 |vmin=1.000 |vmax=1.250 |tdp=35 |sock=FCBGA6 |date=January 2008 |price=$530 |sspec1=SLAPW|step1=C0|part1=EC80576GG0646M |sspec2=SLAZA|step2=C0 |sspec3=SLB49|step3=C0 |sspec4=SLB4A|step4=C0 |sspecs=<br>SLB4B (C0)<br>SLB3BW (C0)|part2=AV80576SH0616M}} {{cpulist|core|penryn|model=Core 2 Duo T9550|l2=6|fsb=1066|mult=10 |vmin=1.050 |vmax=1.212 |tdp=35 |sock=Socket P |date=December 2008 |price=$316 |sspec1=SLGE4|step1=E0|part1=AW80576GH0676MG}} {{cpulist|core|penryn|model=Core 2 Duo T9550|l2=6|fsb=1066|mult=10 |vmin=1.050 |vmax=1.212 |tdp=35 |sock=FCBGA6 |date=December 2008 |price=$316 |sspec1=SLGEL|step1=E0|part1=AV80576GH0676MG}} {{cpulist|core|penryn|model=Core 2 Duo T9600|l2=6|fsb=1066|mult=10.5 |vmin=1.050 |vmax=1.162 |tdp=35 |sock=Socket P |date=July 2008 |price=$530 |sspec1=SLB47|step1=C0|part1=AW80576GH0726M |sspec2=SLG8N|step2=C0 |sspec3=SLG9F|step3=E0}} {{cpulist|core|penryn|model=Core 2 Duo T9600|l2=6|fsb=1066|mult=10.5 |vmin=1.050 |vmax=1.162 |tdp=35 |sock=FCBGA6 |date=July 2008 |price=$530 |sspec1=SLB43|step1=C0|part1=AV80576GH0726M |sspec2=SLGEM|step2=E0}} {{cpulist|core|penryn|model=Core 2 Duo T9800|l2=6|fsb=1066|mult=11 |vmin=1.050 |vmax=1.212 |tdp=35 |sock=Socket P |date=December 2008 |price=$530 |sspec1=SLGES|step1=E0|part1=AW80576GH0776MG}} {{cpulist|core|penryn|model=Core 2 Duo T9800|l2=6|fsb=1066|mult=11 |vmin=1.050 |vmax=1.212 |tdp=35 |sock=FCBGA6 |date=December 2008 |price=$530 |sspec1=SLGEP|step1=E0|part1=AV80576GH0776MG}} {{cpulist|core|penryn|model=Core 2 Duo T9900|l2=6|fsb=1066|mult=11.5 |vmin=1.050 |vmax=1.2125|tdp=35 |sock=Socket P |date=April 2009 |price=$530 |sspec1=SLGEE|step1=E0|part1=AW80576GH0836MG}} {{cpulist|core|penryn|model=Core 2 Duo T9900|l2=6|fsb=1066|mult=11.5 |vmin=1.050 |vmax=1.2125|tdp=35 |sock=FCBGA6 |date=April 2009 |price=$530 |sspec1=SLGKH|step1=E0|part1=AV80576GH0836MG}} {{end}} =====[[Penryn (microprocessor)#Penryn|"Penryn"]], [[Penryn (microprocessor)#Penryn-3M|"Penryn-3M"]] (medium-voltage, 45 nm) {{anchor|"Penryn" (medium-voltage, 45 nm)|"Penryn-3M" (medium-voltage, 45 nm)}} ===== * All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]].1, Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]] (except the non-Mac P7350, P7450),<ref name="P7350">{{cite web |url=http://processorfinder.intel.com/details.aspx?sSpec=SLB53 |title=Intel® Core™2 Duo Mobile Processor P7350 - SLB53 |access-date=2009-02-09 |archive-url=https://web.archive.org/web/20090205000256/http://processorfinder.intel.com/details.aspx?sSpec=SLB53 |archive-date=2009-02-05 |url-status=dead }}</ref><ref name="P7450">{{cite web |url=http://processorfinder.intel.com/Details.aspx?sSpec=SLB54 |title=Intel® Core™2 Duo Mobile Processor P7450 - SLB54 |access-date=2009-05-02 |archive-url=https://web.archive.org/web/20090516173831/http://processorfinder.intel.com/details.aspx?sSpec=SLB54 |archive-date=2009-05-16 |url-status=dead }}</ref><ref name="P7550">{{cite web|url=https://ark.intel.com/content/www/us/en/ark.html|title=Intel product specifications|website=ark.intel.com|access-date=26 June 2019}}</ref> [[Trusted Execution Technology]] (TXT), Intel Dynamic Acceleration (IDA)'' * Select [[Apple Inc.|Apple]] subsets of P7000 series processors support Intel VT-x.<ref>{{cite web |author=Eric Tung |title=Re: Does VMware Fusion require a CPU supporting Intel VT-x? |url=http://communities.vmware.com/thread/199449#1198447 |access-date=18 April 2009 |date=13 March 2009}}</ref> * Penryn and Penryn-3M processors support Dynamic Front Side Bus Throttling between 533–1066MT/s. * [[Die (integrated circuit)|Die]] size: 107&nbsp;mm² (Penryn), 82&nbsp;mm² (Penryn-3M) * Package size: 35&nbsp;mm × 35&nbsp;mm * Transistors: 410 million <ref name="Techarp20151218">{{cite web|publisher=Techarp.com|title=Tech ARP - Mobile CPU Comparison Guide Rev. 12.3 |url=http://www.techarp.com/showarticle.aspx?artno=347&pgno=8|access-date=Dec 18, 2015}}</ref> * [[Stepping level|Steppings]]: ([[Intel Core (microarchitecture)#Steppings using 45nm process|Core microarchitecture 45nm steppings]]) **[[Intel Core (microarchitecture)#Steppings using 45nm process|C0, E0]] (Penryn) **[[Intel Core (microarchitecture)#Steppings using 45nm process|M0, R0]] (Penryn-3M) **stepping C0/M0 is only used in the Intel Mobile 965 Express ([[Centrino#Santa Rosa platform (2007)|Santa Rosa refresh]]) platform **stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and supports the later Intel Mobile 4 Express ([[Centrino#Montevina platform (2008)|Montevina]]) platform {{cpulist|core|head}} {{cpulist|core|penryn|model=Core 2 Duo P7350 |sspec1=SLB44 |step1=C0 |sspec2=SLB53 |step2=M0 |freq=2000 |l2=3 |fsb=1066 |mult=7.5 |vmin=1.00 |vmax=1.250 |tdp=25 |sock=Socket P |date=Mid 2008 |part1=AW80576GH0413M |part2=AW80577SH0413M |price=OEM |links=1}} {{cpulist|core|penryn|model=Core 2 Duo P7350 |sspec1=SLG8E |step1=C0 |sspec2=SLGE3 |step2=R0 |freq=2000 |l2=3 |fsb=1066 |mult=7.5 |vmin=1.00 |vmax=1.250 |tdp=25 |sock=FC-BGA478 |date=Mid 2008 |price=OEM |links=1}} {{cpulist|core|penryn|model=Core 2 Duo P7370 |2000&nbsp;MHz |l2=3 |fsb=1066 |mult=7.5 |vmin=1.00 |vmax=1.250 |tdp=25 |Socket P |date=January 2009 |price=OEM| part1=AW80577SH0413M |sspec1=SLG8X |step1=R0 |sspec2=SLGF9 |step2=R0 |part2=AW80577SH0413ML}} {{cpulist|core|penryn|model=Core 2 Duo P7450 |2133&nbsp;MHz |l2=3 |fsb=1066 |mult=8 |vmin=1.00 |vmax=1.250 |tdp=25 |sock=Socket P |date=January 2009 |price=OEM| sspec1=SLB45 |step1=C0 |sspec2=SLGF7 |step2=R0 |sspec3=SLB54 |step3=M0 |sspec4=SLB56 |step4=M0 |part1=AW80577SH0463M |part2=AW80576GH0463M (C0)}} {{cpulist|core|penryn|model=Core 2 Duo P7450 |2133&nbsp;MHz |l2=3 |fsb=1066 |mult=8 |vmin=1.00 |vmax=1.250 |tdp=25 |sock=FC-BGA478 |date=January 2009 |price=OEM| sspec2=SLGFF |step2=C0 |part2=AW80577P7450M (C0)}} {{cpulist|core|penryn|model=Core 2 Duo P7550 |2266&nbsp;MHz |l2=3 |fsb=1066 |mult=8.5 |vmin=1.00 |vmax=1.250 |tdp=25 |Socket P |date=June 2009 |price=OEM| sspec1=SLGF8 |step1=R0 |part1=AW80577SH0513MA}} {{cpulist|core|penryn|model=Core 2 Duo P7570 |2266&nbsp;MHz |l2=3 |fsb=1066 |mult=8.5 |vmin=1.00 |vmax=1.250 |tdp=25 |Socket P |date=Q3 2009 |price=OEM| sspec1=SLGLW |step1=R0 |part1=AW80577SH0513ML}} {{cpulist|core|penryn|model=Core 2 Duo P8400 |2266&nbsp;MHz |l2=3 |fsb=1066 |mult=8.5 |vmin=1.00 |vmax=1.250 |tdp=25 |sock=Socket P |date=13 June 2008<ref>{{cite web|url=http://www.hardware.info/en-US/productdb/bGRkapiUmJjKY8g/viewproduct/Intel_Core_2_Duo_P8400/|title=[ Hardware.Info ] - Intel Core 2 Duo P8400 [BX80577P8400]|date=2 September 2008|access-date=26 June 2019|archive-url=https://web.archive.org/web/20080902235441/http://www.hardware.info/en-US/productdb/bGRkapiUmJjKY8g/viewproduct/Intel_Core_2_Duo_P8400/|archive-date=2008-09-02}}</ref> |price=$209| sspec1=SLB3R |step1=M0 |sspec2=SLB3Q |step2=M0 |sspec3=SLB52 |step3=M0 |sspec= * SLG8Z&nbsp;(M0) * SLGCC&nbsp;(R0) * SLGCQ&nbsp;(R0) * SLGCF&nbsp;(R0) * SLGFC&nbsp;(R0) * SLGCL&nbsp;(R0) |part1=AW80577SH0513M|part2=AW80577SH0513MN|part3=BX80577P8400}} {{cpulist|core|penryn|model=Core 2 Duo P8400 |2266&nbsp;MHz |l2=3 |fsb=1066 |mult=8.5 |vmin=1.00 |vmax=1.250 |tdp=25 |sock=FC-BGA478 |date=June 2008 |price=$209 | sspec1=SLB4M|step1=M0|part1=AV80577SH0513M}} {{cpulist|core|penryn|model=Core 2 Duo P8600 |2400&nbsp;MHz |l2=3 |fsb=1066 |mult=9 |vmin=1.00 |vmax=1.250 |tdp=25 |date=June 2008<ref>{{cite web|url=http://www.hardware.info/en-US/productdb/bGRkapiUmJjKZMg/viewproductprices/Intel_Core_2_Duo_P8600_BX80577P8600|title=[ Hardware.Info ] - Intel Core 2 Duo P8600 [BX80577P8600]|date=8 February 2009|access-date=26 June 2019|archive-url=https://web.archive.org/web/20090208032055/http://www.hardware.info/en-US/productdb/bGRkapiUmJjKZMg/viewproductprices/Intel_Core_2_Duo_P8600_BX80577P8600|archive-date=2009-02-08}}</ref> |price=$241 | sspec1=SLB3S |step1=M0 |sspec2=SLGA4 |step2=M0 |sspec3=SLGFD |step3=R0 |part1=AW80577SH0563M|part2=BX80577P8600}} {{cpulist|core|penryn|model=Core 2 Duo P8600 |2400&nbsp;MHz |l2=3 |fsb=1066 |mult=9 |vmin=1.00 |vmax=1.250 |tdp=25 |date=June 2008 |price=$241 | sspec1=SLB4N |step1=M0|sspec2=SLGDZ |step2=R0 |sock=FC-BGA478 |part1=AV80577SH0563M}} {{cpulist|core|penryn|model=Core 2 Duo P8700 |2533&nbsp;MHz |l2=3 |fsb=1066 |mult=9.5 |vmin=1.00 |vmax=1.250 |tdp=25 |sock=Socket P |date=December 2008 |price=$241| sspec1=SLGFE |step1=R0 |part1=AW80577SH0613MG |part2=BX80577P8700}} {{cpulist|core|penryn|model=Core 2 Duo P8700 |2533&nbsp;MHz |l2=3 |fsb=1066 |mult=9.5 |vmin=1.00 |vmax=1.250 |tdp=25 |sock=FC-BGA478 |date=December 2008 |price=$241| sspec1=SLGFG |step1=R0 |part1=AV80577SH0613MG}} {{cpulist|core|penryn|model=Core 2 Duo P8800 |2667&nbsp;MHz |l2=3 |fsb=1066 |mult=10 |vmin=1.00 |vmax=1.250 |tdp=25 |sock=Socket P |date=Q2 2009 |price=$241| sspec1=SLGLR |step1=R0 |part1=AW80577SH0673MG |part2=BX80577P8800}} {{cpulist|core|penryn|model=Core 2 Duo P8800 |2667&nbsp;MHz |l2=3 |fsb=1066 |mult=10 |vmin=1.00 |vmax=1.250 |tdp=25 |sock=FC-BGA478 |date=Q2 2009 |price=$241| sspec1=SLGLA |step1=E0 |part1=AV80577SH0673MG}} {{cpulist|core|penryn|model=Core 2 Duo P9500 |2533&nbsp;MHz |l2=6 |fsb=1066 |mult=9.5 |vmin=1.05 |vmax=1.162 |tdp=25 |sock=Socket P |date=July 2008|price=$348| sspec1=SLB4E |step1=C0 |sspec2=SLGE8|step2=E0|part1=AW80576SH0616M |part2=AV80576SH0616M}} {{cpulist|core|penryn|model=Core 2 Duo P9600 |2667&nbsp;MHz |l2=6 |fsb=1066 |mult=10 |vmin=1.05 |vmax=1.212 |tdp=25 |Socket P |date=December 2008 |price=$348| sspec1=SLGE6 |step1=E0 |part1=AW80576SH0676MG}} {{cpulist|core|penryn|model=Core 2 Duo P9700 |2800&nbsp;MHz |l2=6 |fsb=1066 |mult=10.5 |vmin=1.012 |vmax=1.175 |tdp=28 |Socket P |date=June 2009 |price=$348| sspec1=SLGQS |step1=E0 |part1=AW80576SH0726MG}} {{end}} =====[[Penryn (microprocessor)#Penryn|"Penryn"]] (medium-voltage, 45 nm, Small Form Factor)===== * All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]].1, Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]], [[Trusted Execution Technology]] (TXT), Intel Dynamic Acceleration (IDA)'' * [[Die (integrated circuit)|Die]] size: 107&nbsp;mm² * Package size: 22&nbsp;mm × 22&nbsp;mm * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|C0]], [[Intel Core (microarchitecture)#Steppings using 45nm process|E0]] {{cpulist|core|head}} {{cpulist|core|penrynulv|model=Core 2 Duo SP9300|sspec1=SLB63|step1=C0|<!--sspec2=SLGAF|step2=E0|-->freq=2266|l2=6|fsb=1066|mult=8.5 |vmin=0.900 |vmax=1.225|tdp=25|date=July 2008|part1=AV80576SH0516M|price=$284|links=1}} {{cpulist|core|penrynulv|model=Core 2 Duo SP9400|sspec1=SLB64|step1=C0|sspec2=SLGHG|step2=C0|freq=2400|l2=6|fsb=1066|mult=9 |vmin=0.900 |vmax=1.225|tdp=25|date=July 2008|part1=AV80576SH0566M|price=$284|sspec3=SLGAA|step3=E0}} {{cpulist|core|penrynulv|model=Core 2 Duo SP9600|<!--sspec1=SLGER|step1=C0|-->sspec2=SLGER|step2=E0|freq=2533|l2=6|fsb=1066|mult=9.5 |vmin=0.900 |vmax=1.225|tdp=25|date=Q1 2009|part1=AV80576SH0516M|part2=AV80576SH0616M|price=$316}} {{end}} =====[[Penryn (microprocessor)#Penryn|"Penryn"]] (low-voltage, 45 nm, Small Form Factor)===== * All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]].1, Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]], [[Trusted Execution Technology]] (TXT), Intel Dynamic Acceleration (IDA)'' * [[Die (integrated circuit)|Die]] size: 107&nbsp;mm² * Package size: 22&nbsp;mm × 22&nbsp;mm * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|C0]], [[Intel Core (microarchitecture)#Steppings using 45nm process|E0]] {{cpulist|core|head}} {{cpulist|core|penrynulv|model=Core 2 Duo SL9300|l2=6|fsb=1066|mult=6 |vmin=1.050 |vmax=1.150|tdp=17|date=September 2008|price=$284| sspec1=SLB65|step1=C0|sspec2=SLGHC|step2=C0|sspec3=SLGAG|step3=E0|part1=AV80576LH0256M|links=1}} {{cpulist|core|penrynulv|model=Core 2 Duo SL9380|l2=6|fsb=800 |mult=9 |vmin=1.050 |vmax=1.150|tdp=17|date=September 2008|price=$316| sspec1=SLGA2|step1=C0|sspec2=SLGAD|step2=E0|part1=AV80576LG0336M}} {{cpulist|core|penrynulv|model=Core 2 Duo SL9400|l2=6|fsb=1066|mult=7 |vmin=1.050 |vmax=1.150|tdp=17|date=September 2008|price=$316| sspec1=SLB66|step1=C0|sspec2=SLGHD|step2=C0|sspec3=SLGAB|step3=E0|part1=AV80576LH0366M}} {{cpulist|core|penrynulv|model=Core 2 Duo SL9600|l2=6|fsb=1066|mult=8 |vmin=1.050 |vmax=1.150|tdp=17|date=Q1'09 |price=$316| sspec1=SLGEQ|step1=E0|part1=AV80576LH0466M}} {{end}} =====[[Penryn (microprocessor)#Penryn-3M|"Penryn-3M"]] (ultra-low-voltage, 45 nm, Small Form Factor)===== * All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]].1, Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]], [[Trusted Execution Technology]] (TXT) (except SU7300), Intel Dynamic Acceleration (IDA)'' * [[Die (integrated circuit)|Die]] size: 107&nbsp;mm² * Package size: 22&nbsp;mm × 22&nbsp;mm * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|M0]], [[Intel Core (microarchitecture)#Steppings using 45nm process|R0]] {{cpulist|core|head}} {{cpulist|core|penrynulv|model=Core 2 Duo SU7300|l2=3|mult=6.5|date=September 2009|fsb=800|price=$289 |vmin=1.05 |vmax=1.15|links=1 |sspec1=SLGS6|step1=R0|sspec2=SLGYV|step2=R0|part1=AV80577UG0133M|part2=AV80577UG0133ML}} <!--{{cpulist|core|penrynulv|model=Core 2 Duo SU7800|l2=3|mult=7 |date=September 2009|fsb=800|price=$289 |part1=AV80577UG0173M|sspec1=SLGS5|step1=R0}}--> {{cpulist|core|penrynulv|model=Core 2 Duo SU9300|l2=3|mult=6 |date=September 2008|fsb=800|price=$262 |vmin=1.05 |vmax=1.15 |part1=AV80577UG0093M|sspec1=SLB5Q|step1=M0|sspec2=SLGAL|step2=R0}} {{cpulist|core|penrynulv|model=Core 2 Duo SU9400|l2=3|mult=7 |date=September 2008|fsb=800|price=$289 |vmin=1.05 |vmax=1.15 |part1=AV80577UG0173M|sspec1=SLB5V|step1=M0|sspec2=SLGHN|step2=M0|sspec3=SLGAK|step3=R0}} {{cpulist|core|penrynulv|model=Core 2 Duo SU9600|l2=3|mult=8 |date=Q1 2009 |fsb=800|price=$289 |vmin=1.05 |vmax=1.15 |part1=AV80577UG0253M|sspec1=SLGEX|step1=R0|sspec2=SLGFN|step2=R0}} {{end}} ====Core 2 Extreme==== ===== [[Merom (microprocessor)#Merom XE|"Merom XE"]] (65 nm) {{anchor|"Merom XE" (standard-voltage, 65 nm)}} ===== ''These models feature an [[CPU locking|unlocked]] [[clock multiplier]]'' *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]], [[Trusted Execution Technology]] (TXT), Intel Dynamic Front Side Bus Frequency Switching'' * Merom XE processors support Dynamic Front Side Bus Throttling between 400 and 800 MT/s. * [[Die (integrated circuit)|Die]] size: 143&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 65nm process|E1, G0]] {{cpulist|core|head}} {{cpulist|core|merom|model=Core 2 Extreme X7800|l2=4|fsb=800|mult=13 |vmin=1.0375 |vmax=1.3|tdp=44|sock=[[Socket P]]|date=July 2007|price=$851|links=1 |sspec1=SLA6Z|step1=E1|part1=LF80537GG0644M}} {{cpulist|core|merom|model=Core 2 Extreme X7900|l2=4|fsb=800|mult=14 |vmin=1.0375 |vmax=1.3|tdp=44|sock=Socket P|date=August 2007|price=$851 |sspec1=SLA33|step1=E1|part1=LF80537GG0724M |sspec2=SLAF4|step2=G0}} {{end}} ===== [[Penryn (microprocessor)#Penryn-QC|"Penryn XE"]] (45 nm) {{anchor|"Penryn XE" (standard-voltage, 45 nm)}} ===== *These models feature an [[CPU locking|unlocked]] [[clock multiplier]] *All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]].1, Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]], [[Trusted Execution Technology]] (TXT)'' * Penryn XE processors support Dynamic Front Side Bus Throttling between 400–800 MT/s and 533–1066 MT/s. * [[Die (integrated circuit)|Die]] size: 107&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|C0, E0]] {{cpulist|core|head}} {{cpulist|core|penryn|model=Core 2 Extreme X9000|sspec1=SLAQJ|step1=C0|sspec2=SLAZ3|step2=C0|l2=6|fsb=800|mult=14 |vmin=1.062 |vmax=1.150|tdp=44|date=January 2008|part1=FF80576ZG0726M|price=$851|links=1}} {{cpulist|core|penryn|model=Core 2 Extreme X9100|sspec1=SLB48|step1=C0|sspec2=SLG8M|step2=C0|sspec3=SLGE7|step3=E0|l2=6|fsb=1066|mult=11.5 |vmin=1.062 |vmax=1.150|tdp=44|date=July 2008|part1=AW80576GH0836M|price=$851}} {{end}} ===Quad-Core Notebook processors=== ====Core 2 Quad==== =====[[Penryn (microprocessor)#Penryn-QC|"Penryn QC"]] (45 nm) {{anchor|"Penryn QC" (standard-voltage, 45 nm)}} ===== * All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]].1, Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]], [[Trusted Execution Technology]] (TXT)'' * Can throttle the [[front-side bus]] (FSB) anywhere between 533–1066 MT/s as needed. * [[Die (integrated circuit)|Die]] size: 2 × 107&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|E0]] {{cpulist|core|head}} {{cpulist|core|penrynqc|model=Core 2 Quad Q9000|sspec1=SLGEJ|step1=E0|freq=2.00|l2=2 × 3 MB|fsb=1066|mult=7.5 |vmin=1.050 |vmax=1.175|tdp=45|sock=P|date=December 2008|part1=AW80581GH0416M|part2=BX80581Q9000|price=$348|links=1|cores=4}} {{cpulist|core|penrynqc|model=Core 2 Quad Q9100|sspec1=SLB5G|step1=E0|freq=2.26|l2=2 × 6 MB|fsb=1066|mult=8.5 |vmin=1.050 |vmax=1.175|tdp=45|sock=P|date=August 2008|part1=AW80581GH051003|price=$851|cores=4}} {{end}} ====Core 2 Extreme==== =====[[Penryn (microprocessor)#Penryn-QC|"Penryn QC XE"]] (45 nm) {{anchor|"Penryn QC XE" (standard-voltage, 45 nm)}} ===== * This model features an [[CPU locking|unlocked]] [[clock multiplier]] usually manipulated through the systems BIOS however some manufacturers (such as [[Hewlett-Packard|HP]]) do not have this feature enabled on their laptops that use this processor. * All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]].1, Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), [[Intel Active Management Technology]] (iAMT2), [[Intel VT-x]], [[Trusted Execution Technology]] (TXT)'' * Can throttle the [[front-side bus]] (FSB) anywhere between 533 and 1066 MT/s as needed. * Package size: 35&nbsp;mm × 35&nbsp;mm * [[Die (integrated circuit)|Die]] size: 2 × 107&nbsp;mm² * [[Stepping level|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|E0]] {{cpulist|core|head}} {{cpulist|core|penrynqc|model=Core 2 Extreme QX9300|sspec1=SLB5J|step1=E0|freq=2533|l2=2 × 6 [[Mebibyte|MiB]]||fsb=1066|mult=9.5 |vmin=1.050 |vmax=1.175|tdp=45|sock=P|date=August 2008|part1=AW80581ZH061003|price=$1038|links=1|cores=4}} <!-- {{cpulist|core|penrynqc||model=Core 2 Extreme QX9400|sspec1=SLB5K|step1=E0|freq=2667|l2=2 × 6 MiB||fsb=1066|mult=10 |vmin=1.050 |vmax=1.175|tdp=45|sock=P|date=|part1=AW80581ZH067003|price=}} --> {{end}} ==See also== *[[Intel Core]] *[[Intel Core 2]] *[[Intel Core (microarchitecture)]] *[[Penryn (microarchitecture)]] *[[List of Intel Core microprocessors]] *[[List of Intel Core i3 microprocessors]] *[[List of Intel Core i5 microprocessors]] *[[List of Intel Core i7 microprocessors]] *[[List of Intel Core i9 microprocessors]] ==References== {{Reflist|30em}} {{refbegin}} *[https://web.archive.org/web/20100304212004/http://www.reghardware.co.uk/2006/05/23/ati_confirms_intel_allendale/ ATI provides pointer to Intel's 'Allendale'], 23 May 2006 *[https://web.archive.org/web/20060716013939/http://www.theinquirer.net/default.aspx?article=32026 Rumoured prices and specifications for Intel Core 2], 30 May 2006 *[http://www.tgdaily.com/2006/07/24/intel_to_launch_core_2_duo TGDaily indicates leaked release dates],{{dead link |date=April 2018 |bot=InternetArchiveBot |fix-attempted=yes}} 24 July 2006 *[http://digitimes.com/mobos/a20060717PB213.html Intel to unveil five Merom CPUs in July, paper says]{{subscription required}} as re-reported by DigiTimes, 17 July 2006 *[https://web.archive.org/web/20060811230151/http://www.intel.com/pressroom/archive/releases/20060727comp.htm Intel Unveils World's Best Processor],{{dead link|date=October 2018}} 27 July 2006 *[https://web.archive.org/web/20070911160332/http://www.intel.com/pressroom/archive/releases/20070716corp_a.htm?iid=pr1_releasepri_20070716ar Intel Takes Popular Laptops to 'Extreme' with First-Ever Extreme Edition Mobile Processor; Adds New Desktop Chip],{{dead link|date=October 2018}} 16 July 2007 *[http://xtreview.com/addcomment-id-2933-view-Core-2-duo-1333-mhz-stepping.html CORE 2 DUO 1333 MHZ STEPPING], 18 July 2007 {{refend}} ==External links== * [http://qdms.intel.com/MDDS/MDDSView.aspx Search MDDS Database] * [http://ark.intel.com/ Intel ARK Database] *[http://ark.intel.com/sspecqdf.aspx SSPEC/QDF Reference] (Intel) *[http://www.intel.com/products/processor_number] *[http://www.intel.com/design/intarch/core2duo/tech_docs.htm Intel Core 2 Duo Processors Technical Documents] {{Intel processors|core}} {{DEFAULTSORT:List Of Intel Core 2 Microprocessors}} [[Category:Intel x86 microprocessors|*Core 2]] [[Category:Lists of microprocessors|Intel Core 2]]'