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Page ID (page_id) | 3349272 |
Page namespace (page_namespace) | 0 |
Page title without namespace (page_title) | 'Sign extension' |
Full page title (page_prefixedtitle) | 'Sign extension' |
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Action (action) | 'edit' |
Edit summary/reason (summary) | '/* Zero Extension */Fixed typo' |
Old page wikitext, before the edit (old_wikitext) | ''''Sign extension''' is the operation, in [[computer]] [[arithmetic]], of increasing the number of [[bit]]s of a [[binary number]] while preserving the number's [[sign (mathematics)|sign (positive/negative)]] and value. This is done by appending digits to the [[most significant bit|most significant]] side of the number, following a procedure dependent on the particular [[signed number representation]] used.
For example, if six bits are used to represent the number "<code>00 1010</code>" (decimal positive 10) and the sign extend operation increases the [[Word (data type)|word length]] to 16 bits, then the new representation is simply "<code>0000 0000 0000 1010</code>". Thus, both the value and the fact that the value was positive are maintained.
If ten bits are used to represent the value "<code>11 1111 0001</code>" (decimal negative 15) using [[two's complement]], and this is sign extended to 16 bits, the new representation is "<code>1111 1111 1111 0001</code>". Thus, by padding the left side with ones, the negative sign and the value of the original number are maintained.
In the [[Intel]] [[x86 instruction listings|x86 instruction set]], for example, there are two ways of doing sign extension:
* using the instructions <tt>cbw</tt>, <tt>cwd</tt>, <tt>cwde</tt>, and <tt>cdq</tt>: convert byte to word, word to doubleword, word to extended doubleword, and doubleword to quadword, respectively (in the x86 context a byte has 8 bits, a word 16 bits, a doubleword and extended doubleword 32 bits, and a quadword 64 bits);
* using one of the sign extended moves, accomplished by the <tt>movsx</tt> ("move with sign extension") family of instructions.
==Zero Extension==
A similar concept is zero extension. On x64, most instructions that write to the lower 32 bits of the general-purpose registers will zero the upper half of the destination register. For example, the instruction <code>mov eax, 1234</code> will clear the upper 32 bits of the <tt>eax</tt> register.
==References==
* Mano, Morris M.; Kime, Charles R. (2004). ''Logic and Computer Design Fundamentals'' (3rd ed.), pp 453. Pearson Prentice Hall. ISBN 0-13-140539-X.
[[Category:Binary arithmetic]]
[[de:Zweierkomplement#Vorzeichenerweiterung]]
[[ru:Дополнительный_код_(представление_числа)#Расширение_знака]]' |
New page wikitext, after the edit (new_wikitext) | ''''Sign extension''' is the operation, in [[computer]] [[arithmetic]], of increasing the number of [[bit]]s of a [[binary number]] while preserving the number's [[sign (mathematics)|sign (positive/negative)]] and value. This is done by appending digits to the [[most significant bit|most significant]] side of the number, following a procedure dependent on the particular [[signed number representation]] used.
For example, if six bits are used to represent the number "<code>00 1010</code>" (decimal positive 10) and the sign extend operation increases the [[Word (data type)|word length]] to 16 bits, then the new representation is simply "<code>0000 0000 0000 1010</code>". Thus, both the value and the fact that the value was positive are maintained.
If ten bits are used to represent the value "<code>11 1111 0001</code>" (decimal negative 15) using [[two's complement]], and this is sign extended to 16 bits, the new representation is "<code>1111 1111 1111 0001</code>". Thus, by padding the left side with ones, the negative sign and the value of the original number are maintained.
In the [[Intel]] [[x86 instruction listings|x86 instruction set]], for example, there are two ways of doing sign extension:
* using the instructions <tt>cbw</tt>, <tt>cwd</tt>, <tt>cwde</tt>, and <tt>cdq</tt>: convert byte to word, word to doubleword, word to extended doubleword, and doubleword to quadword, respectively (in the x86 context a byte has 8 bits, a word 16 bits, a doubleword and extended doubleword 32 bits, and a quadword 64 bits);
* using one of the sign extended moves, accomplished by the <tt>movsx</tt> ("move with sign extension") family of instructions.
==Zero Extension==
A similar concept is zero extension. On x64, most instructions that write to the lower 32 bits of the general-purpose registers will zero the upper half of the destination register. For example, the instruction <code>mov eax, 1234</code> will clear the upper 32 bits of the <tt>rax</tt> register.
==References==
* Mano, Morris M.; Kime, Charles R. (2004). ''Logic and Computer Design Fundamentals'' (3rd ed.), pp 453. Pearson Prentice Hall. ISBN 0-13-140539-X.
[[Category:Binary arithmetic]]
[[de:Zweierkomplement#Vorzeichenerweiterung]]
[[ru:Дополнительный_код_(представление_числа)#Расширение_знака]]' |
Unified diff of changes made by edit (edit_diff) | '@@ -10,5 +10,5 @@
==Zero Extension==
-A similar concept is zero extension. On x64, most instructions that write to the lower 32 bits of the general-purpose registers will zero the upper half of the destination register. For example, the instruction <code>mov eax, 1234</code> will clear the upper 32 bits of the <tt>eax</tt> register.
+A similar concept is zero extension. On x64, most instructions that write to the lower 32 bits of the general-purpose registers will zero the upper half of the destination register. For example, the instruction <code>mov eax, 1234</code> will clear the upper 32 bits of the <tt>rax</tt> register.
==References==
' |
New page size (new_size) | 2346 |
Old page size (old_size) | 2346 |
Size change in edit (edit_delta) | 0 |
Lines added in edit (added_lines) | [
0 => 'A similar concept is zero extension. On x64, most instructions that write to the lower 32 bits of the general-purpose registers will zero the upper half of the destination register. For example, the instruction <code>mov eax, 1234</code> will clear the upper 32 bits of the <tt>rax</tt> register.'
] |
Lines removed in edit (removed_lines) | [
0 => 'A similar concept is zero extension. On x64, most instructions that write to the lower 32 bits of the general-purpose registers will zero the upper half of the destination register. For example, the instruction <code>mov eax, 1234</code> will clear the upper 32 bits of the <tt>eax</tt> register.'
] |
New page wikitext, pre-save transformed (new_pst) | ''''Sign extension''' is the operation, in [[computer]] [[arithmetic]], of increasing the number of [[bit]]s of a [[binary number]] while preserving the number's [[sign (mathematics)|sign (positive/negative)]] and value. This is done by appending digits to the [[most significant bit|most significant]] side of the number, following a procedure dependent on the particular [[signed number representation]] used.
For example, if six bits are used to represent the number "<code>00 1010</code>" (decimal positive 10) and the sign extend operation increases the [[Word (data type)|word length]] to 16 bits, then the new representation is simply "<code>0000 0000 0000 1010</code>". Thus, both the value and the fact that the value was positive are maintained.
If ten bits are used to represent the value "<code>11 1111 0001</code>" (decimal negative 15) using [[two's complement]], and this is sign extended to 16 bits, the new representation is "<code>1111 1111 1111 0001</code>". Thus, by padding the left side with ones, the negative sign and the value of the original number are maintained.
In the [[Intel]] [[x86 instruction listings|x86 instruction set]], for example, there are two ways of doing sign extension:
* using the instructions <tt>cbw</tt>, <tt>cwd</tt>, <tt>cwde</tt>, and <tt>cdq</tt>: convert byte to word, word to doubleword, word to extended doubleword, and doubleword to quadword, respectively (in the x86 context a byte has 8 bits, a word 16 bits, a doubleword and extended doubleword 32 bits, and a quadword 64 bits);
* using one of the sign extended moves, accomplished by the <tt>movsx</tt> ("move with sign extension") family of instructions.
==Zero Extension==
A similar concept is zero extension. On x64, most instructions that write to the lower 32 bits of the general-purpose registers will zero the upper half of the destination register. For example, the instruction <code>mov eax, 1234</code> will clear the upper 32 bits of the <tt>rax</tt> register.
==References==
* Mano, Morris M.; Kime, Charles R. (2004). ''Logic and Computer Design Fundamentals'' (3rd ed.), pp 453. Pearson Prentice Hall. ISBN 0-13-140539-X.
[[Category:Binary arithmetic]]
[[de:Zweierkomplement#Vorzeichenerweiterung]]
[[ru:Дополнительный_код_(представление_числа)#Расширение_знака]]' |
Whether or not the change was made through a Tor exit node (tor_exit_node) | 0 |
Unix timestamp of change (timestamp) | 1473954994 |
