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'{{Hatnote|For silicon on insulator optical devices, see [[silicon photonics]].}} [[Image:SIMOX processing schematic.svg|thumb|300px|SIMOX process]] '''Silicon on insulator''' ('''SOI''') technology refers to the use of a layered silicon–insulator–silicon [[Substrate (materials science)|substrate]] in place of conventional [[silicon]] substrates in semiconductor manufacturing, especially microelectronics, to reduce [[parasitic capacitance|parasitic device capacitance]], thereby improving performance.<ref name="celler">{{cite journal |last=Celler |first=G. K. |last2=Cristoloveanu |first2=S. |title=Frontiers of silicon-on-insulator |journal=[[Journal of Applied Physics|J Appl Phys]] |volume=93 |issue=9 |pages=4955 |year=2003 |doi=10.1063/1.1558223 |url=http://www.soitec.com/pdf/Frontiers_SOI.pdf}}</ref> SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically [[silicon dioxide]] or [[sapphire]] (these types of devices are called [[silicon on sapphire]], or SOS). The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short channel effects in microelectronics devices.<ref>{{cite book |title=SOI design: analog, memory and digital techniques |first=Andrew |last=Marshall |first2=Sreedhar |last2=Natarajan |year=2002 |location=Boston |publisher=Kluwer |isbn=0792376404 }}</ref> The insulating layer and topmost silicon layer also vary widely with application.<ref>{{cite book |title=Silicon-on-Insulator Technology: Materials to VLSI |first=Jean-Pierre |last=Colinge |publisher=Springer Verlag |year=1991 |location=Berlin |isbn=978-0-7923-9150-0 }}</ref> ==Industry need== [[Image:Smart Cut SOI Wafer Manufacturing Schema.svg|thumb|300px|Smart Cut process]] The implementation of SOI technology is one of several manufacturing strategies employed to allow the continued miniaturization of microelectronic devices, colloquially referred to as "extending [[Moore's Law]]" (or "More Moore", abbreviated "MM"). Reported benefits of SOI technology relative to conventional silicon (bulk [[CMOS]]) processing include:<ref> [http://www.soiconsortium.org/pdf/Consortium_9april09_final.pdf Silicon-on-insulator - SOI technology and ecosystem - Emerging SOI applications] by Horacio Mendez, Executive Director of the SOI Industry Consortium, April 9, 2009</ref> *''Lower parasitic capacitance'' due to isolation from the bulk silicon, which improves power consumption at matched performance. *''Resistance to [[latchup]]'' due to complete isolation of the n- and p-well structures. *Higher performance at equivalent [[IC power-supply pin|VDD]]. Can work at low VDD's.<ref>http://www.infotech-enterprises.com/fileadmin/infotech-enterprises.com/assets/downloads/White_Papers/Infotech_SOI_Paper_Oct_2010.pdf</ref> *Reduced temperature dependency due to no doping. *Better yield due to high density, better wafer utilization. *Reduced antenna issues *No body or well taps are needed. *Lower leakage currents due to isolation thus higher power efficiency. *Inherently radiation hardened ( resistant to soft errors ), thus reducing the need for redundancy. From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel [[metrology]] requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The threshold voltage of the transistor depends on the history of operation and applied voltage to it, thus making modeling harder. The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10&ndash;15% increase to total manufacturing costs.<ref>[http://news.cnet.com/IBM+touts+chipmaking+technology/2100-1001_3-254983.html IBM touts chipmaking technology]</ref> ==SOI transistors== An SOI MOSFET is a [[semiconductor]] device ([[MOSFET]]) in which a semiconductor layer such as silicon or [[germanium]] is formed on an insulator layer which may be a buried oxide (BOX) layer formed in a semiconductor substrate.<ref>United States Patent 6,835,633 ''SOI wafers with 30-100 Ang. Buried OX created by wafer bonding using 30-100 Ang. thin oxide as bonding layer''</ref><ref>United States Patent 7,002,214 ''Ultra-thin body super-steep retrograde well (SSRW) FET devices''</ref><ref>''Ultrathin-body SOI MOSFET for deep-sub-tenth micron era''; Yang-Kyu Choi; Asano, K.; Lindert, N.; Subramanian, V.; Tsu-Jae King; Bokor, J.; Chenming Hu; Electron Device Letters, IEEE; Volume 21, Issue 5, May 2000 Page(s):254 - 255</ref> SOI MOSFET devices are adapted for use by the computer industry.{{Citation needed|date=October 2008}} The buried oxide layer can be used in [[Static random-access memory|SRAM]] designs.<ref>United States Patent 7138685 " Vertical MOSFET SRAM cell" describes SOI buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures.</ref> There are two type of SOI devices: PDSOI (partially depleted SOI) and FDSOI (fully depleted SOI) MOSFETs. For an n-type PDSOI MOSFET the sandwiched p-type film between the gate oxide (GOX) and buried oxide (BOX) is large, so the depletion region can't cover the whole p region. So to some extent PDSOI behaves like bulk MOSFET. Obviously there are some advantages over the bulk MOSFETs. The film is very thin in FDSOI devices so that the depletion region covers the whole film. In FDSOI the front gate (GOX) supports less depletion charges than the bulk so an increase in inversion charges occurs resulting in higher switching speeds. The limitation of the depletion charge by the BOX induces a suppression of the depletion capacitance and therefore a substantial reduction of the subthreshold swing allowing FD SOI MOSFETs to work at lower gate bias resulting in lower power operation. The subthreshold swing can reach the minimum theoretical value for MOSFET at 300K, which is 60mV/decade. This ideal value was first demonstrated using numerical simulation [<ref> F. Balestra, Characterization and Simulation of SOI MOSFETs with Back Potential Control, PhD thesis, INP-Grenoble, 1985 </ref>] [<ref> F. Balestra, Challenges to Ultralow-Power Semiconductor Device Operation, in “Future Trends in Microelectronics-Journey into the unknown”, S. Lury, J. Xu, A. Zaslavsky Eds., J. Wiley & Sons, 2016 </ref>]. Other drawbacks in bulk MOSFETs, like threshold voltage roll off, etc. are reduced in FDSOI since the source and drain electric fields can't interfere due to the BOX. The main problem in PDSOI is the "[[floating body effect]] (FBE)" since the film is not connected to any of the supplies. ==Manufacture of SOI wafers== SiO₂-based SOI wafers can be produced by several methods: *''[[SIMOX]]'' - '''S'''eparation by '''IM'''plantation of '''OX'''ygen &ndash; uses an oxygen [[ion implantation|ion beam implantation]] process followed by high temperature annealing to create a buried SiO₂ layer.<ref>{{US patent|5888297}} Method of fabricating SOI substrate Atsushi Ogura, Issue date: Mar 30, 1999</ref><ref>{{US patent|5061642}} Method of manufacturing semiconductor on insulator Hiroshi Fujioka, Issue date: Oct 29, 1991</ref><ref>[http://www.ibis.com/simox.htm SIMOX-SOI Technology: Ibis Technology]</ref> *[[Wafer bonding]]<ref>"SemiConductor Wafer Bonding: Science and Technology" by Q.-Y. Tong & U. Gösele, Wiley-Interscience, 1998, {{ISBN|978-0-471-57481-1}}</ref><ref>{{US patent|4771016}} Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor, George Bajor et al., Issue date: Sep 13, 1988</ref> &ndash; the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer. **One prominent example of a wafer bonding process is the ''[[Smart Cut]]'' method developed by the French firm [[Soitec]] which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer. **''NanoCleave'' is a technology developed by Silicon Genesis Corporation that separates the silicon via stress at the interface of silicon and silicon-germanium alloy.<ref>http://www.sigen.com/</ref> **''ELTRAN'' is a technology developed by Canon which is based on porous silicon and water cut.<ref>[http://www.jsapi.jsap.or.jp/Pdf/Number04/CuttingEdge2.pdf ELTRAN - Novel SOI Wafer Technology], JSAPI vol.4</ref> *Seed methods<ref>{{US patent|5417180}}</ref> - wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate. An exhaustive review of these various manufacturing processes may be found in reference<ref name="celler"/> ==Use in the microelectronics industry== [[IBM]] began to use SOI in the high-end [[RS64#RS64-IV|RS64-IV]] "Istar" PowerPC-AS microprocessor in 2000. Other examples of microprocessors built on SOI technology include [[AMD]]'s 130&nbsp;nm, 90&nbsp;nm, 65&nbsp;nm, 45&nbsp;nm and 32&nbsp;nm single, dual, quad, six and eight core processors since 2001.<ref>[http://chip-architect.com/news/2000_11_07_process_130_nm.html Chip Architect: Intel and Motorola/AMD's 130 nm processes to be revealed]</ref> [[Freescale]] adopted SOI in their [[PowerPC]] 7455 CPU in late 2001, currently Freescale is shipping SOI products in 180&nbsp;nm, 130&nbsp;nm, 90&nbsp;nm and 45&nbsp;nm lines.<ref>[http://www.freescale.com/webapp/sps/site/overview.jsp?nodeId=0121000303#soi Process Technology]</ref> The 90&nbsp;nm [[Power Architecture]] based processors used in the [[Xbox 360]], [[PlayStation 3]] and [[Wii]] use SOI technology as well. Competitive offerings from [[Intel]] however continues to use conventional bulk [[CMOS]] technology for each process node, instead focusing on other venues such as [[HKMG]] and [[Tri-gate transistor]]s to improve transistor performance. In January 2005, Intel researchers reported on an experimental single-chip silicon rib waveguide Raman laser built using SOI.<ref name="Intel 2005">{{cite journal | url=http://www.ece.ucsb.edu/uoeg/publications/papers/Rong05nature.pdf | title=An all-silicon Raman laser | journal=Nature |date=January 2005 | volume=433 | pages=292–294 | doi=10.1038/nature03723 | authors=Rong, Haisheng; Liu, Ansheng; Jones, Richard; Cohen, Oded; Hak, Dani, Nicolaescu, Remus; Fang, Alexander; Paniccia, Mario}}</ref> As for the traditional foundries, on July 2006 [[TSMC]] claimed no customer wanted SOI,<ref>[http://www.fabtech.org/content/view/1698/74/ TSMC has no customer demand for SOI technology - Fabtech - The online information source for semiconductor professionals]</ref> but [[Chartered Semiconductor]] devoted a whole fab to SOI.<ref>[http://www.charteredsemi.com/media/corp/2006n/20060420_IBM_SOI.asp Chartered expands foundry market access to IBM's 90nm SOI technology]</ref> ==Use in high-performance radio frequency (RF) applications== In 1990, [[Peregrine Semiconductor]] began development of an SOI process technology utilizing a standard 0.5&nbsp;μm CMOS node and an enhanced sapphire substrate. Its patented [[silicon on sapphire]] (SOS) process is widely used in high-performance RF applications. The intrinsic benefits of the insulating sapphire substrate allow for high isolation, high linearity and electro-static discharge (ESD) tolerance. Multiple other companies have also applied SOI technology to successful RF applications in smartphones and cellular radios.<ref>{{cite news | title=Handset RFFEs: ''MMPAs, Envelope Tracking, Antenna Tuning, FEMs, and MIMO'' | first=Joe | last=Madden | url=http://mobile-experts.net/manuals/mexp-rffe-12%20toc.pdf | archive-url=https://web.archive.org/web/20160304044306/http://mobile-experts.net/manuals/mexp-rffe-12%20toc.pdf | dead-url=yes | archive-date=4 March 2016 |publisher= Mobile Experts | accessdate=2 May 2012 }} </ref> ==Use in photonics== SOI wafers are widely used in [[silicon photonics]].<ref>[https://books.google.com/books?id=6lsVVvFCBeAC&lpg=PA57&ots=XmqaiUFliA&dq=SOI%20Wafers%20in%20Photonics&hl=en&pg=PA111#v=onepage&q=SOI%20&f=false "Silicon photonics: an introduction" by Graham T. Reed, Andrew P. Knights. WIley. Page 111]</ref> The crystalline silicon layer on insulator can be used to fabricate optical waveguides and other optical devices, either passive or active (e.g. through suitable implantations). The buried insulator enables propagation of infrared light in the silicon layer on the basis of total internal reflection. The top surface of the waveguides can be either left uncovered and exposed to air (e.g. for sensing applications) or covered with a cladding, typically made of silica. ==See also== *[[FinFET]] *[[CMOS]] *[[MOSFET]] *[[Strain engineering]] *[[Intel TeraHertz]] - similar technology from Intel. *[[Wafer (electronics)]] *[[Wafer bonding]] *[[Silicon on sapphire]] ==References== {{reflist|30em}} ==External links== *[http://www.soiconsortium.org/ SOI Industry Consortium] - a site with extensive information and education for SOI technology *[http://www.chipestimate.com/SOI SOI IP portal] - A search engine for SOI IP *[http://www.amdboard.com/soispecial.html AMDboard] - a site with extensive information regarding SOI technology *[http://www.advancedsubstratenews.com/ Advanced Substrate News] - a newsletter about the SOI industry, produced by Soitec. *[http://www.migas.inpg.fr/2004/index.htm MIGAS '04] - The 7th session of MIGAS International Summer School on Advanced Microelectronics, devoted to SOI technology and devices. *[http://www.migas.inpg.fr/ MIGAS '09] - 12th session of the International Summer School on Advanced Microelectronics: "Silicon on Insulator (SOI) Nanodevices" {{DEFAULTSORT:Silicon On Insulator}} [[Category:Semiconductor structures]] [[Category:Semiconductor technology]] [[Category:Microtechnology]]'