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'{{Infobox CPU |image = W65C816S8PG-14 lg.jpg |image_size = |caption = W65C816S in PDIP40 package |name = WDC 65C816 |produced-start = {{Start date and age|1983}} |produced-end = |slowest = 1 | slow-unit = MHz |fastest = 14 | fast-unit = MHz |manuf1 = [[Western Design Center]], others |arch = [[MOS Technology 6502|6502]] |instructions = 92 |data-width = {{plainlist| *8 (external) *16 (internal)}} |address-width = 24 |pack1 = 40-pin [[Dual in-line package|DIP]] |pack2 = 44-pin [[Plastic leaded chip carrier|PLCC]], others |predecessor = {{plainlist| *MOS 6502 *[[WDC 65C02]]}} |successor = }} The '''W65C816S''' (also '''65C816''' or '''65816''') is an 8/16-bit [[microprocessor]] (MPU) developed and sold by the [[Western Design Center]] (WDC). Introduced in 1983,<ref>[http://processortimeline.info/proc1980.htm Chronology of Microprocessors (1980-1989)]</ref> the W65C816S is an enhanced version of the [[WDC 65C02]] 8-bit MPU, itself a [[CMOS]] enhancement of the venerable [[MOS Technology]] [[MOS Technology 6502|6502]] [[NMOS logic|NMOS]] MPU. The 65C816 was the CPU for the [[Apple IIGS]] and in modified form, the [[Super Nintendo Entertainment System]]. The ''65'' in the part's designation comes from its 65C02 compatibility mode, and the ''816'' signifies that the MPU has selectable 8&ndash; and 16&ndash;bit [[processor register|register]] sizes. In addition to the availability of 16 bit registers, the W65C816S features extended [[memory address]]ing to [[24-bit]]s, supporting up to 16 [[megabyte]]s of [[random-access memory]], an enhanced instruction set, and a 16 bit [[Stack (data structure)|stack pointer]], as well as several new electrical signals for improved system hardware management. At [[reset (computing)|reset]], the W65C816S starts in "emulation mode," meaning it substantially behaves as a 65C02. Thereafter, the W65C816S may be switched to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree of [[backward compatibility]] with most 65C02 software. However, unlike the [[PDIP|PDIP40]] version of the 65C02, which is a [[pin-compatible]] replacement for its NMOS ancestor, the PDIP40 W65C816S is not pin-compatible with any other 6502 family MPU. Related to the W65C816S is the '''W65C802''', which had the same internal structure and 16-bit support, but used a 40-pin layout compatible with the original 6502. This allowed it to be used as a drop-in replacement in certain roles. However, the 65C802 could not emit a full 24-bit address, which limited it to 64&nbsp;kB of memory. The 65C802 and its relatives are no longer produced. ==History== [[File:65c816plcc.jpg|thumb|[[plastic leaded chip carrier|PLCC-44]] version of '''W65C816S''' microprocessor, shown mounted on a [[single-board computer]].]] In 1981, [[Bill Mensch]], founder and [[chief executive officer|CEO]] of WDC, began development of the 65C02 with his production partners, primarily [[Rockwell Semiconductor]] and [[Synertek]]. The primary goal of the 65C02 effort was to move from the original 6502's NMOS process to the 65C02's CMOS, which would allow it to run at much lower power levels, somewhere between {{frac|10}} and {{frac|20}} when running at the same clock speeds. A number of new [[opcode]]s and bug fixes were also worked into the design.{{sfn|Eyes|Lichty|1986|p=42}} Development of the W65C816S commenced in 1982 after Mensch consulted with [[Apple Computer]] on a new version of the [[Apple II]] series of [[personal computer]]s that would, among other things, have improved graphics and sound. Apple wanted an MPU that would be software compatible with the 6502 then in use in the Apple II but with the ability to address more memory, and to load and store 16 bit words. The result was the 65C816, finished in March 1984, with samples provided to both Apple and [[Atari]] in the second half of the year and full release in 1985.{{sfn|Eyes|Lichty|1986|p=44}} Mensch was aided during the design process by his sister Kathryn, who was responsible for part of the device's layout. The same process also led to the 65C802, which was identical inside to the 65C816. Both were produced on the same fabrication lines and diverged only during the last metalization stages when the chip was being connected to the external pins. In the 65C802, those pins had the same layout as the original 6502, which allowed it to be used as a drop-in replacement while still allowing the 16-bit processing of the CPU to be used. However, as it used the original pinout it had only 16 addressing pins, and could therefore only access 64&nbsp;kB of external memory.{{sfn|Eyes|Lichty|1986|p=45}} Typically, when hardware manufacturers designed a project from the ground up, they used the 65C816 rather than the 65C802, resulting in the latter being withdrawn from production. Apple subsequently integrated the 65C816 into the [[Apple IIGS]] computer. The basic 65C816 design was [[second source|second-sourced]] by [[Verizon Communications#GTE|GTE]], [[Sanyo]] and others from the mid-to-late 1980s to the early 1990s. In the 1990s, both the 65C816 and 65C02 were converted to a fully [[static core]], which made it possible to completely stop the [[clock signal|processor clock]] without losing data in any of the registers. This feature, along with the use of [[static RAM|asynchronous static RAM]], made it possible to produce designs that used minimal power when in a standby state. {{As of|2019}}, the W65C816S is available from WDC in a 40 pin [[PDIP]] or [[plastic leaded chip carrier|PLCC44]] package, as well as a core for [[Application-specific integrated circuit|ASIC]] integration (for example [[Winbond]]'s W55V9x series of TV [[Edutainment]] [[integrated circuit|IC]]s). WDC, itself a [[fabless semiconductor company]], works with various [[semiconductor fabrication plant|foundries]] to produce the W65C816S, as well as other compatible products. Discrete processors are available through a number of electronics distributors. For designers who wish to include W65C816S functionality into a custom [[Application-specific integrated circuit|ASIC]], WDC offers RTL ([[register-transfer level]]) code in [[Verilog]]. [[File:WDC W65C802P 4 1.jpg|thumb|W65C802P]] ==Features== WDC 65816 features: {| class="infobox" style="font-size:88%" |- |style="text-align:center" |''WDC 65816 registers'' |- | {| style="font-size:88%;" |- | style="width:10px; text-align:center;"| <small>23</small> | style="width:10px; text-align:center;"| <small>22</small> | style="width:10px; text-align:center;"| <small>21</small> | style="width:10px; text-align:center;"| <small>20</small> | style="width:10px; text-align:center;"| <small>19</small> | style="width:10px; text-align:center;"| <small>18</small> | style="width:10px; text-align:center;"| <small>17</small> | style="width:10px; text-align:center;"| <small>16</small> | style="width:10px; text-align:center;"| <small>15</small> | style="width:10px; text-align:center;"| <small>14</small> | style="width:10px; text-align:center;"| <small>13</small> | style="width:10px; text-align:center;"| <small>12</small> | style="width:10px; text-align:center;"| <small>11</small> | style="width:10px; text-align:center;"| <small>10</small> | style="width:10px; text-align:center;"| <small>9</small> | style="width:10px; text-align:center;"| <small>8</small> | style="width:10px; text-align:center;"| <small>7</small> | style="width:10px; text-align:center;"| <small>6</small> | style="width:10px; text-align:center;"| <small>5</small> | style="width:10px; text-align:center;"| <small>4</small> | style="width:10px; text-align:center;"| <small>3</small> | style="width:10px; text-align:center;"| <small>2</small> | style="width:10px; text-align:center;"| <small>1</small> | style="width:10px; text-align:center;"| <small>0</small> | style="width:auto;" | ''(bit position)'' |- |colspan="25" | '''Main registers''' |- style="background:silver;color:black" | style="text-align:center; background:white" colspan="8"| | style="text-align:center;" colspan="8"| '''B''' | style="text-align:center;" colspan="8"| '''A''' | style="width:auto; background:white; color:black;"| Accumulators |- |colspan="25" | '''Index registers''' |- style="background:silver;color:black" | style="text-align:center; background:white" colspan="8"| | style="text-align:center;" colspan="16"| '''X''' | style="background:white; color:black;"| '''X''' index |- style="background:silver;color:black" | style="text-align:center; background:white" colspan="8"| | style="text-align:center;" colspan="16"| '''Y''' | style="background:white; color:black;"| '''Y''' index |- style="background:silver;color:black" | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | colspan="16" style="text-align:center; background:silver" | '''DP''' | style="background:white; color:black;"| '''D'''irect '''P'''age register |- style="background:silver;color:black" | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center;" colspan="16"| '''SP''' | style="background:white; color:black;"| '''S'''tack '''P'''ointer |- style="background:silver;color:black" | style="text-align:center;" colspan="8"| '''DB''' | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="text-align:center; background:white"| 0 | style="background:white; color:black;"| '''D'''ata '''B'''ank register |- |colspan="25" | '''Program counter''' |- style="background:silver;color:black" | style="text-align:center;" colspan="8"| '''PB''' | style="text-align:center;" colspan="16"| '''PC''' | style="background:white; color:black;"| '''P'''rogram '''C'''ounter |- |colspan="25" | '''Status register''' |- style="background:silver;color:black" | style="text-align:center; background:white" colspan="16" | | style="text-align:center;"| '''N''' | style="text-align:center;"| '''V''' | style="text-align:center;"| '''m''' | style="text-align:center;"| '''x''' | style="text-align:center;"| '''D''' | style="text-align:center;"| '''I''' | style="text-align:center;"| '''Z''' | style="text-align:center;"| '''C''' | style="background:white; color:black" | '''S'''tatus '''R'''egister |} |} * Fully static CMOS design offers low power consumption (300[[micro-|µ]][[amperes|A]] at 1[[megahertz|MHz]]) and increased noise immunity. * Wide operating [[voltage]] range: 1.8V to 5.0V ± 5%. * Wide [[clock rate|operating frequency]] range, officially 14&nbsp;MHz maximum at 5 volts, using a single-phase clock source (hobbyists have successfully operated the 65C816 at 20 MHz). * [[emulator|Emulation]] mode allows substantial software compatibility with the NMOS 6502 and CMOS 65C02, excepting undocumented [[opcode]]s. All 256 opcodes in the 65C816 are functional in both operating modes. * 24-bit memory addressing provides access to 16MB of [[Memory space (computational resource)|memory space]]. * 16-bit [[arithmetic logic unit|ALU]], [[accumulator (computing)|accumulator]] (A), [[stack pointer]] (SP), and [[index register]]s (X and Y). * 16-bit Direct Page (aka zero page) register (DP). * 8-bit data bank (DB) and program bank (PB) registers, generating bits 16-23 of 24-bit code and data addresses. Separate program and data bank registers allow program [[segmentation (memory)|segmentation]] and 16MB linear data addressing. * Valid data address (VDA) and valid program address (VPA) control outputs for memory qualification, dual [[CPU cache|cache]] and cycle steal [[direct memory access|DMA]] implementation. * Vector pull (VPB) control output to indicate when an [[interrupt vector]] is being fetched. * Abort (ABORTB) input and associated vector supports processor repairs of bus error conditions, such as [[page fault]]s and memory access violations. * * Direct register and stack relative addressing provides capability for [[reentrant (subroutine)|reentrant]], [[recursion|recursive]] and [[relocation (computer science)|re-locatable]] programming. * 24 [[addressing mode]]s&mdash;13 original 6502 modes with 92 [[instruction set|instructions]] using 256 [[op code]]s, including most new opcodes implemented in the 65C02. * Block-copy instructions, allowing rapid copying of data structures from one area of [[RAM]] to another with minimal code. * Wait-for-Interrupt (WAI) and Stop-the-Clock (STP) instructions further [[low-power electronics|reduce power consumption]], decrease [[interrupt latency]] and allows synchronization with external events. * [[Coprocessor|Co-Processor]] (COP) instruction with associated vector supports co-processor configurations, e.g., [[floating point unit|floating point processor]]s * Reserved "escape" (WDM) instruction for future two-byte opcodes and a link to future designs. (WDM is the initials of W65C816S designer [[Bill Mensch|William D. Mensch]].) ==Comparison with earlier models== ===Two modes=== The 65C816 has two operating modes, "emulation mode," in which the 16-bit operations are invisible—the index registers are forced to eight bits— and the chip appears to be very similar to the 65C02, with to the same cycle timings for the opcodes, and "native mode," which exposes all new features. The CPU automatically returns to emulation mode when it is powered on or reset, which allows it to replace a 65C02, assuming one makes the required circuit changes to accommodate the different pin layout.{{sfn|Eyes|Lichty|1986|p=42}} ===16-bit registers=== The most obvious change to the 65C816 when running in native mode is the expansion of the various registers from 8-bit to 16-bit sizes. This enhancement affects the accumulator (A), the X and Y [[index register]]s, and the [[stack pointer]] (SP). It does not affect the [[program counter]] (PC), which has always been 16-bit.{{sfn|Eyes|Lichty|1986|p=46}} When running in native mode, two bits in the status register change their meaning. In the original 6502, bits 4 and 5 were not used, although bit 4 is referred to as the B(reak) flag. In native mode, bit 4 becomes the x flag and bit 5 becomes the m flag. These bits control whether or not the [[index register]]s (x) and/or accumulator/memory (m) are 8-bit or 16-bit in size. Zeros in these bits set 16-bit sizes, ones set 8-bit sizes. These bits are fixed at ones when the processor is powered on or reset, but become changeable when the processor is switched to native mode.{{sfn|Eyes|Lichty|1986|p=46}} It might not be immediately obvious why one would want to use the now 16-bit registers in 8-bit mode. Switching to 8-bit mode using the new <code>SEP</code> (SEt bit in Processor status) and <code>REP</code> (REset) instructions means that all subsequent instructions accessing those registers will only read or write a single byte instead of two. For instance, if the m bit is set to 1 when an <code>LDA $1234</code> instruction is executed, only a single byte at address $1234 will be read, thereby reducing the number of cycles needed to execute the instruction.{{sfn|Eyes|Lichty|1986|p=50}} This is particularly useful when dealing with 8-bit character data, for instance.{{sfn|Eyes|Lichty|1986|p=65}} When register sizes are set to 16 bits, memory access will access two contiguous bytes of memory, at the cost of one extra clock cycle. Furthermore, a read-modify-write instruction, such as <code>ROR <addr></code>, when used while the accumulator is set to 16 bits, will affect two contiguous bytes of memory, not one. Similarly, all arithmetic and logical operations will be 16-bit operations.{{sfn|Eyes|Lichty|1986|p=52}} ===24-bit addressing=== The other major change to the system while running in native mode is that the memory model is expanded to a 24-bit format from the original 16-bit format of the 6502. This is handled using two 8-bit offset registers, the Data Bank Register (DB) and the Program Bank Register (PB). Addresses in the code remain in the original 16-bit format, but the values in the DB and PB are prepended to form a 24-bit address in [[main memory]]. This means that instructions can access data within a 64KB ''bank'', and if data outside that bank needs to be accessed, DB has to change or "long" addressing must be used (that is, specification of a 24-bit address as an operand to the instruction). PB determines from which 64KB bank the processor will fetch instructions—there is no programmatic means by which PB can be directly changed. Branches and 16-bit jumps or 16-bit subroutine calls are generally limited to the bank in PB (<code>JMP(<addr>)</code> always fetches the target address from bank $00). A 24-bit "long" jump or subroutine call is possible, which overcomes the normal 64 KB program size limit.{{sfn|Eyes|Lichty|1986|p=46}} A further addition to the register set is the 16-bit Direct Page Register (DP), which sets the base address for what was formerly called the zero page, but now referred to as direct page. Direct page addressing uses an 8-bit address, which results in faster access than when a 16- or 24-bit address is used. Also, some addressing modes that offer indirection are only possible on direct page. In the 65(C)02, the direct page is always the first 256 bytes of memory, thus "zero page." In native mode, the 65C816 can relocate direct (zero) page anywhere in the first 64KB of memory by writing the starting address into DP. There is a one-cycle access penalty if DP is not set to an even page boundary.{{sfn|Eyes|Lichty|1986|p=48}} ===Switching between modes=== The current mode of operation is stored in the emulation (E) bit. Having already added the new x and m bits to the previous set of six flags in the status register (SR), there were not enough bits left to hold the new mode bit. Instead, a unique solution was used in which the mode bit was left "invisible", unable to be directly accessed. The new <code>XCE</code> (eXchange Carry with Emulation) instruction exchanges the value of the emulation bit with the C(arry) bit, bit 0 in the status register. For instance, if one wants to enter native mode after the processor has started up, one would use <code>CLC</code> to CLear the Carry bit, and then <code>XCE</code> to write it to the emulation bit.{{sfn|Eyes|Lichty|1986|p=64}} Returning to 65C02 emulation mode uses <code>SEC</code> followed by <code>XCE</code>.{{sfn|Eyes|Lichty|1986|p=65}} Internally, the 65C816 is a fully 16-bit design. The m and x bits in SR determine how the user registers (accumulator and index) appear to the rest of the system. Upon reset, the 65C816 starts in 65C02 emulation mode, in which m and x are set to 1 and cannot be changed. Hence the registers appear to the rest of the system as 8 bits. The most significant byte (MSB) of the accumulator (the B-accumulator) is not directly accessible but can be swapped with the least significant byte (LSB) of the accumulator (the A-accumulator) by using the <code>XBA</code> instruction. There is no corresponding operation for the index registers (.X and .Y). Upon being switched to native mode, the MSB of .X and .Y will be zero, and the B-accumulator will be unchanged. If the m bit in SR is cleared, the B-accumulator will "ganged" to the A-accumulator to form a 16-bit register. A load/store or arithmetic/logical operation involving the accumulator and/or memory will be a 16-bit operation—two bus cycles are required to fetch/store a 16-bit value. If the x bit in SR is cleared, both index registers will be set to 16-bits. If used to index an address, e.g., <code>LDA SOMEWHERE,X</code>, the 16-bit value in the index register will be added to the base address to form the effective address. If the m bit in SR is set the accumulator will return to being an 8-bit register and subsequent operations on the accumulator, with a few exceptions, will be 8-bit operations. The B-accumulator will retain the value it had when the accumulator was operating in 16-bit mode. The exceptions are the instructions that transfer the direct page register (DP) and stack pointer (SP) to/from the accumulator. These operations are always 16-bits wide in native mode, regardless of the condition of the m bit in the status register. If the x bit in SR is set, not only will the index registers return to being 8 bits, whatever was in the MSB while in 16-bit mode will be lost, something an assembly language programmer cannot afford to forget.{{sfn|Eyes|Lichty|1986|p=51}} ==Applications== Systems based on 65816 variants: * [[Acorn Communicator]] * [[Apple IIGS]] * [[Super Nintendo Entertainment System]]: the [[video game console|console]]'s [[Ricoh 5A22]] CPU is based on the 65C816 **Additionally, 30+ Super NES games include the [[Nintendo SA-1|Nintendo SA1]], a 65C816-based co-processor chip, in each cartridge. It is also used in the [[C-One]] and [[SuperCPU]] enhancements for the [[Commodore 64]]. == See also == * [[Interrupts in 65xx processors]] ==References== ===Citations=== {{Reflist}} ===Bibliography=== * {{cite book |title=Programming the 65816 - including the 6502, 65C02, 65802 |first1=David |last1=Eyes |first2=Ron |last2=Lichty |publisher=Prentice Hall |date=1986 |isbn=978-0893037895 |url=https://archive.org/details/0893037893ProgrammingThe65816/ }} ==Further reading== {{See also|MOS Technology 6502#Further reading|l1=List of books about 65xx microprocessor families}} * ''[http://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf 65C816 Datasheet]''; Western Design Center; 55 pages; 2018. ==External links== * [http://www.westerndesigncenter.com/wdc/w65c816s-chip.cfm 65C816 webpage] - Western Design Center * [http://axis.llx.com/~nparker/a2/opcodes.html 6502/65C02/65C816 Instruction Set decoded] * [http://www.zophar.net/tech/65816.html 65816/65C816 Technical Documents] - zophar.net * [http://www.defence-force.org/computing/oric/coding/annexe_2/ A 6502 Programmer's Introduction to the 65816] &ndash; A ''Commodore World'' article by Brett Tabke; includes [[Creative Micro Designs|CMD]]'s instruction set summary * [http://sbc.bcstechnology.net/65c816interrupts.html Investigating 65C816 Interrupts] &ndash; An extensive discussion of interrupt processing on the 65C816 <!--- *[http://www.winbond-usa.com/mambo/content/view/286/523/#ProductSelectionGuide Winbond TV Edutainment IC Selection Guide] &ndash; ICs with 65816 CPU core ---> {{FOLDOC}} {{MOS CPU}} {{DEFAULTSORT:WDC 65816 65802}} [[Category:65xx microprocessors]] [[Category:Computer-related introductions in 1983]] [[Category:16-bit microprocessors]]'