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Old page wikitext, before the edit (old_wikitext) | '{{Short description|Integrated circuit that incorporates the components of a computer}}
{{Use American English|date=October 2018}}
[[File:Raspberry Pi 4 Model B - Top.jpg|thumb|The [[Raspberry Pi]] uses a system on a chip as an almost fully contained [[microcomputer]]. This SoC does not contain any kind of data storage, which is common for a microprocessor SoC.]]
A '''system on a chip''' ('''SoC'''; {{IPAc-en|ˌ|ɛ|s|ˌ|oʊ|ˈ|s|iː|}} {{respell|es|oh|SEE}} or {{IPAc-en|s|ɒ|k}} {{respell|sock}}<ref group="nb">This article uses the convention that SoC is pronounced {{IPAc-en|ˌ|ɛ|s|ˌ|oʊ|ˈ|s|iː}} {{respell|es|oh|SEE}}. Therefore, it uses the convention "an" for the [[indefinite article]] corresponding to SoC ("'''an''' SoC"). Other sources may pronounce it as {{IPAc-en|s|ɒ|k}} {{respell|sock}} and therefore use "'''a''' SoC".</ref>) is an [[integrated circuit]] (also known as a "chip") that integrates all or most components of a [[computer]] or other [[Electronics|electronic system]]. These components almost always include a [[central processing unit]] (CPU), [[Computer memory|memory]], [[input/output]] ports and [[Computer data storage#Secondary storage|secondary storage]], often alongside other components such as [[radio modem]]s and a [[graphics processing unit]] (GPU) – all on a single [[Wafer (electronics)|substrate]] or microchip.<ref>{{Cite web|url=https://www.networkworld.com/article/3154386/7-dazzling-smartphone-improvements-with-qualcomms-snapdragon-835-chip.html|title=7 dazzling smartphone improvements with Qualcomm's Snapdragon 835 chip|first=Agam|last=Shah|date=January 3, 2017|website=Network World}}</ref> It may contain [[Digital signal (electronics)|digital]], [[Analog signal|analog]], [[Mixed-signal integrated circuit|mixed-signal]], and often [[radio frequency]] [[signal processing]] functions (otherwise it is considered only an application processor).
Higher-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (almost always [[LPDDR]] and [[Universal Flash Storage|eUFS]] or [[eMMC]], respectively) chips, that may be layered on top of the SoC in what's known as a [[package on package]] (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may use separate wireless modems.<ref>https://arstechnica.com/gadgets/2020/02/qualcomms-snapdragon-x60-promises-smaller-5g-modems-in-2021/?amp=1</ref>
SoCs are in contrast to the common traditional [[motherboard]]-based [[Personal computer|PC]] [[Computer architecture|architecture]], which separates components based on function and connects them through a central interfacing circuit board.<ref group="nb">This central board is called the "mother board" for hosting the "child" component cards.</ref> Whereas a motherboard houses and connects detachable or replaceable components, SoCs integrate all of these components into a single integrated circuit. An SoC will typically integrate a CPU, graphics and memory interfaces,<ref group="nb">The graphics connections ([[PCI Express]]) and RAM historically constituted the [[northbridge (computing)|northbridge]] of motherboard-backed discrete architectures.</ref> hard-disk and USB connectivity,<ref group="nb">The hard disk and USB connectivity historically comprised part of the [[southbridge (computing)|southbridge]] of motherboard-backed discrete modular architectures.</ref> [[random-access memory|random-access]] and [[read-only memory|read-only]] [[computer memory|memories]] and secondary storage and/or their controllers on a single circuit die, whereas a motherboard would connect these modules as [[discrete components]] or [[expansion card]]s.
An SoC integrates a [[microcontroller]], [[microprocessor]] or perhaps several processor cores with peripherals like a [[GPU]], [[Wi-Fi]] and [[cellular network]] radio modems, and/or one or more [[coprocessor]]s. Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with even more advanced [[peripheral]]s. {{Selfref inline|For an overview of integrating system components, see [[system integration]].}}
More tightly integrated computer system designs improve [[computer performance|performance]] and reduce [[power consumption]] as well as [[Die (integrated circuit)|semiconductor die]] area than multi-chip designs with equivalent functionality. This comes at the cost of reduced [[Interchangeable parts|replaceability]] of components. By definition, SoC designs are fully or nearly fully integrated across different component [[Modularity|modules]]. For these reasons, there has been a general trend towards tighter integration of components in the [[Semiconductor industry|computer hardware industry]], in part due to the influence of SoCs and lessons learned from the mobile and embedded computing markets. SoCs can be viewed as part of a larger trend towards [[embedded system|embedded computing]] and [[hardware acceleration]].
SoCs are very common in the [[mobile computing]] (such as in [[smartphones]] and [[tablet computer]]s) and [[edge computing]] markets.<ref>Pete Bennett, [[EE Times]]. "[http://www.eetimes.com/document.asp?doc_id=1276973 The why, where and what of low-power SoC design]." December 2, 2004. Retrieved July 28, 2015.</ref><ref>{{Cite web|url=https://www.design-reuse.com/articles/42705/power-management-for-iot-soc-development.html|title=Power Management for Internet of Things (IoT) System on a Chip (SoC) Development|last=Nolan|first=Stephen M.|website=Design And Reuse|access-date=2018-09-25}}</ref> They are also commonly used in [[embedded system]]s such as WiFi routers and the [[Internet of things|Internet of Things]].
== Types ==
[[Image:ARMSoCBlockDiagram.svg|right|275px|thumbnail|[[Microcontroller]]-based system on a chip]]In general, there are four distinguishable types of SoCs:
* SoCs built around a [[microcontroller]],
* SoCs built around a [[microprocessor]], often found in mobile phones;
* Specialized [[application-specific integrated circuit]] SoCs designed for specific applications that do not fit into the above two categories, and
* [[Programmable system-on-chip|Programmable SoCs]] (PSoC), where most functionality is fixed but some functionality is [[reconfigurable computing|reprogrammable]] in a manner analogous to a [[field-programmable gate array]].
[[File:KL AMD Am286LX ZX.jpg|thumb|[[AMD]] Am286ZX/LX, SoC based on [[Intel 80286]] ]]
== Applications ==
SoCs can be applied to any computing task. However, they are typically used in mobile computing such as tablets, smartphones, smartwatches and netbooks as well as [[embedded system]]s and in applications where previously [[microcontroller]]s would be used.
=== Embedded systems ===
Where previously only microcontrollers could be used, SoCs are rising to prominence in the embedded systems market. Tighter system integration offers better reliability and [[Mean time between failures|mean time between failure]], and SoCs offer more advanced functionality and computing power than microcontrollers.<ref>{{Cite news|url=https://www.embedded.com/design/mcus-processors-and-socs/4419584/Is-a-single-chip-SOC-processor-right-for-your-embedded-project-|title=Is a single-chip SOC processor right for your embedded project?|work=Embedded|access-date=2018-10-13|language=en}}</ref> Applications include [[AI accelerator|AI acceleration]], embedded [[machine vision]],<ref>{{Cite web|url=https://www.imveurope.com/news/qualcomm-launches-socs-embedded-vision|title=Qualcomm launches SoCs for embedded vision {{!}} Imaging and Machine Vision Europe|website=www.imveurope.com|language=en|access-date=2018-10-13}}</ref> data collection, [[telemetry]], vector processing and [[ambient intelligence]]. Often embedded SoCs target the [[internet of things]], [[Internet of things|industrial internet of things]] and [[edge computing]] markets.
=== Mobile computing ===
[[Mobile computing]] based SoCs always bundle processors, memories, on-chip [[Cache (computing)|caches]], [[wireless networking]] capabilities and often [[digital camera]] hardware and firmware. With increasing memory sizes, high end SoCs will often have no memory and flash storage and instead, the memory and [[flash memory]] will be placed right next to, or above ([[package on package]]), the SoC.<ref>{{Cite web|url=https://www.ifixit.com/Teardown/Samsung+Galaxy+S10+and+S10e+Teardown/120331|title=Samsung Galaxy S10 and S10e Teardown|date=March 6, 2019|website=iFixit}}</ref> Some examples of mobile computing SoCs include:
* [[Samsung Electronics]]: [[List of Samsung System on Chips|list]], typically based on [[ARM architecture|ARM]]
** [[Exynos]], used mainly by Samsung's [[Samsung Galaxy|Galaxy]] series of smartphones
* [[Qualcomm]]:
** [[Qualcomm Snapdragon|Snapdragon]] ([[List of Qualcomm Snapdragon systems-on-chip|list]]), used in many [[LG Corporation|LG]], [[Xiaomi]], [[Google Pixel]], [[HTC]] and Samsung Galaxy smartphones. In 2018, Snapdragon SoCs are being used as the backbone of [[Laptop|laptop computers]] running [[Windows 10]], marketed as "Always Connected PCs".<ref name=":3">{{Cite news|url=https://www.windowscentral.com/arm-going-after-intel-new-chip-roadmap-through-2020|title=ARM is going after Intel with new chip roadmap through 2020|work=Windows Central|access-date=2018-10-06|language=en}}</ref><ref name=":4">{{Cite web|url=https://www.microsoft.com/en-us/windows/always-connected-laptop-pcs|title=Always Connected PCs, Extended Battery Life 4G LTE Laptops {{!}} Windows|website=www.microsoft.com|language=en-us|access-date=2018-10-06}}</ref>
=== Personal computers ===
In 1992, [[Acorn Computers]] produced the [[Acorn Archimedes#New range and a laptop|A3010, A3020 and A4000 range of personal computers]] with the ARM250 SoC. It combined the original Acorn ARM2 processor with a memory controller (MEMC), video controller (VIDC), and I/O controller (IOC). In previous Acorn [[ARM architecture|ARM]]-powered computers, these were four discrete chips. The ARM7500 chip was their second-generation SoC, based on the ARM700, VIDC20 and IOMD controllers, and was widely licensed in embedded devices such as set-top-boxes, as well as later Acorn personal computers.
SoCs are being applied to mainstream [[personal computer]]s as of 2018.<ref name=":3" /> They are particularly applied to [[laptop]]s and [[Tablet computer|tablet PCs]]. Tablet and laptop manufacturers have learned lessons from embedded systems and smartphone markets about reduced power consumption, better performance and reliability from tighter [[System integration|integration]] of hardware and [[firmware]] [[Module system|modules]], and [[LTE (telecommunication)|LTE]] and other [[wireless network]] communications integrated on chip (integrated [[network interface controller]]s).<ref>{{Cite news|url=https://www.qualcomm.com/products/modems|title=Gigabit Class LTE, 4G LTE and 5G Cellular Modems {{!}} Qualcomm|work=Qualcomm|access-date=2018-10-13|language=en}}</ref>
[[ARM architecture|ARM]]-based:
* [[Qualcomm Snapdragon]]<ref name=":4" />
* ARM250
* ARM7500(FE)
* [[Apple M1]]
[[x86]]-based:
* [[Intel Core]] [[CULV]]
== Structure ==
An SoC consists of hardware [[functional unit]]s, including [[microprocessor]]s that run [[Computer program|software code]], as well as a [[communications subsystem]] to connect, control, direct and interface between these functional modules.
=== Functional components ===
==== Processor cores ====
An SoC must have at least one [[processor core]], but typically an SoC has more than one core. Processor cores can be a [[microcontroller]], [[microprocessor]] (μP),<ref name="Furber ARM">{{Cite book|title=ARM system-on-chip architecture|last=Furber|first=Stephen B.|publisher=Addison-Wesley|year=2000|isbn=0201675196|location=Harlow, England|oclc=44267964}}</ref> [[digital signal processor]] (DSP) or [[application-specific instruction set processor]] (ASIP) core.<ref name=":1">{{Cite book|title=Pipelined Multiprocessor System-on-Chip for Multimedia|publisher=[[Springer-Verlag|Springer]]|year=2014|isbn=9783319011134|oclc=869378184|authors=Haris Javaid, Sri Parameswaran}}</ref> ASIPs have [[Instruction set architecture|instruction sets]] that are customized for an [[application domain]] and designed to be more efficient than general-purpose instructions for a specific type of workload. [[Multi-processor system-on-chip|Multiprocessor SoCs]] have more than one processor core by definition.
Whether single-core, [[Multi-core processor|multi-core]] or [[manycore]], SoC processor cores typically use [[Reduced instruction set computer|RISC]] instruction set architectures. RISC architectures are advantageous over [[Complex instruction set computer|CISC]] processors for SoCs because they require less digital logic, and therefore less power and area on [[Die (integrated circuit)|board]], and in the [[Embedded system|embedded]] and [[mobile computing]] markets, area and power are often highly constrained. In particular, SoC processor cores often use the [[ARM architecture]] because it is a [[Soft microprocessor|soft processor]] specified as an [[IP core]] and is more power efficient than [[x86]].<ref name="Furber ARM" />
==== Memory ====
{{Further|Computer memory}}
SoCs must have [[semiconductor memory]] blocks to perform their computation, as do [[microcontroller]]s and other [[embedded system]]s. Depending on the application, SoC memory may form a [[memory hierarchy]] and [[cache hierarchy]]. In the mobile computing market, this is common, but in many [[Low-power electronics|low-power]] embedded microcontrollers, this is not necessary. Memory technologies for SoCs include [[read-only memory]] (ROM), [[random-access memory]] (RAM), Electrically Erasable Programmable ROM ([[EEPROM]]) and [[flash memory]].<ref name="Furber ARM" /> As in other computer systems, RAM can be subdivided into relatively faster but more expensive [[Static random-access memory|static RAM]] (SRAM) and the slower but cheaper [[Dynamic random-access memory|dynamic RAM]] (DRAM). When an SoC has a [[Cache (computing)|cache]] hierarchy, SRAM will usually be used to implement [[processor register]]s and cores' [[L1 cache]]s whereas DRAM will be used for lower levels of the cache hierarchy including [[main memory]]. "Main memory" may be specific to a single processor (which can be [[Multi-core processor|multi-core]]) when the SoC [[Multi-processor system-on-chip|has multiple processors]], in which case it is [[distributed memory]] and must be sent via {{Section link||Intermodule communication|nopage=y}} on-chip to be accessed by a different processor.<ref name=":1" /> For further discussion of multi-processing memory issues, see [[cache coherence]] and [[memory latency]].
==== Interfaces ====
SoCs include external [[Electrical connector|interfaces]], typically for [[communication protocol]]s. These are often based upon industry standards such as [[USB]], [[FireWire]], [[Ethernet]], [[Universal synchronous and asynchronous receiver-transmitter|USART]], [[Serial Peripheral Interface|SPI]], [[HDMI]], [[I²C]], etc. These interfaces will differ according to the intended application. [[Wireless network]]ing protocols such as [[Wi-Fi]], [[Bluetooth]], [[6LoWPAN]] and [[near-field communication]] may also be supported.
When needed, SoCs include [[Analog signal|analog]] interfaces including [[Analog-to-digital converter|analog-to-digital]] and [[digital-to-analog converter]]s, often for [[signal processing]]. These may be able to interface with different types of [[sensor]]s or [[actuator]]s, including [[smart transducer]]s. They may interface with application-specific [[Modularity|modules]] or shields.<ref group="nb">In [[embedded system]]s, "shields" are analogous to [[expansion card]]s for [[Personal computer|PCs]]. They often fit over a [[microcontroller]] such as an [[Arduino]] or [[single-board computer]] such as the [[Raspberry Pi]] and function as [[peripheral]]s for the device.</ref> Or they may be internal to the SoC, such as if an analog sensor is built in to the SoC and its readings must be converted to digital signals for mathematical processing.
==== Digital signal processors ====
[[Digital signal processor]] (DSP) cores are often included on SoCs. They perform [[signal processing]] operations in SoCs for [[sensor]]s, [[actuator]]s, [[data collection]], [[data analysis]] and multimedia processing. DSP cores typically feature [[very long instruction word]] (VLIW) and [[SIMD|single instruction, multiple data]] (SIMD) [[instruction set architecture]]s, and are therefore highly amenable to exploiting [[instruction-level parallelism]] through [[Parallel processing (DSP implementation)|parallel processing]] and [[superscalar execution]].<ref name=":1" />{{Rp|4}} DSP cores most often feature application-specific instructions, and as such are typically [[application-specific instruction-set processor]]s (ASIP). Such application-specific instructions correspond to dedicated hardware [[functional unit]]s that compute those instructions.
Typical DSP instructions include [[Multiply–accumulate operation|multiply-accumulate]], [[Fast Fourier transform]], [[Fused multiply-accumulate|fused multiply-add]], and [[convolution]]s.
==== Other ====
As with other computer systems, SoCs require [[Clock generator|timing sources]] to generate [[clock signal]]s, control execution of SoC functions and provide time context to [[signal processing]] applications of the SoC, if needed. Popular time sources are [[crystal oscillators]] and [[phase-locked loop]]s.
SoC [[peripheral]]s including [[counter (digital)|counter]]-timers, real-time [[timer]]s and [[power-on reset]] generators. SoCs also include [[voltage regulator]]s and [[power management]] circuits.
=== Intermodule communication ===
SoCs comprise many [[execution unit]]s. These units must often send [[data]] and [[Instruction (computing)|instructions]] back and forth. Because of this, all but the most trivial SoCs require [[Communications system|communications subsystems]]. Originally, as with other [[microcomputer]] technologies, [[Bus (computing)|data bus]] architectures were used, but recently designs based on sparse intercommunication networks known as [[Network on a chip|networks-on-chip]] (NoC) have risen to prominence and are forecast to overtake bus architectures for SoC design in the near future.<ref name=":0">{{Cite book|title=Network-on-chip: the Next Generation of System-on-Chip Integration|last=Kundu|first=Santanu|last2=Chattopadhyay|first2=Santanu|publisher=CRC Press|year=2014|isbn=9781466565272|edition=1st|location=Boca Raton, FL|oclc=895661009}}</ref>
==== Bus-based communication ====
Historically, a shared global [[bus (computing)|computer bus]] typically connected the different components, also called "blocks" of the SoC.<ref name=":0" /> A very common bus for SoC communications is ARM's royalty-free Advanced Microcontroller Bus Architecture ([[Advanced Microcontroller Bus Architecture|AMBA]]) standard.
[[Direct memory access]] controllers route data directly between external interfaces and SoC memory, bypassing the CPU or [[control unit]], thereby increasing the data [[throughput]] of the SoC. This is similar to some [[device driver]]s of peripherals on component-based [[multi-chip module]] PC architectures.
Computer buses are limited in [[scalability]], supporting only up to tens of cores ([[multicore]]) on a single chip.<ref name=":0" />{{Rp|xiii}} Wire delay is not scalable due to continued [[miniaturization]], [[Computer performance|system performance]] does not scale with the number of cores attached, the SoC's [[operating frequency]] must decrease with each additional core attached for power to be sustainable, and long wires consume large amounts of electrical power. These challenges are prohibitive to supporting [[manycore]] systems on chip.<ref name=":0" />{{Rp|xiii}}
==== Network on a chip ====
{{Main|Network on a chip}}
In the late [[2010s]], a trend of SoCs implementing [[communications subsystem]]s in terms of a network-like topology instead of [[bus (computing)|bus-based]] protocols has emerged. A trend towards [[Multi-processor system-on-chip|more processor cores on SoCs]] has caused on-chip communication efficiency to become one of the key factors in determining the overall system performance and cost.<ref name=":0" />{{Rp|xiii}} This has led to the emergence of interconnection networks with [[Router (computing)|router]]-based [[packet switching]] known as "[[network on a chip|networks on chip]]" (NoCs) to overcome the [[Bottleneck (engineering)|bottlenecks]] of bus-based networks.<ref name=":0" />{{Rp|xiii}}
Networks-on-chip have advantages including destination- and application-specific [[routing]], greater power efficiency and reduced possibility of [[bus contention]]. Network-on-chip architectures take inspiration from [[communication protocols]] like [[Transmission Control Protocol|TCP]] and the [[Internet protocol suite]] for on-chip communication,<ref name=":0" /> although they typically have fewer [[network layer]]s. Optimal network-on-chip [[network architecture]]s are an ongoing area of much research interest. NoC architectures range from traditional distributed computing [[Network topology|network topologies]] such as [[Torus interconnect|torus]], [[Hypercube internetwork topology|hypercube]], [[Mesh networking|meshes]] and [[tree network]]s to [[genetic algorithm scheduling]] to [[randomized algorithm]]s such as [[Branching random walk|random walks with branching]] and randomized [[time to live]] (TTL).
Many SoC researchers consider NoC architectures to be the future of SoC design because they have been shown to efficiently meet power and throughput needs of SoC designs. Current NoC architectures are two-dimensional. 2D IC design has limited [[Floorplan (microelectronics)|floorplanning]] choices as the number of cores in SoCs increase, so as [[three-dimensional integrated circuit]]s (3DICs) emerge, SoC designers are looking towards building three-dimensional on-chip networks known as 3DNoCs.<ref name=":0" />
== Design flow ==
{{More citations needed section|date=March 2017}}
{{Main|Design flow (EDA)|Physical design (electronics)|Platform-based design|l1=Electronics design flow|l3=}}{{See also|Systems design|Software design|label 2=Software design process}}[[Image:SoCDesignFlow.svg|275px|thumbnail|SoC design flow|alt=]]
A system on a chip consists of both the [[electronic hardware|hardware]], described in {{Section link||Structure|nopage=y}}, and the [[software]] controlling the microcontroller, microprocessor or digital signal processor cores, peripherals and interfaces. The [[design flow (EDA)|design flow]] for an SoC aims to develop this hardware and software at the same time, also known as architectural co-design. The design flow must also take into account optimizations ({{Section link||Optimization goals|nopage=y}}) and constraints.
Most SoCs are developed from pre-qualified hardware component [[Semiconductor intellectual property core|IP core specifications]] for the hardware elements and [[execution unit]]s, collectively "blocks", described above, together with software [[device driver]]s that may control their operation. Of particular importance are the [[protocol stack]]s that drive industry-standard interfaces like [[Universal Serial Bus|USB]]. The hardware blocks are put together using [[computer-aided design]] tools, specifically [[electronic design automation]] tools; the [[modular programming|software modules]] are integrated using a software [[integrated development environment]].
SoCs components are also often designed in [[high-level programming language]]s such as [[C++]], [[MATLAB]] or [[SystemC]] and converted to [[Register-transfer level|RTL]] designs through [[high-level synthesis]] (HLS) tools such as [[C to HDL]] or [[flow to HDL]].<ref>{{Cite news|url=http://www.eejournal.com/archives/articles/20110825-mathworks/|title=Best Practices for FPGA Prototyping of MATLAB and Simulink Algorithms|date=2011-08-25|work=EEJournal|access-date=2018-10-08|language=en-US}}</ref> HLS products called "algorithmic synthesis" allow designers to use C++ to model and synthesize system, circuit, software and verification levels all in one high level language commonly known to [[computer engineers]] in a manner independent of time scales, which are typically specified in HDL.<ref>{{Cite web|url=https://www.eetimes.com/document.asp?doc_id=1271261|title=The 'why' and 'what' of algorithmic synthesis|last=Bowyer|first=Bryan|date=2005-02-05|website=[[EE Times]]|access-date=2018-10-08}}</ref> Other components can remain software and be compiled and embedded onto [[Soft microprocessor|soft-core processors]] included in the SoC as modules in HDL as [[Semiconductor intellectual property core|IP cores]].
Once the [[Computer architecture|architecture]] of the SoC has been defined, any new hardware elements are written in an abstract [[hardware description language]] termed [[Register-transfer level|register transfer level]] (RTL) which defines the circuit behavior, or synthesized into RTL from a high level language through high-level synthesis. These elements are connected together in a hardware description language to create the full SoC design. The logic specified to connect these components and convert between possibly different interfaces provided by different vendors is called [[glue logic]].
=== Design verification ===
{{Further|Functional verification|Signoff (electronic design automation)||label2=}}
Chips are verified for validation correctness before being sent to a [[Semiconductor fabrication plant|semiconductor foundry]]. This process is called [[functional verification]] and it accounts for a significant portion of the time and energy expended in the [[Integrated circuit development|chip design life cycle]], often quoted as 70%.<ref name="70% verification?">[[EE Times]]. "[http://www.eetimes.com/author.asp?section_id=36&doc_id=1264922 Is verification really 70 percent?]." June 14, 2004. Retrieved July 28, 2015.</ref><ref name="verification vs. validation">{{cite web|url=http://www.softwaretestingclass.com/difference-between-verification-and-validation/|title=Difference between Verification and Validation|work=Software Testing Class|access-date=2018-04-30|quote=In interviews most of the interviewers are asking questions on “What is Difference between Verification and Validation?” Many people use verification and validation interchangeably but both have different meanings.}}</ref> With the growing complexity of chips, [[hardware verification language]]s like [[SystemVerilog]], [[SystemC]], [[e (verification language)|e]], and [[OpenVera]] are being used. [[Software bug|Bugs]] found in the verification stage are reported to the designer.
Traditionally, engineers have employed simulation acceleration, [[emulator|emulation]] or prototyping on [[Reconfigurable computing|reprogrammable hardware]] to verify and debug hardware and software for SoC designs prior to the finalization of the design, known as [[tape-out]]. [[Field-programmable gate array]]s (FPGAs) are favored for prototyping SoCs because [[FPGA prototyping|FPGA prototypes]] are reprogrammable, allow [[debugging]] and are more flexible than [[application-specific integrated circuit]]s (ASICs).<ref name="nm prototyping">{{Cite web|url=http://www.tayden.com/publications/Nanometer%20Prototyping.pdf|title=Nanometer prototyping|last=Rittman|first=Danny|date=2006-01-05|website=Tayden Design|access-date=2018-10-07}}</ref><ref name="Reason to debug in FPGA">{{Cite web|url=http://www.design-reuse.com/articles/13550/fpga-prototyping-to-structured-asic-production-to-reduce-cost-risk-ttm.html|title=FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk & TTM|website=Design And Reuse|access-date=2018-10-07}}</ref>
With high capacity and fast compilation time, simulation acceleration and emulation are powerful technologies that provide wide visibility into systems. Both technologies, however, operate slowly, on the order of MHz, which may be significantly slower – up to 100 times slower – than the SoC's operating frequency. Acceleration and emulation boxes are also very large and expensive at over US$1 million.{{Citation needed|date=May 2018}}
FPGA prototypes, in contrast, use FPGAs directly to enable engineers to validate and test at, or close to, a system's full operating frequency with real-world stimuli. Tools such as Certus<ref>Brian Bailey, EE Times. "[http://www.eetimes.com/document.asp?doc_id=1317504 Tektronix hopes to shake up ASIC prototyping]." October 30, 2012. Retrieved July 28, 2015.</ref> are used to insert probes in the FPGA RTL that make signals available for observation. This is used to debug hardware, firmware and software interactions across multiple FPGAs with capabilities similar to a logic analyzer.
In parallel, the hardware elements are grouped and passed through a process of [[logic synthesis]], during which performance constraints, such as operational frequency and expected signal delays, are applied. This generates an output known as a [[netlist]] describing the design as a physical circuit and its interconnections. These netlists are combined with the [[glue logic]] connecting the components to produce the schematic description of the SoC as a circuit which can be [[printed circuit board|printed]] onto a chip. This process is known as [[place and route]] and precedes [[tape-out]] in the event that the SoCs are produced as [[application-specific integrated circuit]]s (ASIC).
== Optimization goals ==
SoCs must optimize [[Power consumption|power use]], area on [[Die (integrated circuit)|die]], communication, positioning for [[Locality of reference|locality]] between modular units and other factors. Optimization is necessarily a design goal of SoCs. If optimization was not necessary, the engineers would use a [[multi-chip module]] architecture without accounting for the area utilization, power consumption or performance of the system to the same extent.
Common optimization targets for SoC designs follow, with explanations of each. In general, optimizing any of these quantities may be a hard [[combinatorial optimization]] problem, and can indeed be [[NP-hardness|NP-hard]] fairly easily. Therefore, sophisticated [[optimization algorithm]]s are often required and it may be practical to use [[approximation algorithm]]s or [[Heuristic (computer science)|heuristics]] in some cases. Additionally, most SoC designs contain [[Multivariate optimization|multiple variables to optimize simultaneously]], so [[Pareto efficiency|Pareto efficient]] solutions are sought after in SoC design. Oftentimes the goals of optimizing some of these quantities are directly at odds, further adding complexity to design optimization of SoCs and introducing [[Trade-off#Engineering|trade-offs]] in system design.
For broader coverage of trade-offs and [[requirements analysis]], see [[requirements engineering]].
=== Targets ===
==== Power consumption ====
SoCs are optimized to minimize the [[Electric power#Definition|electrical power]] used to perform the SoC's functions. Most SoCs must use low power. SoC systems often require long [[battery life]] (such as [[smartphone]]s), can potentially spending months or years without a power source needing to maintain autonomous function, and often are limited in power use by a high number of [[Embedded system|embedded]] SoCs being [[Distributed computing|networked together]] in an area. Additionally, energy costs can be high and conserving energy will reduce the [[total cost of ownership]] of the SoC. Finally, [[waste heat]] from high energy consumption can damage other circuit components if too much heat is dissipated, giving another pragmatic reason to conserve energy. The amount of [[energy]] used in a circuit is the [[integral]] of [[Power (physics)|power]] consumed with respect to time, and the [[Mean value theorem|average rate]] of power consumption is the product of [[Electric current|current]] by [[voltage]]. Equivalently, by [[Ohm's law]], power is current squared times resistance or voltage squared divided by [[Resistance (physics)|resistance]]:
<math display="block">P = IV = \frac{V^2}{R} = {I^2}{R}</math>SoCs are frequently embedded in [[Mobile device|portable devices]] such as [[smartphones]], [[GPS navigation device]]s, digital [[Digital watch|watches]] (including [[smartwatch]]es) and [[netbook]]s. Customers want long battery lives for [[mobile computing]] devices, another reason that power consumption must be minimized in SoCs. [[Multimedia application]]s are often executed on these devices, including [[video game]]s, [[video streaming]], [[image processing]]; all of which have grown in [[computational complexity]] in recent years with user demands and expectations for higher-[[Video quality|quality]] multimedia. Computation is more demanding as expectations move towards [[3D video]] at [[high resolution]] with [[List of video compression formats|multiple standards]], so SoCs performing multimedia tasks must be computationally capable platform while being low power to run off a standard mobile battery.<ref name=":1" />{{Rp|3}}
==== Performance per watt ====
{{See also|Green computing}}
SoCs are optimized to maximize [[power efficiency]] in performance per watt: maximize the performance of the SoC given a budget of power usage. Many applications such as [[edge computing]], [[distributed processing]] and [[ambient intelligence]] require a certain level of [[Computer performance|computational performance]], but power is limited in most SoC environments. The [[ARM architecture]] has greater performance per watt than [[x86]] in embedded systems, so it is preferred over x86 for most SoC applications requiring an [[Soft microprocessor|embedded processor]].
==== Waste heat ====
{{Main|Heat generation in integrated circuits}}{{See also|Thermal management (electronics)|Thermal design power|label 1=Thermal management in electronics}}
SoC designs are optimized to minimize [[waste heat]] [[dissipation|output]] on the chip. As with other [[integrated circuit]]s, heat generated due to high [[power density]] are the [[Bottleneck (engineering)|bottleneck]] to further [[miniaturization]] of components.<ref name=":2">{{Cite book|title=Heat Management in Integrated circuits: On-chip and system-level monitoring and cooling|last=Ogrenci-Memik|first=Seda|publisher=The Institution of Engineering and Technology|year=2015|isbn=9781849199353|location=London, United Kingdom|oclc=934678500}}</ref>{{Rp|1}} The power densities of high speed integrated circuits, particularly microprocessors and including SoCs, have become highly uneven. Too much waste heat can damage circuits and erode [[Reliability (semiconductor)|reliability]] of the circuit over time. High temperatures and thermal stress negatively impact reliability, [[stress migration]], decreased [[mean time between failures]], [[electromigration]], [[wire bonding]], [[Metastability (electronics)|metastability]] and other performance degradation of the SoC over time.<ref name=":2" />{{Rp|2–9}}
In particular, most SoCs are in a small physical area or volume and therefore the effects of waste heat are compounded because there is little room for it to diffuse out of the system. Because of high [[transistor count]]s on modern devices due to [[Moore's law]], oftentimes a layout of sufficient throughput and high [[Transistors density|transistor density]] is physically realizable from [[Semiconductor device fabrication|fabrication processes]] but would result in unacceptably high amounts of heat in the circuit's volume.<ref name=":2" />{{Rp|1}}
These thermal effects force SoC and other chip designers to apply conservative [[design margin]]s, creating less performant devices to mitigate the risk of [[catastrophic failure]]. Due to increased [[Transistors density|transistor densities]] as length scales get smaller, each [[Semiconductor node|process generation]] produces more heat output than the last. Compounding this problem, SoC architectures are usually heterogeneous, creating spatially inhomogeneous [[heat flux]]es, which cannot be effectively mitigated by uniform [[passive cooling]].<ref name=":2" />{{Rp|1}}
==== Throughput ====
{{Expand section|date=October 2018}}
SoCs are optimized to maximize computational and communications [[throughput]].
==== Latency ====
{{Expand section|date=October 2018}}
SoCs are optimized to minimize [[Latency (engineering)|latency]] for some or all of their functions. This can be accomplished by [[Integrated circuit layout|laying out]] elements with proper proximity and [[Locality of reference|locality]] to each-other to minimize the interconnection delays and maximize the speed at which data is communicated between modules, [[Execution unit|functional units]] and memories. In general, optimizing to minimize latency is an [[NP-completeness|NP-complete]] problem equivalent to the [[boolean satisfiability problem]].
For [[Task (computing)|tasks]] running on processor cores, latency and throughput can be improved with [[Scheduling (computing)|task scheduling]]. Some tasks run in application-specific hardware units, however, and even task scheduling may not be sufficient to optimize all software-based tasks to meet timing and throughput constraints.
=== Methodologies ===
{{Further|Multi-objective optimization|Multiple-criteria decision analysis|Architecture tradeoff analysis method|label3=Architecture tradeoff analysis}}
{{Expand section|date=October 2018|small=no}}
Systems on chip are modeled with standard hardware [[verification and validation]] techniques, but additional techniques are used to model and optimize SoC design alternatives to make the system optimal with respect to [[multiple-criteria decision analysis]] on the above optimization targets.
==== Task scheduling ====
[[Scheduling (computing)|Task scheduling]] is an important activity in any computer system with multiple [[Process (computing)|processes]] or [[Thread (computing)|threads]] sharing a single processor core. It is important to reduce {{Section link||Latency|nopage=y}} and increase {{Section link||Throughput|nopage=y}} for [[embedded software]] running on an SoC's {{Section link||Processor cores|nopage=y}}. Not every important computing activity in a SoC is performed in software running on on-chip processors, but scheduling can drastically improve performance of software-based tasks and other tasks involving [[shared resource]]s.
SoCs often schedule tasks according to [[network scheduling]] and [[Stochastic scheduling|randomized scheduling]] algorithms.
==== Pipelining ====
{{Broader|Pipeline (computing)}}
Hardware and software tasks are often pipelined in [[processor design]]. Pipelining is an important principle for [[speedup]] in [[computer architecture]]. They are frequently used in [[GPU]]s ([[graphics pipeline]]) and RISC processors (evolutions of the [[classic RISC pipeline]]), but are also applied to application-specific tasks such as [[digital signal processing]] and multimedia manipulations in the context of SoCs.<ref name=":1" />
==== Probabilistic modeling ====
SoCs are often analyzed though [[probabilistic model]]s, {{Section link|Queueing theory|Queueing networks}} and [[Markov chain]]s. For instance, [[Little's law]] allows SoC states and NoC buffers to be modeled as arrival processes and analyzed through [[Poisson random variable]]s and [[Poisson process]]es.
==== Markov chains ====
SoCs are often modeled with [[Markov chain]]s, both [[Markov chain#Discrete-time Markov chain|discrete time]] and [[Markov chain#Continuous-time Markov chain|continuous time]] variants. Markov chain modeling allows [[asymptotic analysis]] of the SoC's [[Markov chain#Steady-state analysis and limiting distributions|steady state distribution]] of power, heat, latency and other factors to allow design decisions to be optimized for the common case.
== Fabrication ==
{{More citations needed section|date=March 2017}}{{See|Semiconductor device fabrication}}
SoC chips are typically [[semiconductor device fabrication|fabricated]] using [[metal–oxide–semiconductor]] (MOS) technology.<ref>{{cite book |last1=Lin |first1=Youn-Long Steve |title=Essential Issues in SOC Design: Designing Complex Systems-on-Chip |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9781402053528 |page=176 |url=https://books.google.com/books?id=7OV9lEn9LiQC&pg=PA176}}</ref> The netlists described above are used as the basis for the physical design ([[place and route]]) flow to convert the designers' intent into the design of the SoC. Throughout this conversion process, the design is analyzed with static timing modeling, simulation and other tools to ensure that it meets the specified operational parameters such as frequency, power consumption and dissipation, functional integrity (as described in the register transfer level code) and electrical integrity.
When all known bugs have been rectified and these have been re-verified and all physical design checks are done, the physical design files describing each layer of the chip are sent to the foundry's mask shop where a full set of glass lithographic masks will be etched. These are sent to a wafer fabrication plant to create the SoC dice before packaging and testing.
SoCs can be fabricated by several technologies, including:
* [[Full custom]] ASIC
* [[Standard cell]] ASIC
* [[Field-programmable gate array]] (FPGA)
ASICs consume less power and are faster than FPGAs but cannot be reprogrammed and are expensive to manufacture. FPGA designs are more suitable for lower volume designs, but after enough units of production ASICs reduce the total cost of ownership.<ref>{{Cite web|url=https://numato.com/blog/differences-between-fpga-and-asics/|title=FPGA vs ASIC: Differences between them and which one to use? – Numato Lab Help Center|website=numato.com|language=en-US|access-date=2018-10-17}}</ref>
SoC designs consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. With fewer packages in the system, assembly costs are reduced as well.
However, like most [[very-large-scale integration]] (VLSI) designs, the total cost{{Clarify|reason=what kind of cost?|date=May 2018}} is higher for one large chip than for the same functionality distributed over several smaller chips, because of [[Semiconductor device fabrication#Device test|lower yields]]{{Clarify|reason=confusing to non-experts|date=May 2018}} and higher [[non-recurring engineering]] costs.
When it is not feasible to construct an SoC for a particular application, an alternative is a [[system in package]] (SiP) comprising a number of chips in a single [[chip carrier|package]]. When produced in large volumes, SoC is more cost-effective than SiP because its packaging is simpler.<ref>[[EE Times]]. "[http://www.eetimes.com/document.asp?doc_id=1153043 The Great Debate: SOC vs. SIP]." March 21, 2005. Retrieved July 28, 2015.</ref> Another reason SiP may be preferred is [[waste heat]] may be too high in a SoC for a given purpose because functional components are too close together, and in an SiP heat will dissipate better from different functional modules since they are physically further apart.
== Benchmarks ==
{{Expand section|date=October 2018}}
SoC [[research and development]] often compares many options. Benchmarks, such as COSMIC,<ref>{{Cite web|url=http://www.ece.ust.hk/~eexu/COSMIC.html|title=COSMIC|website=www.ece.ust.hk|access-date=2018-10-08}}</ref> are developed to help such evaluations.
== See also ==
* [[List of system-on-a-chip suppliers]]
* [[Post-silicon validation]]
* [[ARM architecture]]
* [[Single-board computer]]
* [[System in package]]
* [[Network on a chip]]
* [[Programmable system-on-chip|Programmable SoC]]
* [[Application-specific instruction set processor]] (ASIP)
* [[Platform-based design]]
* [[Lab on a chip]]
* [[Organ on a chip]] in biomedical technology
* [[Multi-chip module]]
* [[List of Qualcomm Snapdragon processors]] - [[Qualcomm]]
* [[Exynos]] - [[Samsung]]
== Notes ==
{{reflist|group=nb}}
== References ==
{{reflist}}
== Further reading ==
* {{cite book |editor1-first=Wael |editor1-last=Badawy |editor2-first=Graham A. |editor2-last=Jullien |year=2003 |title=System-on-Chip for Real-Time Applications |series=Kluwer international series in engineering and computer science, SECS 711 |publisher=[[Wolters Kluwer|Kluwer Academic Publishers]] |location=Boston |isbn=9781402072543 |oclc=50478525 |url=https://books.google.com/books?id=Ha76NqrqPVIC}} 465 pages.
* {{cite book |author=Furber, Stephen B. |title=ARM system-on-chip architecture |publisher=Addison-Wesley |location=Boston |year=2000 |isbn=0-201-67519-6 |title-link=ARM system-on-chip architecture }}
* {{Cite book|title=Network-on-chip: the Next Generation of System-on-Chip Integration|last=Kundu|first=Santanu|last2=Chattopadhyay|first2=Santanu|publisher=CRC Press|year=2014|isbn=9781466565272|edition=1st|location=Boca Raton, FL|oclc=895661009}}
== External links ==
<!-- Follow [[WP:EL]] guidelines before adding anything to this section -->
* [http://www.ieee-socc.org/ SOCC] Annual [[Institute of Electrical and Electronics Engineers|IEEE]] International SoC Conference
* [http://www.edautils.com/Baya.html Baya] free SoC platform assembly and IP integration tool
*[http://www.eng.auburn.edu/~nelson/courses/elec5260_6260/Systems%20on%20Chip%20(SoC).pdf Systems on Chip for Embedded Applications], [[Auburn University]] seminar in [[Very-large-scale integration|VLSI]]
* [http://www.fpga-cores.com/instant-soc/ Instant SoC] SoC for FPGAs defined by C++
{{Systems on chip}}{{CPU technologies}}
{{Single-board computer}}
{{Programmable Logic}}
{{Computer science}}
{{Hardware acceleration}}
[[Category:System on a chip| ]]
[[Category:Computer engineering]]
[[Category:Electronic design]]
[[Category:Microtechnology]]
[[Category:Hardware acceleration]]
[[Category:Computer systems]]
[[Category:Application-specific integrated circuits]]' |
New page wikitext, after the edit (new_wikitext) | '{{Short description|Integrated circuit that incorporates the components of a computer}}
{{Use American English|date=October 2018}}
[[File:Raspberry Pi 4 Model B - Top.jpg|thumb|The Raspberry Pi uses a system on a chip as an almost fully contained microcomputer. This SoC does not contain any kind of data storage, which is common for a microprocessor SoC.]]
A '''system on a chip''' ('''SoC'''; {{IPAc-en|ˌ|ɛ|s|ˌ|oʊ|ˈ|s|iː|}} {{respell|es|oh|SEE}} or {{IPAc-en|s|ɒ|k}} {{respell|sock}}) is an integrated circuit (also known as a "chip") that integrates all or most components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory, input/output ports and secondary storage, often alongside other components such as radio modems and a graphics processing unit (GPU) – all on a single substrate or microchip. It may contain digital, analog, mixed-signal, and often radio frequency signal processing functions (otherwise it is considered only an application processor).
Higher-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (almost always LPDDR and eUFS or eMMC, respectively) chips, that may be layered on top of the SoC in what's known as a package on package (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may use separate wireless modems.
SoCs are in contrast to the common traditional motherboard-based PC architecture, which separates components based on function and connects them through a central interfacing circuit board. Whereas a motherboard houses and connects detachable or replaceable components, SoCs integrate all of these components into a single integrated circuit. An SoC will typically integrate a CPU, graphics and memory interfaces, hard-disk and USB connectivity, random-access and read-only memories and secondary storage and/or their controllers on a single circuit die, whereas a motherboard would connect these modules as discrete components or expansion cards.
An SoC integrates a microcontroller, microprocessor or perhaps several processor cores with peripherals like a GPU, Wi-Fi and cellular network radio modems, and/or one or more coprocessors. Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with even more advanced peripherals. {{Selfref inline|For an overview of integrating system components, see [[system integration]].}}
More tightly integrated computer system designs improve performance and reduce power consumption as well as semiconductor die area than multi-chip designs with equivalent functionality. This comes at the cost of reduced replaceability of components. By definition, SoC designs are fully or nearly fully integrated across different component modules. For these reasons, there has been a general trend towards tighter integration of components in the computer hardware industry, in part due to the influence of SoCs and lessons learned from the mobile and embedded computing markets. SoCs can be viewed as part of a larger trend towards embedded computing and hardware acceleration.
SoCs are very common in the mobile computing (such as in smartphones and tablet computers) and edge computing markets. They are also commonly used in embedded systems such as WiFi routers and the Internet of Things.
== Types ==
[[Image:ARMSoCBlockDiagram.svg|right|275px|thumbnail|[[Microcontroller]]-based system on a chip]]In general, there are four distinguishable types of SoCs:
* SoCs built around a [[microcontroller]],
* SoCs built around a [[microprocessor]], often found in mobile phones;
* Specialized [[application-specific integrated circuit]] SoCs designed for specific applications that do not fit into the above two categories, and
* [[Programmable system-on-chip|Programmable SoCs]] (PSoC), where most functionality is fixed but some functionality is [[reconfigurable computing|reprogrammable]] in a manner analogous to a [[field-programmable gate array]].
[[File:KL AMD Am286LX ZX.jpg|thumb|[[AMD]] Am286ZX/LX, SoC based on [[Intel 80286]] ]]
== Applications ==
SoCs can be applied to any computing task. However, they are typically used in mobile computing such as tablets, smartphones, smartwatches and netbooks as well as [[embedded system]]s and in applications where previously [[microcontroller]]s would be used.
=== Embedded systems ===
Where previously only microcontrollers could be used, SoCs are rising to prominence in the embedded systems market. Tighter system integration offers better reliability and [[Mean time between failures|mean time between failure]], and SoCs offer more advanced functionality and computing power than microcontrollers.<ref>{{Cite news|url=https://www.embedded.com/design/mcus-processors-and-socs/4419584/Is-a-single-chip-SOC-processor-right-for-your-embedded-project-|title=Is a single-chip SOC processor right for your embedded project?|work=Embedded|access-date=2018-10-13|language=en}}</ref> Applications include [[AI accelerator|AI acceleration]], embedded [[machine vision]],<ref>{{Cite web|url=https://www.imveurope.com/news/qualcomm-launches-socs-embedded-vision|title=Qualcomm launches SoCs for embedded vision {{!}} Imaging and Machine Vision Europe|website=www.imveurope.com|language=en|access-date=2018-10-13}}</ref> data collection, [[telemetry]], vector processing and [[ambient intelligence]]. Often embedded SoCs target the [[internet of things]], [[Internet of things|industrial internet of things]] and [[edge computing]] markets.
=== Mobile computing ===
[[Mobile computing]] based SoCs always bundle processors, memories, on-chip [[Cache (computing)|caches]], [[wireless networking]] capabilities and often [[digital camera]] hardware and firmware. With increasing memory sizes, high end SoCs will often have no memory and flash storage and instead, the memory and [[flash memory]] will be placed right next to, or above ([[package on package]]), the SoC.<ref>{{Cite web|url=https://www.ifixit.com/Teardown/Samsung+Galaxy+S10+and+S10e+Teardown/120331|title=Samsung Galaxy S10 and S10e Teardown|date=March 6, 2019|website=iFixit}}</ref> Some examples of mobile computing SoCs include:
* [[Samsung Electronics]]: [[List of Samsung System on Chips|list]], typically based on [[ARM architecture|ARM]]
** [[Exynos]], used mainly by Samsung's [[Samsung Galaxy|Galaxy]] series of smartphones
* [[Qualcomm]]:
** [[Qualcomm Snapdragon|Snapdragon]] ([[List of Qualcomm Snapdragon systems-on-chip|list]]), used in many [[LG Corporation|LG]], [[Xiaomi]], [[Google Pixel]], [[HTC]] and Samsung Galaxy smartphones. In 2018, Snapdragon SoCs are being used as the backbone of [[Laptop|laptop computers]] running [[Windows 10]], marketed as "Always Connected PCs".<ref name=":3">{{Cite news|url=https://www.windowscentral.com/arm-going-after-intel-new-chip-roadmap-through-2020|title=ARM is going after Intel with new chip roadmap through 2020|work=Windows Central|access-date=2018-10-06|language=en}}</ref><ref name=":4">{{Cite web|url=https://www.microsoft.com/en-us/windows/always-connected-laptop-pcs|title=Always Connected PCs, Extended Battery Life 4G LTE Laptops {{!}} Windows|website=www.microsoft.com|language=en-us|access-date=2018-10-06}}</ref>
=== Personal computers ===
In 1992, [[Acorn Computers]] produced the [[Acorn Archimedes#New range and a laptop|A3010, A3020 and A4000 range of personal computers]] with the ARM250 SoC. It combined the original Acorn ARM2 processor with a memory controller (MEMC), video controller (VIDC), and I/O controller (IOC). In previous Acorn [[ARM architecture|ARM]]-powered computers, these were four discrete chips. The ARM7500 chip was their second-generation SoC, based on the ARM700, VIDC20 and IOMD controllers, and was widely licensed in embedded devices such as set-top-boxes, as well as later Acorn personal computers.
SoCs are being applied to mainstream [[personal computer]]s as of 2018.<ref name=":3" /> They are particularly applied to [[laptop]]s and [[Tablet computer|tablet PCs]]. Tablet and laptop manufacturers have learned lessons from embedded systems and smartphone markets about reduced power consumption, better performance and reliability from tighter [[System integration|integration]] of hardware and [[firmware]] [[Module system|modules]], and [[LTE (telecommunication)|LTE]] and other [[wireless network]] communications integrated on chip (integrated [[network interface controller]]s).<ref>{{Cite news|url=https://www.qualcomm.com/products/modems|title=Gigabit Class LTE, 4G LTE and 5G Cellular Modems {{!}} Qualcomm|work=Qualcomm|access-date=2018-10-13|language=en}}</ref>
[[ARM architecture|ARM]]-based:
* [[Qualcomm Snapdragon]]<ref name=":4" />
* ARM250
* ARM7500(FE)
* [[Apple M1]]
[[x86]]-based:
* [[Intel Core]] [[CULV]]
== Structure ==
An SoC consists of hardware [[functional unit]]s, including [[microprocessor]]s that run [[Computer program|software code]], as well as a [[communications subsystem]] to connect, control, direct and interface between these functional modules.
=== Functional components ===
==== Processor cores ====
An SoC must have at least one [[processor core]], but typically an SoC has more than one core. Processor cores can be a [[microcontroller]], [[microprocessor]] (μP),<ref name="Furber ARM">{{Cite book|title=ARM system-on-chip architecture|last=Furber|first=Stephen B.|publisher=Addison-Wesley|year=2000|isbn=0201675196|location=Harlow, England|oclc=44267964}}</ref> [[digital signal processor]] (DSP) or [[application-specific instruction set processor]] (ASIP) core.<ref name=":1">{{Cite book|title=Pipelined Multiprocessor System-on-Chip for Multimedia|publisher=[[Springer-Verlag|Springer]]|year=2014|isbn=9783319011134|oclc=869378184|authors=Haris Javaid, Sri Parameswaran}}</ref> ASIPs have [[Instruction set architecture|instruction sets]] that are customized for an [[application domain]] and designed to be more efficient than general-purpose instructions for a specific type of workload. [[Multi-processor system-on-chip|Multiprocessor SoCs]] have more than one processor core by definition.
Whether single-core, [[Multi-core processor|multi-core]] or [[manycore]], SoC processor cores typically use [[Reduced instruction set computer|RISC]] instruction set architectures. RISC architectures are advantageous over [[Complex instruction set computer|CISC]] processors for SoCs because they require less digital logic, and therefore less power and area on [[Die (integrated circuit)|board]], and in the [[Embedded system|embedded]] and [[mobile computing]] markets, area and power are often highly constrained. In particular, SoC processor cores often use the [[ARM architecture]] because it is a [[Soft microprocessor|soft processor]] specified as an [[IP core]] and is more power efficient than [[x86]].<ref name="Furber ARM" />
==== Memory ====
{{Further|Computer memory}}
SoCs must have [[semiconductor memory]] blocks to perform their computation, as do [[microcontroller]]s and other [[embedded system]]s. Depending on the application, SoC memory may form a [[memory hierarchy]] and [[cache hierarchy]]. In the mobile computing market, this is common, but in many [[Low-power electronics|low-power]] embedded microcontrollers, this is not necessary. Memory technologies for SoCs include [[read-only memory]] (ROM), [[random-access memory]] (RAM), Electrically Erasable Programmable ROM ([[EEPROM]]) and [[flash memory]].<ref name="Furber ARM" /> As in other computer systems, RAM can be subdivided into relatively faster but more expensive [[Static random-access memory|static RAM]] (SRAM) and the slower but cheaper [[Dynamic random-access memory|dynamic RAM]] (DRAM). When an SoC has a [[Cache (computing)|cache]] hierarchy, SRAM will usually be used to implement [[processor register]]s and cores' [[L1 cache]]s whereas DRAM will be used for lower levels of the cache hierarchy including [[main memory]]. "Main memory" may be specific to a single processor (which can be [[Multi-core processor|multi-core]]) when the SoC [[Multi-processor system-on-chip|has multiple processors]], in which case it is [[distributed memory]] and must be sent via {{Section link||Intermodule communication|nopage=y}} on-chip to be accessed by a different processor.<ref name=":1" /> For further discussion of multi-processing memory issues, see [[cache coherence]] and [[memory latency]].
==== Interfaces ====
SoCs include external [[Electrical connector|interfaces]], typically for [[communication protocol]]s. These are often based upon industry standards such as [[USB]], [[FireWire]], [[Ethernet]], [[Universal synchronous and asynchronous receiver-transmitter|USART]], [[Serial Peripheral Interface|SPI]], [[HDMI]], [[I²C]], etc. These interfaces will differ according to the intended application. [[Wireless network]]ing protocols such as [[Wi-Fi]], [[Bluetooth]], [[6LoWPAN]] and [[near-field communication]] may also be supported.
When needed, SoCs include [[Analog signal|analog]] interfaces including [[Analog-to-digital converter|analog-to-digital]] and [[digital-to-analog converter]]s, often for [[signal processing]]. These may be able to interface with different types of [[sensor]]s or [[actuator]]s, including [[smart transducer]]s. They may interface with application-specific [[Modularity|modules]] or shields.<ref group="nb">In [[embedded system]]s, "shields" are analogous to [[expansion card]]s for [[Personal computer|PCs]]. They often fit over a [[microcontroller]] such as an [[Arduino]] or [[single-board computer]] such as the [[Raspberry Pi]] and function as [[peripheral]]s for the device.</ref> Or they may be internal to the SoC, such as if an analog sensor is built in to the SoC and its readings must be converted to digital signals for mathematical processing.
==== Digital signal processors ====
[[Digital signal processor]] (DSP) cores are often included on SoCs. They perform [[signal processing]] operations in SoCs for [[sensor]]s, [[actuator]]s, [[data collection]], [[data analysis]] and multimedia processing. DSP cores typically feature [[very long instruction word]] (VLIW) and [[SIMD|single instruction, multiple data]] (SIMD) [[instruction set architecture]]s, and are therefore highly amenable to exploiting [[instruction-level parallelism]] through [[Parallel processing (DSP implementation)|parallel processing]] and [[superscalar execution]].<ref name=":1" />{{Rp|4}} DSP cores most often feature application-specific instructions, and as such are typically [[application-specific instruction-set processor]]s (ASIP). Such application-specific instructions correspond to dedicated hardware [[functional unit]]s that compute those instructions.
Typical DSP instructions include [[Multiply–accumulate operation|multiply-accumulate]], [[Fast Fourier transform]], [[Fused multiply-accumulate|fused multiply-add]], and [[convolution]]s.
==== Other ====
As with other computer systems, SoCs require [[Clock generator|timing sources]] to generate [[clock signal]]s, control execution of SoC functions and provide time context to [[signal processing]] applications of the SoC, if needed. Popular time sources are [[crystal oscillators]] and [[phase-locked loop]]s.
SoC [[peripheral]]s including [[counter (digital)|counter]]-timers, real-time [[timer]]s and [[power-on reset]] generators. SoCs also include [[voltage regulator]]s and [[power management]] circuits.
=== Intermodule communication ===
SoCs comprise many [[execution unit]]s. These units must often send [[data]] and [[Instruction (computing)|instructions]] back and forth. Because of this, all but the most trivial SoCs require [[Communications system|communications subsystems]]. Originally, as with other [[microcomputer]] technologies, [[Bus (computing)|data bus]] architectures were used, but recently designs based on sparse intercommunication networks known as [[Network on a chip|networks-on-chip]] (NoC) have risen to prominence and are forecast to overtake bus architectures for SoC design in the near future.<ref name=":0">{{Cite book|title=Network-on-chip: the Next Generation of System-on-Chip Integration|last=Kundu|first=Santanu|last2=Chattopadhyay|first2=Santanu|publisher=CRC Press|year=2014|isbn=9781466565272|edition=1st|location=Boca Raton, FL|oclc=895661009}}</ref>
==== Bus-based communication ====
Historically, a shared global [[bus (computing)|computer bus]] typically connected the different components, also called "blocks" of the SoC.<ref name=":0" /> A very common bus for SoC communications is ARM's royalty-free Advanced Microcontroller Bus Architecture ([[Advanced Microcontroller Bus Architecture|AMBA]]) standard.
[[Direct memory access]] controllers route data directly between external interfaces and SoC memory, bypassing the CPU or [[control unit]], thereby increasing the data [[throughput]] of the SoC. This is similar to some [[device driver]]s of peripherals on component-based [[multi-chip module]] PC architectures.
Computer buses are limited in [[scalability]], supporting only up to tens of cores ([[multicore]]) on a single chip.<ref name=":0" />{{Rp|xiii}} Wire delay is not scalable due to continued [[miniaturization]], [[Computer performance|system performance]] does not scale with the number of cores attached, the SoC's [[operating frequency]] must decrease with each additional core attached for power to be sustainable, and long wires consume large amounts of electrical power. These challenges are prohibitive to supporting [[manycore]] systems on chip.<ref name=":0" />{{Rp|xiii}}
==== Network on a chip ====
{{Main|Network on a chip}}
In the late [[2010s]], a trend of SoCs implementing [[communications subsystem]]s in terms of a network-like topology instead of [[bus (computing)|bus-based]] protocols has emerged. A trend towards [[Multi-processor system-on-chip|more processor cores on SoCs]] has caused on-chip communication efficiency to become one of the key factors in determining the overall system performance and cost.<ref name=":0" />{{Rp|xiii}} This has led to the emergence of interconnection networks with [[Router (computing)|router]]-based [[packet switching]] known as "[[network on a chip|networks on chip]]" (NoCs) to overcome the [[Bottleneck (engineering)|bottlenecks]] of bus-based networks.<ref name=":0" />{{Rp|xiii}}
Networks-on-chip have advantages including destination- and application-specific [[routing]], greater power efficiency and reduced possibility of [[bus contention]]. Network-on-chip architectures take inspiration from [[communication protocols]] like [[Transmission Control Protocol|TCP]] and the [[Internet protocol suite]] for on-chip communication,<ref name=":0" /> although they typically have fewer [[network layer]]s. Optimal network-on-chip [[network architecture]]s are an ongoing area of much research interest. NoC architectures range from traditional distributed computing [[Network topology|network topologies]] such as [[Torus interconnect|torus]], [[Hypercube internetwork topology|hypercube]], [[Mesh networking|meshes]] and [[tree network]]s to [[genetic algorithm scheduling]] to [[randomized algorithm]]s such as [[Branching random walk|random walks with branching]] and randomized [[time to live]] (TTL).
Many SoC researchers consider NoC architectures to be the future of SoC design because they have been shown to efficiently meet power and throughput needs of SoC designs. Current NoC architectures are two-dimensional. 2D IC design has limited [[Floorplan (microelectronics)|floorplanning]] choices as the number of cores in SoCs increase, so as [[three-dimensional integrated circuit]]s (3DICs) emerge, SoC designers are looking towards building three-dimensional on-chip networks known as 3DNoCs.<ref name=":0" />
== Design flow ==
{{More citations needed section|date=March 2017}}
{{Main|Design flow (EDA)|Physical design (electronics)|Platform-based design|l1=Electronics design flow|l3=}}{{See also|Systems design|Software design|label 2=Software design process}}[[Image:SoCDesignFlow.svg|275px|thumbnail|SoC design flow|alt=]]
A system on a chip consists of both the [[electronic hardware|hardware]], described in {{Section link||Structure|nopage=y}}, and the [[software]] controlling the microcontroller, microprocessor or digital signal processor cores, peripherals and interfaces. The [[design flow (EDA)|design flow]] for an SoC aims to develop this hardware and software at the same time, also known as architectural co-design. The design flow must also take into account optimizations ({{Section link||Optimization goals|nopage=y}}) and constraints.
Most SoCs are developed from pre-qualified hardware component [[Semiconductor intellectual property core|IP core specifications]] for the hardware elements and [[execution unit]]s, collectively "blocks", described above, together with software [[device driver]]s that may control their operation. Of particular importance are the [[protocol stack]]s that drive industry-standard interfaces like [[Universal Serial Bus|USB]]. The hardware blocks are put together using [[computer-aided design]] tools, specifically [[electronic design automation]] tools; the [[modular programming|software modules]] are integrated using a software [[integrated development environment]].
SoCs components are also often designed in [[high-level programming language]]s such as [[C++]], [[MATLAB]] or [[SystemC]] and converted to [[Register-transfer level|RTL]] designs through [[high-level synthesis]] (HLS) tools such as [[C to HDL]] or [[flow to HDL]].<ref>{{Cite news|url=http://www.eejournal.com/archives/articles/20110825-mathworks/|title=Best Practices for FPGA Prototyping of MATLAB and Simulink Algorithms|date=2011-08-25|work=EEJournal|access-date=2018-10-08|language=en-US}}</ref> HLS products called "algorithmic synthesis" allow designers to use C++ to model and synthesize system, circuit, software and verification levels all in one high level language commonly known to [[computer engineers]] in a manner independent of time scales, which are typically specified in HDL.<ref>{{Cite web|url=https://www.eetimes.com/document.asp?doc_id=1271261|title=The 'why' and 'what' of algorithmic synthesis|last=Bowyer|first=Bryan|date=2005-02-05|website=[[EE Times]]|access-date=2018-10-08}}</ref> Other components can remain software and be compiled and embedded onto [[Soft microprocessor|soft-core processors]] included in the SoC as modules in HDL as [[Semiconductor intellectual property core|IP cores]].
Once the [[Computer architecture|architecture]] of the SoC has been defined, any new hardware elements are written in an abstract [[hardware description language]] termed [[Register-transfer level|register transfer level]] (RTL) which defines the circuit behavior, or synthesized into RTL from a high level language through high-level synthesis. These elements are connected together in a hardware description language to create the full SoC design. The logic specified to connect these components and convert between possibly different interfaces provided by different vendors is called [[glue logic]].
=== Design verification ===
{{Further|Functional verification|Signoff (electronic design automation)||label2=}}
Chips are verified for validation correctness before being sent to a [[Semiconductor fabrication plant|semiconductor foundry]]. This process is called [[functional verification]] and it accounts for a significant portion of the time and energy expended in the [[Integrated circuit development|chip design life cycle]], often quoted as 70%.<ref name="70% verification?">[[EE Times]]. "[http://www.eetimes.com/author.asp?section_id=36&doc_id=1264922 Is verification really 70 percent?]." June 14, 2004. Retrieved July 28, 2015.</ref><ref name="verification vs. validation">{{cite web|url=http://www.softwaretestingclass.com/difference-between-verification-and-validation/|title=Difference between Verification and Validation|work=Software Testing Class|access-date=2018-04-30|quote=In interviews most of the interviewers are asking questions on “What is Difference between Verification and Validation?” Many people use verification and validation interchangeably but both have different meanings.}}</ref> With the growing complexity of chips, [[hardware verification language]]s like [[SystemVerilog]], [[SystemC]], [[e (verification language)|e]], and [[OpenVera]] are being used. [[Software bug|Bugs]] found in the verification stage are reported to the designer.
Traditionally, engineers have employed simulation acceleration, [[emulator|emulation]] or prototyping on [[Reconfigurable computing|reprogrammable hardware]] to verify and debug hardware and software for SoC designs prior to the finalization of the design, known as [[tape-out]]. [[Field-programmable gate array]]s (FPGAs) are favored for prototyping SoCs because [[FPGA prototyping|FPGA prototypes]] are reprogrammable, allow [[debugging]] and are more flexible than [[application-specific integrated circuit]]s (ASICs).<ref name="nm prototyping">{{Cite web|url=http://www.tayden.com/publications/Nanometer%20Prototyping.pdf|title=Nanometer prototyping|last=Rittman|first=Danny|date=2006-01-05|website=Tayden Design|access-date=2018-10-07}}</ref><ref name="Reason to debug in FPGA">{{Cite web|url=http://www.design-reuse.com/articles/13550/fpga-prototyping-to-structured-asic-production-to-reduce-cost-risk-ttm.html|title=FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk & TTM|website=Design And Reuse|access-date=2018-10-07}}</ref>
With high capacity and fast compilation time, simulation acceleration and emulation are powerful technologies that provide wide visibility into systems. Both technologies, however, operate slowly, on the order of MHz, which may be significantly slower – up to 100 times slower – than the SoC's operating frequency. Acceleration and emulation boxes are also very large and expensive at over US$1 million.{{Citation needed|date=May 2018}}
FPGA prototypes, in contrast, use FPGAs directly to enable engineers to validate and test at, or close to, a system's full operating frequency with real-world stimuli. Tools such as Certus<ref>Brian Bailey, EE Times. "[http://www.eetimes.com/document.asp?doc_id=1317504 Tektronix hopes to shake up ASIC prototyping]." October 30, 2012. Retrieved July 28, 2015.</ref> are used to insert probes in the FPGA RTL that make signals available for observation. This is used to debug hardware, firmware and software interactions across multiple FPGAs with capabilities similar to a logic analyzer.
In parallel, the hardware elements are grouped and passed through a process of [[logic synthesis]], during which performance constraints, such as operational frequency and expected signal delays, are applied. This generates an output known as a [[netlist]] describing the design as a physical circuit and its interconnections. These netlists are combined with the [[glue logic]] connecting the components to produce the schematic description of the SoC as a circuit which can be [[printed circuit board|printed]] onto a chip. This process is known as [[place and route]] and precedes [[tape-out]] in the event that the SoCs are produced as [[application-specific integrated circuit]]s (ASIC).
== Optimization goals ==
SoCs must optimize [[Power consumption|power use]], area on [[Die (integrated circuit)|die]], communication, positioning for [[Locality of reference|locality]] between modular units and other factors. Optimization is necessarily a design goal of SoCs. If optimization was not necessary, the engineers would use a [[multi-chip module]] architecture without accounting for the area utilization, power consumption or performance of the system to the same extent.
Common optimization targets for SoC designs follow, with explanations of each. In general, optimizing any of these quantities may be a hard [[combinatorial optimization]] problem, and can indeed be [[NP-hardness|NP-hard]] fairly easily. Therefore, sophisticated [[optimization algorithm]]s are often required and it may be practical to use [[approximation algorithm]]s or [[Heuristic (computer science)|heuristics]] in some cases. Additionally, most SoC designs contain [[Multivariate optimization|multiple variables to optimize simultaneously]], so [[Pareto efficiency|Pareto efficient]] solutions are sought after in SoC design. Oftentimes the goals of optimizing some of these quantities are directly at odds, further adding complexity to design optimization of SoCs and introducing [[Trade-off#Engineering|trade-offs]] in system design.
For broader coverage of trade-offs and [[requirements analysis]], see [[requirements engineering]].
=== Targets ===
==== Power consumption ====
SoCs are optimized to minimize the [[Electric power#Definition|electrical power]] used to perform the SoC's functions. Most SoCs must use low power. SoC systems often require long [[battery life]] (such as [[smartphone]]s), can potentially spending months or years without a power source needing to maintain autonomous function, and often are limited in power use by a high number of [[Embedded system|embedded]] SoCs being [[Distributed computing|networked together]] in an area. Additionally, energy costs can be high and conserving energy will reduce the [[total cost of ownership]] of the SoC. Finally, [[waste heat]] from high energy consumption can damage other circuit components if too much heat is dissipated, giving another pragmatic reason to conserve energy. The amount of [[energy]] used in a circuit is the [[integral]] of [[Power (physics)|power]] consumed with respect to time, and the [[Mean value theorem|average rate]] of power consumption is the product of [[Electric current|current]] by [[voltage]]. Equivalently, by [[Ohm's law]], power is current squared times resistance or voltage squared divided by [[Resistance (physics)|resistance]]:
<math display="block">P = IV = \frac{V^2}{R} = {I^2}{R}</math>SoCs are frequently embedded in [[Mobile device|portable devices]] such as [[smartphones]], [[GPS navigation device]]s, digital [[Digital watch|watches]] (including [[smartwatch]]es) and [[netbook]]s. Customers want long battery lives for [[mobile computing]] devices, another reason that power consumption must be minimized in SoCs. [[Multimedia application]]s are often executed on these devices, including [[video game]]s, [[video streaming]], [[image processing]]; all of which have grown in [[computational complexity]] in recent years with user demands and expectations for higher-[[Video quality|quality]] multimedia. Computation is more demanding as expectations move towards [[3D video]] at [[high resolution]] with [[List of video compression formats|multiple standards]], so SoCs performing multimedia tasks must be computationally capable platform while being low power to run off a standard mobile battery.<ref name=":1" />{{Rp|3}}
==== Performance per watt ====
{{See also|Green computing}}
SoCs are optimized to maximize [[power efficiency]] in performance per watt: maximize the performance of the SoC given a budget of power usage. Many applications such as [[edge computing]], [[distributed processing]] and [[ambient intelligence]] require a certain level of [[Computer performance|computational performance]], but power is limited in most SoC environments. The [[ARM architecture]] has greater performance per watt than [[x86]] in embedded systems, so it is preferred over x86 for most SoC applications requiring an [[Soft microprocessor|embedded processor]].
==== Waste heat ====
{{Main|Heat generation in integrated circuits}}{{See also|Thermal management (electronics)|Thermal design power|label 1=Thermal management in electronics}}
SoC designs are optimized to minimize [[waste heat]] [[dissipation|output]] on the chip. As with other [[integrated circuit]]s, heat generated due to high [[power density]] are the [[Bottleneck (engineering)|bottleneck]] to further [[miniaturization]] of components.<ref name=":2">{{Cite book|title=Heat Management in Integrated circuits: On-chip and system-level monitoring and cooling|last=Ogrenci-Memik|first=Seda|publisher=The Institution of Engineering and Technology|year=2015|isbn=9781849199353|location=London, United Kingdom|oclc=934678500}}</ref>{{Rp|1}} The power densities of high speed integrated circuits, particularly microprocessors and including SoCs, have become highly uneven. Too much waste heat can damage circuits and erode [[Reliability (semiconductor)|reliability]] of the circuit over time. High temperatures and thermal stress negatively impact reliability, [[stress migration]], decreased [[mean time between failures]], [[electromigration]], [[wire bonding]], [[Metastability (electronics)|metastability]] and other performance degradation of the SoC over time.<ref name=":2" />{{Rp|2–9}}
In particular, most SoCs are in a small physical area or volume and therefore the effects of waste heat are compounded because there is little room for it to diffuse out of the system. Because of high [[transistor count]]s on modern devices due to [[Moore's law]], oftentimes a layout of sufficient throughput and high [[Transistors density|transistor density]] is physically realizable from [[Semiconductor device fabrication|fabrication processes]] but would result in unacceptably high amounts of heat in the circuit's volume.<ref name=":2" />{{Rp|1}}
These thermal effects force SoC and other chip designers to apply conservative [[design margin]]s, creating less performant devices to mitigate the risk of [[catastrophic failure]]. Due to increased [[Transistors density|transistor densities]] as length scales get smaller, each [[Semiconductor node|process generation]] produces more heat output than the last. Compounding this problem, SoC architectures are usually heterogeneous, creating spatially inhomogeneous [[heat flux]]es, which cannot be effectively mitigated by uniform [[passive cooling]].<ref name=":2" />{{Rp|1}}
==== Throughput ====
{{Expand section|date=October 2018}}
SoCs are optimized to maximize computational and communications [[throughput]].
==== Latency ====
{{Expand section|date=October 2018}}
SoCs are optimized to minimize [[Latency (engineering)|latency]] for some or all of their functions. This can be accomplished by [[Integrated circuit layout|laying out]] elements with proper proximity and [[Locality of reference|locality]] to each-other to minimize the interconnection delays and maximize the speed at which data is communicated between modules, [[Execution unit|functional units]] and memories. In general, optimizing to minimize latency is an [[NP-completeness|NP-complete]] problem equivalent to the [[boolean satisfiability problem]].
For [[Task (computing)|tasks]] running on processor cores, latency and throughput can be improved with [[Scheduling (computing)|task scheduling]]. Some tasks run in application-specific hardware units, however, and even task scheduling may not be sufficient to optimize all software-based tasks to meet timing and throughput constraints.
=== Methodologies ===
{{Further|Multi-objective optimization|Multiple-criteria decision analysis|Architecture tradeoff analysis method|label3=Architecture tradeoff analysis}}
{{Expand section|date=October 2018|small=no}}
Systems on chip are modeled with standard hardware [[verification and validation]] techniques, but additional techniques are used to model and optimize SoC design alternatives to make the system optimal with respect to [[multiple-criteria decision analysis]] on the above optimization targets.
==== Task scheduling ====
[[Scheduling (computing)|Task scheduling]] is an important activity in any computer system with multiple [[Process (computing)|processes]] or [[Thread (computing)|threads]] sharing a single processor core. It is important to reduce {{Section link||Latency|nopage=y}} and increase {{Section link||Throughput|nopage=y}} for [[embedded software]] running on an SoC's {{Section link||Processor cores|nopage=y}}. Not every important computing activity in a SoC is performed in software running on on-chip processors, but scheduling can drastically improve performance of software-based tasks and other tasks involving [[shared resource]]s.
SoCs often schedule tasks according to [[network scheduling]] and [[Stochastic scheduling|randomized scheduling]] algorithms.
==== Pipelining ====
{{Broader|Pipeline (computing)}}
Hardware and software tasks are often pipelined in [[processor design]]. Pipelining is an important principle for [[speedup]] in [[computer architecture]]. They are frequently used in [[GPU]]s ([[graphics pipeline]]) and RISC processors (evolutions of the [[classic RISC pipeline]]), but are also applied to application-specific tasks such as [[digital signal processing]] and multimedia manipulations in the context of SoCs.<ref name=":1" />
==== Probabilistic modeling ====
SoCs are often analyzed though [[probabilistic model]]s, {{Section link|Queueing theory|Queueing networks}} and [[Markov chain]]s. For instance, [[Little's law]] allows SoC states and NoC buffers to be modeled as arrival processes and analyzed through [[Poisson random variable]]s and [[Poisson process]]es.
==== Markov chains ====
SoCs are often modeled with [[Markov chain]]s, both [[Markov chain#Discrete-time Markov chain|discrete time]] and [[Markov chain#Continuous-time Markov chain|continuous time]] variants. Markov chain modeling allows [[asymptotic analysis]] of the SoC's [[Markov chain#Steady-state analysis and limiting distributions|steady state distribution]] of power, heat, latency and other factors to allow design decisions to be optimized for the common case.
== Fabrication ==
{{More citations needed section|date=March 2017}}{{See|Semiconductor device fabrication}}
SoC chips are typically [[semiconductor device fabrication|fabricated]] using [[metal–oxide–semiconductor]] (MOS) technology.<ref>{{cite book |last1=Lin |first1=Youn-Long Steve |title=Essential Issues in SOC Design: Designing Complex Systems-on-Chip |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9781402053528 |page=176 |url=https://books.google.com/books?id=7OV9lEn9LiQC&pg=PA176}}</ref> The netlists described above are used as the basis for the physical design ([[place and route]]) flow to convert the designers' intent into the design of the SoC. Throughout this conversion process, the design is analyzed with static timing modeling, simulation and other tools to ensure that it meets the specified operational parameters such as frequency, power consumption and dissipation, functional integrity (as described in the register transfer level code) and electrical integrity.
When all known bugs have been rectified and these have been re-verified and all physical design checks are done, the physical design files describing each layer of the chip are sent to the foundry's mask shop where a full set of glass lithographic masks will be etched. These are sent to a wafer fabrication plant to create the SoC dice before packaging and testing.
SoCs can be fabricated by several technologies, including:
* [[Full custom]] ASIC
* [[Standard cell]] ASIC
* [[Field-programmable gate array]] (FPGA)
ASICs consume less power and are faster than FPGAs but cannot be reprogrammed and are expensive to manufacture. FPGA designs are more suitable for lower volume designs, but after enough units of production ASICs reduce the total cost of ownership.<ref>{{Cite web|url=https://numato.com/blog/differences-between-fpga-and-asics/|title=FPGA vs ASIC: Differences between them and which one to use? – Numato Lab Help Center|website=numato.com|language=en-US|access-date=2018-10-17}}</ref>
SoC designs consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. With fewer packages in the system, assembly costs are reduced as well.
However, like most [[very-large-scale integration]] (VLSI) designs, the total cost{{Clarify|reason=what kind of cost?|date=May 2018}} is higher for one large chip than for the same functionality distributed over several smaller chips, because of [[Semiconductor device fabrication#Device test|lower yields]]{{Clarify|reason=confusing to non-experts|date=May 2018}} and higher [[non-recurring engineering]] costs.
When it is not feasible to construct an SoC for a particular application, an alternative is a [[system in package]] (SiP) comprising a number of chips in a single [[chip carrier|package]]. When produced in large volumes, SoC is more cost-effective than SiP because its packaging is simpler.<ref>[[EE Times]]. "[http://www.eetimes.com/document.asp?doc_id=1153043 The Great Debate: SOC vs. SIP]." March 21, 2005. Retrieved July 28, 2015.</ref> Another reason SiP may be preferred is [[waste heat]] may be too high in a SoC for a given purpose because functional components are too close together, and in an SiP heat will dissipate better from different functional modules since they are physically further apart.
== Benchmarks ==
{{Expand section|date=October 2018}}
SoC [[research and development]] often compares many options. Benchmarks, such as COSMIC,<ref>{{Cite web|url=http://www.ece.ust.hk/~eexu/COSMIC.html|title=COSMIC|website=www.ece.ust.hk|access-date=2018-10-08}}</ref> are developed to help such evaluations.
== See also ==
* [[List of system-on-a-chip suppliers]]
* [[Post-silicon validation]]
* [[ARM architecture]]
* [[Single-board computer]]
* [[System in package]]
* [[Network on a chip]]
* [[Programmable system-on-chip|Programmable SoC]]
* [[Application-specific instruction set processor]] (ASIP)
* [[Platform-based design]]
* [[Lab on a chip]]
* [[Organ on a chip]] in biomedical technology
* [[Multi-chip module]]
* [[List of Qualcomm Snapdragon processors]] - [[Qualcomm]]
* [[Exynos]] - [[Samsung]]
== Notes ==
{{reflist|group=nb}}
== References ==
{{reflist}}
== Further reading ==
* {{cite book |editor1-first=Wael |editor1-last=Badawy |editor2-first=Graham A. |editor2-last=Jullien |year=2003 |title=System-on-Chip for Real-Time Applications |series=Kluwer international series in engineering and computer science, SECS 711 |publisher=[[Wolters Kluwer|Kluwer Academic Publishers]] |location=Boston |isbn=9781402072543 |oclc=50478525 |url=https://books.google.com/books?id=Ha76NqrqPVIC}} 465 pages.
* {{cite book |author=Furber, Stephen B. |title=ARM system-on-chip architecture |publisher=Addison-Wesley |location=Boston |year=2000 |isbn=0-201-67519-6 |title-link=ARM system-on-chip architecture }}
* {{Cite book|title=Network-on-chip: the Next Generation of System-on-Chip Integration|last=Kundu|first=Santanu|last2=Chattopadhyay|first2=Santanu|publisher=CRC Press|year=2014|isbn=9781466565272|edition=1st|location=Boca Raton, FL|oclc=895661009}}
== External links ==
<!-- Follow [[WP:EL]] guidelines before adding anything to this section -->
* [http://www.ieee-socc.org/ SOCC] Annual [[Institute of Electrical and Electronics Engineers|IEEE]] International SoC Conference
* [http://www.edautils.com/Baya.html Baya] free SoC platform assembly and IP integration tool
*[http://www.eng.auburn.edu/~nelson/courses/elec5260_6260/Systems%20on%20Chip%20(SoC).pdf Systems on Chip for Embedded Applications], [[Auburn University]] seminar in [[Very-large-scale integration|VLSI]]
* [http://www.fpga-cores.com/instant-soc/ Instant SoC] SoC for FPGAs defined by C++
{{Systems on chip}}{{CPU technologies}}
{{Single-board computer}}
{{Programmable Logic}}
{{Computer science}}
{{Hardware acceleration}}
[[Category:System on a chip| ]]
[[Category:Computer engineering]]
[[Category:Electronic design]]
[[Category:Microtechnology]]
[[Category:Hardware acceleration]]
[[Category:Computer systems]]
[[Category:Application-specific integrated circuits]]' |
Unified diff of changes made by edit (edit_diff) | '@@ -1,17 +1,17 @@
{{Short description|Integrated circuit that incorporates the components of a computer}}
{{Use American English|date=October 2018}}
-[[File:Raspberry Pi 4 Model B - Top.jpg|thumb|The [[Raspberry Pi]] uses a system on a chip as an almost fully contained [[microcomputer]]. This SoC does not contain any kind of data storage, which is common for a microprocessor SoC.]]
+[[File:Raspberry Pi 4 Model B - Top.jpg|thumb|The Raspberry Pi uses a system on a chip as an almost fully contained microcomputer. This SoC does not contain any kind of data storage, which is common for a microprocessor SoC.]]
-A '''system on a chip''' ('''SoC'''; {{IPAc-en|ˌ|ɛ|s|ˌ|oʊ|ˈ|s|iː|}} {{respell|es|oh|SEE}} or {{IPAc-en|s|ɒ|k}} {{respell|sock}}<ref group="nb">This article uses the convention that SoC is pronounced {{IPAc-en|ˌ|ɛ|s|ˌ|oʊ|ˈ|s|iː}} {{respell|es|oh|SEE}}. Therefore, it uses the convention "an" for the [[indefinite article]] corresponding to SoC ("'''an''' SoC"). Other sources may pronounce it as {{IPAc-en|s|ɒ|k}} {{respell|sock}} and therefore use "'''a''' SoC".</ref>) is an [[integrated circuit]] (also known as a "chip") that integrates all or most components of a [[computer]] or other [[Electronics|electronic system]]. These components almost always include a [[central processing unit]] (CPU), [[Computer memory|memory]], [[input/output]] ports and [[Computer data storage#Secondary storage|secondary storage]], often alongside other components such as [[radio modem]]s and a [[graphics processing unit]] (GPU) – all on a single [[Wafer (electronics)|substrate]] or microchip.<ref>{{Cite web|url=https://www.networkworld.com/article/3154386/7-dazzling-smartphone-improvements-with-qualcomms-snapdragon-835-chip.html|title=7 dazzling smartphone improvements with Qualcomm's Snapdragon 835 chip|first=Agam|last=Shah|date=January 3, 2017|website=Network World}}</ref> It may contain [[Digital signal (electronics)|digital]], [[Analog signal|analog]], [[Mixed-signal integrated circuit|mixed-signal]], and often [[radio frequency]] [[signal processing]] functions (otherwise it is considered only an application processor).
+A '''system on a chip''' ('''SoC'''; {{IPAc-en|ˌ|ɛ|s|ˌ|oʊ|ˈ|s|iː|}} {{respell|es|oh|SEE}} or {{IPAc-en|s|ɒ|k}} {{respell|sock}}) is an integrated circuit (also known as a "chip") that integrates all or most components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory, input/output ports and secondary storage, often alongside other components such as radio modems and a graphics processing unit (GPU) – all on a single substrate or microchip. It may contain digital, analog, mixed-signal, and often radio frequency signal processing functions (otherwise it is considered only an application processor).
-Higher-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (almost always [[LPDDR]] and [[Universal Flash Storage|eUFS]] or [[eMMC]], respectively) chips, that may be layered on top of the SoC in what's known as a [[package on package]] (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may use separate wireless modems.<ref>https://arstechnica.com/gadgets/2020/02/qualcomms-snapdragon-x60-promises-smaller-5g-modems-in-2021/?amp=1</ref>
+Higher-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (almost always LPDDR and eUFS or eMMC, respectively) chips, that may be layered on top of the SoC in what's known as a package on package (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may use separate wireless modems.
-SoCs are in contrast to the common traditional [[motherboard]]-based [[Personal computer|PC]] [[Computer architecture|architecture]], which separates components based on function and connects them through a central interfacing circuit board.<ref group="nb">This central board is called the "mother board" for hosting the "child" component cards.</ref> Whereas a motherboard houses and connects detachable or replaceable components, SoCs integrate all of these components into a single integrated circuit. An SoC will typically integrate a CPU, graphics and memory interfaces,<ref group="nb">The graphics connections ([[PCI Express]]) and RAM historically constituted the [[northbridge (computing)|northbridge]] of motherboard-backed discrete architectures.</ref> hard-disk and USB connectivity,<ref group="nb">The hard disk and USB connectivity historically comprised part of the [[southbridge (computing)|southbridge]] of motherboard-backed discrete modular architectures.</ref> [[random-access memory|random-access]] and [[read-only memory|read-only]] [[computer memory|memories]] and secondary storage and/or their controllers on a single circuit die, whereas a motherboard would connect these modules as [[discrete components]] or [[expansion card]]s.
+SoCs are in contrast to the common traditional motherboard-based PC architecture, which separates components based on function and connects them through a central interfacing circuit board. Whereas a motherboard houses and connects detachable or replaceable components, SoCs integrate all of these components into a single integrated circuit. An SoC will typically integrate a CPU, graphics and memory interfaces, hard-disk and USB connectivity, random-access and read-only memories and secondary storage and/or their controllers on a single circuit die, whereas a motherboard would connect these modules as discrete components or expansion cards.
-An SoC integrates a [[microcontroller]], [[microprocessor]] or perhaps several processor cores with peripherals like a [[GPU]], [[Wi-Fi]] and [[cellular network]] radio modems, and/or one or more [[coprocessor]]s. Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with even more advanced [[peripheral]]s. {{Selfref inline|For an overview of integrating system components, see [[system integration]].}}
+An SoC integrates a microcontroller, microprocessor or perhaps several processor cores with peripherals like a GPU, Wi-Fi and cellular network radio modems, and/or one or more coprocessors. Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with even more advanced peripherals. {{Selfref inline|For an overview of integrating system components, see [[system integration]].}}
-More tightly integrated computer system designs improve [[computer performance|performance]] and reduce [[power consumption]] as well as [[Die (integrated circuit)|semiconductor die]] area than multi-chip designs with equivalent functionality. This comes at the cost of reduced [[Interchangeable parts|replaceability]] of components. By definition, SoC designs are fully or nearly fully integrated across different component [[Modularity|modules]]. For these reasons, there has been a general trend towards tighter integration of components in the [[Semiconductor industry|computer hardware industry]], in part due to the influence of SoCs and lessons learned from the mobile and embedded computing markets. SoCs can be viewed as part of a larger trend towards [[embedded system|embedded computing]] and [[hardware acceleration]].
+More tightly integrated computer system designs improve performance and reduce power consumption as well as semiconductor die area than multi-chip designs with equivalent functionality. This comes at the cost of reduced replaceability of components. By definition, SoC designs are fully or nearly fully integrated across different component modules. For these reasons, there has been a general trend towards tighter integration of components in the computer hardware industry, in part due to the influence of SoCs and lessons learned from the mobile and embedded computing markets. SoCs can be viewed as part of a larger trend towards embedded computing and hardware acceleration.
-SoCs are very common in the [[mobile computing]] (such as in [[smartphones]] and [[tablet computer]]s) and [[edge computing]] markets.<ref>Pete Bennett, [[EE Times]]. "[http://www.eetimes.com/document.asp?doc_id=1276973 The why, where and what of low-power SoC design]." December 2, 2004. Retrieved July 28, 2015.</ref><ref>{{Cite web|url=https://www.design-reuse.com/articles/42705/power-management-for-iot-soc-development.html|title=Power Management for Internet of Things (IoT) System on a Chip (SoC) Development|last=Nolan|first=Stephen M.|website=Design And Reuse|access-date=2018-09-25}}</ref> They are also commonly used in [[embedded system]]s such as WiFi routers and the [[Internet of things|Internet of Things]].
+SoCs are very common in the mobile computing (such as in smartphones and tablet computers) and edge computing markets. They are also commonly used in embedded systems such as WiFi routers and the Internet of Things.
== Types ==
' |
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0 => '[[File:Raspberry Pi 4 Model B - Top.jpg|thumb|The Raspberry Pi uses a system on a chip as an almost fully contained microcomputer. This SoC does not contain any kind of data storage, which is common for a microprocessor SoC.]]',
1 => 'A '''system on a chip''' ('''SoC'''; {{IPAc-en|ˌ|ɛ|s|ˌ|oʊ|ˈ|s|iː|}} {{respell|es|oh|SEE}} or {{IPAc-en|s|ɒ|k}} {{respell|sock}}) is an integrated circuit (also known as a "chip") that integrates all or most components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory, input/output ports and secondary storage, often alongside other components such as radio modems and a graphics processing unit (GPU) – all on a single substrate or microchip. It may contain digital, analog, mixed-signal, and often radio frequency signal processing functions (otherwise it is considered only an application processor).',
2 => 'Higher-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (almost always LPDDR and eUFS or eMMC, respectively) chips, that may be layered on top of the SoC in what's known as a package on package (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may use separate wireless modems.',
3 => 'SoCs are in contrast to the common traditional motherboard-based PC architecture, which separates components based on function and connects them through a central interfacing circuit board. Whereas a motherboard houses and connects detachable or replaceable components, SoCs integrate all of these components into a single integrated circuit. An SoC will typically integrate a CPU, graphics and memory interfaces, hard-disk and USB connectivity, random-access and read-only memories and secondary storage and/or their controllers on a single circuit die, whereas a motherboard would connect these modules as discrete components or expansion cards.',
4 => 'An SoC integrates a microcontroller, microprocessor or perhaps several processor cores with peripherals like a GPU, Wi-Fi and cellular network radio modems, and/or one or more coprocessors. Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with even more advanced peripherals. {{Selfref inline|For an overview of integrating system components, see [[system integration]].}}',
5 => 'More tightly integrated computer system designs improve performance and reduce power consumption as well as semiconductor die area than multi-chip designs with equivalent functionality. This comes at the cost of reduced replaceability of components. By definition, SoC designs are fully or nearly fully integrated across different component modules. For these reasons, there has been a general trend towards tighter integration of components in the computer hardware industry, in part due to the influence of SoCs and lessons learned from the mobile and embedded computing markets. SoCs can be viewed as part of a larger trend towards embedded computing and hardware acceleration. ',
6 => 'SoCs are very common in the mobile computing (such as in smartphones and tablet computers) and edge computing markets. They are also commonly used in embedded systems such as WiFi routers and the Internet of Things.'
] |
Lines removed in edit (removed_lines) | [
0 => '[[File:Raspberry Pi 4 Model B - Top.jpg|thumb|The [[Raspberry Pi]] uses a system on a chip as an almost fully contained [[microcomputer]]. This SoC does not contain any kind of data storage, which is common for a microprocessor SoC.]]',
1 => 'A '''system on a chip''' ('''SoC'''; {{IPAc-en|ˌ|ɛ|s|ˌ|oʊ|ˈ|s|iː|}} {{respell|es|oh|SEE}} or {{IPAc-en|s|ɒ|k}} {{respell|sock}}<ref group="nb">This article uses the convention that SoC is pronounced {{IPAc-en|ˌ|ɛ|s|ˌ|oʊ|ˈ|s|iː}} {{respell|es|oh|SEE}}. Therefore, it uses the convention "an" for the [[indefinite article]] corresponding to SoC ("'''an''' SoC"). Other sources may pronounce it as {{IPAc-en|s|ɒ|k}} {{respell|sock}} and therefore use "'''a''' SoC".</ref>) is an [[integrated circuit]] (also known as a "chip") that integrates all or most components of a [[computer]] or other [[Electronics|electronic system]]. These components almost always include a [[central processing unit]] (CPU), [[Computer memory|memory]], [[input/output]] ports and [[Computer data storage#Secondary storage|secondary storage]], often alongside other components such as [[radio modem]]s and a [[graphics processing unit]] (GPU) – all on a single [[Wafer (electronics)|substrate]] or microchip.<ref>{{Cite web|url=https://www.networkworld.com/article/3154386/7-dazzling-smartphone-improvements-with-qualcomms-snapdragon-835-chip.html|title=7 dazzling smartphone improvements with Qualcomm's Snapdragon 835 chip|first=Agam|last=Shah|date=January 3, 2017|website=Network World}}</ref> It may contain [[Digital signal (electronics)|digital]], [[Analog signal|analog]], [[Mixed-signal integrated circuit|mixed-signal]], and often [[radio frequency]] [[signal processing]] functions (otherwise it is considered only an application processor).',
2 => 'Higher-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (almost always [[LPDDR]] and [[Universal Flash Storage|eUFS]] or [[eMMC]], respectively) chips, that may be layered on top of the SoC in what's known as a [[package on package]] (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may use separate wireless modems.<ref>https://arstechnica.com/gadgets/2020/02/qualcomms-snapdragon-x60-promises-smaller-5g-modems-in-2021/?amp=1</ref>',
3 => 'SoCs are in contrast to the common traditional [[motherboard]]-based [[Personal computer|PC]] [[Computer architecture|architecture]], which separates components based on function and connects them through a central interfacing circuit board.<ref group="nb">This central board is called the "mother board" for hosting the "child" component cards.</ref> Whereas a motherboard houses and connects detachable or replaceable components, SoCs integrate all of these components into a single integrated circuit. An SoC will typically integrate a CPU, graphics and memory interfaces,<ref group="nb">The graphics connections ([[PCI Express]]) and RAM historically constituted the [[northbridge (computing)|northbridge]] of motherboard-backed discrete architectures.</ref> hard-disk and USB connectivity,<ref group="nb">The hard disk and USB connectivity historically comprised part of the [[southbridge (computing)|southbridge]] of motherboard-backed discrete modular architectures.</ref> [[random-access memory|random-access]] and [[read-only memory|read-only]] [[computer memory|memories]] and secondary storage and/or their controllers on a single circuit die, whereas a motherboard would connect these modules as [[discrete components]] or [[expansion card]]s.',
4 => 'An SoC integrates a [[microcontroller]], [[microprocessor]] or perhaps several processor cores with peripherals like a [[GPU]], [[Wi-Fi]] and [[cellular network]] radio modems, and/or one or more [[coprocessor]]s. Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with even more advanced [[peripheral]]s. {{Selfref inline|For an overview of integrating system components, see [[system integration]].}}',
5 => 'More tightly integrated computer system designs improve [[computer performance|performance]] and reduce [[power consumption]] as well as [[Die (integrated circuit)|semiconductor die]] area than multi-chip designs with equivalent functionality. This comes at the cost of reduced [[Interchangeable parts|replaceability]] of components. By definition, SoC designs are fully or nearly fully integrated across different component [[Modularity|modules]]. For these reasons, there has been a general trend towards tighter integration of components in the [[Semiconductor industry|computer hardware industry]], in part due to the influence of SoCs and lessons learned from the mobile and embedded computing markets. SoCs can be viewed as part of a larger trend towards [[embedded system|embedded computing]] and [[hardware acceleration]]. ',
6 => 'SoCs are very common in the [[mobile computing]] (such as in [[smartphones]] and [[tablet computer]]s) and [[edge computing]] markets.<ref>Pete Bennett, [[EE Times]]. "[http://www.eetimes.com/document.asp?doc_id=1276973 The why, where and what of low-power SoC design]." December 2, 2004. Retrieved July 28, 2015.</ref><ref>{{Cite web|url=https://www.design-reuse.com/articles/42705/power-management-for-iot-soc-development.html|title=Power Management for Internet of Things (IoT) System on a Chip (SoC) Development|last=Nolan|first=Stephen M.|website=Design And Reuse|access-date=2018-09-25}}</ref> They are also commonly used in [[embedded system]]s such as WiFi routers and the [[Internet of things|Internet of Things]].'
] |
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Parsed HTML source of the new revision (new_html) | '<div class="mw-parser-output"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Integrated circuit that incorporates the components of a computer</div>
<p class="mw-empty-elt">
</p>
<div class="thumb tright"><div class="thumbinner" style="width:222px;"><a href="/enwiki/wiki/File:Raspberry_Pi_4_Model_B_-_Top.jpg" class="image"><img alt="" src="/upwiki/wikipedia/commons/thumb/1/10/Raspberry_Pi_4_Model_B_-_Top.jpg/220px-Raspberry_Pi_4_Model_B_-_Top.jpg" decoding="async" width="220" height="149" class="thumbimage" data-file-width="4365" data-file-height="2966" /></a> <div class="thumbcaption"><div class="magnify"><a href="/enwiki/wiki/File:Raspberry_Pi_4_Model_B_-_Top.jpg" class="internal" title="Enlarge"></a></div>The Raspberry Pi uses a system on a chip as an almost fully contained microcomputer. This SoC does not contain any kind of data storage, which is common for a microprocessor SoC.</div></div></div>
<p>A <b>system on a chip</b> (<b>SoC</b>; <span class="rt-commentedText nowrap"><span class="IPA nopopups noexcerpt"><a href="/enwiki/wiki/Help:IPA/English" title="Help:IPA/English">/<span style="border-bottom:1px dotted"><span title="/ˌ/: secondary stress follows">ˌ</span><span title="/ɛ/: 'e' in 'dress'">ɛ</span><span title="'s' in 'sigh'">s</span><span title="/ˌ/: secondary stress follows">ˌ</span><span title="/oʊ/: 'o' in 'code'">oʊ</span><span title="/ˈ/: primary stress follows">ˈ</span><span title="'s' in 'sigh'">s</span><span title="/iː/: 'ee' in 'fleece'">iː</span></span>/</a></span></span> <a href="/enwiki/wiki/Help:Pronunciation_respelling_key" title="Help:Pronunciation respelling key"><i title="English pronunciation respelling">es-oh-<span style="font-size:90%">SEE</span></i></a> or <span class="rt-commentedText nowrap"><span class="IPA nopopups noexcerpt"><a href="/enwiki/wiki/Help:IPA/English" title="Help:IPA/English">/<span style="border-bottom:1px dotted"><span title="'s' in 'sigh'">s</span><span title="/ɒ/: 'o' in 'body'">ɒ</span><span title="'k' in 'kind'">k</span></span>/</a></span></span> <a href="/enwiki/wiki/Help:Pronunciation_respelling_key" title="Help:Pronunciation respelling key"><i title="English pronunciation respelling">sock</i></a>) is an integrated circuit (also known as a "chip") that integrates all or most components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory, input/output ports and secondary storage, often alongside other components such as radio modems and a graphics processing unit (GPU) – all on a single substrate or microchip. It may contain digital, analog, mixed-signal, and often radio frequency signal processing functions (otherwise it is considered only an application processor).
</p><p>Higher-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (almost always LPDDR and eUFS or eMMC, respectively) chips, that may be layered on top of the SoC in what's known as a package on package (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may use separate wireless modems.
</p><p>SoCs are in contrast to the common traditional motherboard-based PC architecture, which separates components based on function and connects them through a central interfacing circuit board. Whereas a motherboard houses and connects detachable or replaceable components, SoCs integrate all of these components into a single integrated circuit. An SoC will typically integrate a CPU, graphics and memory interfaces, hard-disk and USB connectivity, random-access and read-only memories and secondary storage and/or their controllers on a single circuit die, whereas a motherboard would connect these modules as discrete components or expansion cards.
</p><p>An SoC integrates a microcontroller, microprocessor or perhaps several processor cores with peripherals like a GPU, Wi-Fi and cellular network radio modems, and/or one or more coprocessors. Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with even more advanced peripherals. <style data-mw-deduplicate="TemplateStyles:r1033289096">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}</style><span role="note" class="hatnote navigation-not-searchable">For an overview of integrating system components, see <a href="/enwiki/wiki/System_integration" title="System integration">system integration</a>.</span>
</p><p>More tightly integrated computer system designs improve performance and reduce power consumption as well as semiconductor die area than multi-chip designs with equivalent functionality. This comes at the cost of reduced replaceability of components. By definition, SoC designs are fully or nearly fully integrated across different component modules. For these reasons, there has been a general trend towards tighter integration of components in the computer hardware industry, in part due to the influence of SoCs and lessons learned from the mobile and embedded computing markets. SoCs can be viewed as part of a larger trend towards embedded computing and hardware acceleration.
</p><p>SoCs are very common in the mobile computing (such as in smartphones and tablet computers) and edge computing markets. They are also commonly used in embedded systems such as WiFi routers and the Internet of Things.
</p>
<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div>
<ul>
<li class="toclevel-1 tocsection-1"><a href="#Types"><span class="tocnumber">1</span> <span class="toctext">Types</span></a></li>
<li class="toclevel-1 tocsection-2"><a href="#Applications"><span class="tocnumber">2</span> <span class="toctext">Applications</span></a>
<ul>
<li class="toclevel-2 tocsection-3"><a href="#Embedded_systems"><span class="tocnumber">2.1</span> <span class="toctext">Embedded systems</span></a></li>
<li class="toclevel-2 tocsection-4"><a href="#Mobile_computing"><span class="tocnumber">2.2</span> <span class="toctext">Mobile computing</span></a></li>
<li class="toclevel-2 tocsection-5"><a href="#Personal_computers"><span class="tocnumber">2.3</span> <span class="toctext">Personal computers</span></a></li>
</ul>
</li>
<li class="toclevel-1 tocsection-6"><a href="#Structure"><span class="tocnumber">3</span> <span class="toctext">Structure</span></a>
<ul>
<li class="toclevel-2 tocsection-7"><a href="#Functional_components"><span class="tocnumber">3.1</span> <span class="toctext">Functional components</span></a>
<ul>
<li class="toclevel-3 tocsection-8"><a href="#Processor_cores"><span class="tocnumber">3.1.1</span> <span class="toctext">Processor cores</span></a></li>
<li class="toclevel-3 tocsection-9"><a href="#Memory"><span class="tocnumber">3.1.2</span> <span class="toctext">Memory</span></a></li>
<li class="toclevel-3 tocsection-10"><a href="#Interfaces"><span class="tocnumber">3.1.3</span> <span class="toctext">Interfaces</span></a></li>
<li class="toclevel-3 tocsection-11"><a href="#Digital_signal_processors"><span class="tocnumber">3.1.4</span> <span class="toctext">Digital signal processors</span></a></li>
<li class="toclevel-3 tocsection-12"><a href="#Other"><span class="tocnumber">3.1.5</span> <span class="toctext">Other</span></a></li>
</ul>
</li>
<li class="toclevel-2 tocsection-13"><a href="#Intermodule_communication"><span class="tocnumber">3.2</span> <span class="toctext">Intermodule communication</span></a>
<ul>
<li class="toclevel-3 tocsection-14"><a href="#Bus-based_communication"><span class="tocnumber">3.2.1</span> <span class="toctext">Bus-based communication</span></a></li>
<li class="toclevel-3 tocsection-15"><a href="#Network_on_a_chip"><span class="tocnumber">3.2.2</span> <span class="toctext">Network on a chip</span></a></li>
</ul>
</li>
</ul>
</li>
<li class="toclevel-1 tocsection-16"><a href="#Design_flow"><span class="tocnumber">4</span> <span class="toctext">Design flow</span></a>
<ul>
<li class="toclevel-2 tocsection-17"><a href="#Design_verification"><span class="tocnumber">4.1</span> <span class="toctext">Design verification</span></a></li>
</ul>
</li>
<li class="toclevel-1 tocsection-18"><a href="#Optimization_goals"><span class="tocnumber">5</span> <span class="toctext">Optimization goals</span></a>
<ul>
<li class="toclevel-2 tocsection-19"><a href="#Targets"><span class="tocnumber">5.1</span> <span class="toctext">Targets</span></a>
<ul>
<li class="toclevel-3 tocsection-20"><a href="#Power_consumption"><span class="tocnumber">5.1.1</span> <span class="toctext">Power consumption</span></a></li>
<li class="toclevel-3 tocsection-21"><a href="#Performance_per_watt"><span class="tocnumber">5.1.2</span> <span class="toctext">Performance per watt</span></a></li>
<li class="toclevel-3 tocsection-22"><a href="#Waste_heat"><span class="tocnumber">5.1.3</span> <span class="toctext">Waste heat</span></a></li>
<li class="toclevel-3 tocsection-23"><a href="#Throughput"><span class="tocnumber">5.1.4</span> <span class="toctext">Throughput</span></a></li>
<li class="toclevel-3 tocsection-24"><a href="#Latency"><span class="tocnumber">5.1.5</span> <span class="toctext">Latency</span></a></li>
</ul>
</li>
<li class="toclevel-2 tocsection-25"><a href="#Methodologies"><span class="tocnumber">5.2</span> <span class="toctext">Methodologies</span></a>
<ul>
<li class="toclevel-3 tocsection-26"><a href="#Task_scheduling"><span class="tocnumber">5.2.1</span> <span class="toctext">Task scheduling</span></a></li>
<li class="toclevel-3 tocsection-27"><a href="#Pipelining"><span class="tocnumber">5.2.2</span> <span class="toctext">Pipelining</span></a></li>
<li class="toclevel-3 tocsection-28"><a href="#Probabilistic_modeling"><span class="tocnumber">5.2.3</span> <span class="toctext">Probabilistic modeling</span></a></li>
<li class="toclevel-3 tocsection-29"><a href="#Markov_chains"><span class="tocnumber">5.2.4</span> <span class="toctext">Markov chains</span></a></li>
</ul>
</li>
</ul>
</li>
<li class="toclevel-1 tocsection-30"><a href="#Fabrication"><span class="tocnumber">6</span> <span class="toctext">Fabrication</span></a></li>
<li class="toclevel-1 tocsection-31"><a href="#Benchmarks"><span class="tocnumber">7</span> <span class="toctext">Benchmarks</span></a></li>
<li class="toclevel-1 tocsection-32"><a href="#See_also"><span class="tocnumber">8</span> <span class="toctext">See also</span></a></li>
<li class="toclevel-1 tocsection-33"><a href="#Notes"><span class="tocnumber">9</span> <span class="toctext">Notes</span></a></li>
<li class="toclevel-1 tocsection-34"><a href="#References"><span class="tocnumber">10</span> <span class="toctext">References</span></a></li>
<li class="toclevel-1 tocsection-35"><a href="#Further_reading"><span class="tocnumber">11</span> <span class="toctext">Further reading</span></a></li>
<li class="toclevel-1 tocsection-36"><a href="#External_links"><span class="tocnumber">12</span> <span class="toctext">External links</span></a></li>
</ul>
</div>
<h2><span class="mw-headline" id="Types">Types</span></h2>
<div class="thumb tright"><div class="thumbinner" style="width:277px;"><a href="/enwiki/wiki/File:ARMSoCBlockDiagram.svg" class="image"><img alt="" src="/upwiki/wikipedia/commons/thumb/8/85/ARMSoCBlockDiagram.svg/275px-ARMSoCBlockDiagram.svg.png" decoding="async" width="275" height="330" class="thumbimage" srcset="/upwiki/wikipedia/commons/thumb/8/85/ARMSoCBlockDiagram.svg/413px-ARMSoCBlockDiagram.svg.png 1.5x, /upwiki/wikipedia/commons/thumb/8/85/ARMSoCBlockDiagram.svg/550px-ARMSoCBlockDiagram.svg.png 2x" data-file-width="500" data-file-height="600" /></a> <div class="thumbcaption"><div class="magnify"><a href="/enwiki/wiki/File:ARMSoCBlockDiagram.svg" class="internal" title="Enlarge"></a></div><a href="/enwiki/wiki/Microcontroller" title="Microcontroller">Microcontroller</a>-based system on a chip</div></div></div><p>In general, there are four distinguishable types of SoCs:
</p><ul><li>SoCs built around a <a href="/enwiki/wiki/Microcontroller" title="Microcontroller">microcontroller</a>,</li>
<li>SoCs built around a <a href="/enwiki/wiki/Microprocessor" title="Microprocessor">microprocessor</a>, often found in mobile phones;</li>
<li>Specialized <a href="/enwiki/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">application-specific integrated circuit</a> SoCs designed for specific applications that do not fit into the above two categories, and</li>
<li><a href="/enwiki/wiki/Programmable_system-on-chip" class="mw-redirect" title="Programmable system-on-chip">Programmable SoCs</a> (PSoC), where most functionality is fixed but some functionality is <a href="/enwiki/wiki/Reconfigurable_computing" title="Reconfigurable computing">reprogrammable</a> in a manner analogous to a <a href="/enwiki/wiki/Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate array</a>.</li></ul>
<div class="thumb tright"><div class="thumbinner" style="width:222px;"><a href="/enwiki/wiki/File:KL_AMD_Am286LX_ZX.jpg" class="image"><img alt="" src="/upwiki/wikipedia/commons/thumb/f/fb/KL_AMD_Am286LX_ZX.jpg/220px-KL_AMD_Am286LX_ZX.jpg" decoding="async" width="220" height="225" class="thumbimage" data-file-width="1032" data-file-height="1056" /></a> <div class="thumbcaption"><div class="magnify"><a href="/enwiki/wiki/File:KL_AMD_Am286LX_ZX.jpg" class="internal" title="Enlarge"></a></div><a href="/enwiki/wiki/AMD" class="mw-redirect" title="AMD">AMD</a> Am286ZX/LX, SoC based on <a href="/enwiki/wiki/Intel_80286" title="Intel 80286">Intel 80286</a></div></div></div>
<h2><span class="mw-headline" id="Applications">Applications</span></h2>
<p>SoCs can be applied to any computing task. However, they are typically used in mobile computing such as tablets, smartphones, smartwatches and netbooks as well as <a href="/enwiki/wiki/Embedded_system" title="Embedded system">embedded systems</a> and in applications where previously <a href="/enwiki/wiki/Microcontroller" title="Microcontroller">microcontrollers</a> would be used.
</p>
<h3><span class="mw-headline" id="Embedded_systems">Embedded systems</span></h3>
<p>Where previously only microcontrollers could be used, SoCs are rising to prominence in the embedded systems market. Tighter system integration offers better reliability and <a href="/enwiki/wiki/Mean_time_between_failures" title="Mean time between failures">mean time between failure</a>, and SoCs offer more advanced functionality and computing power than microcontrollers.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1">[1]</a></sup> Applications include <a href="/enwiki/wiki/AI_accelerator" title="AI accelerator">AI acceleration</a>, embedded <a href="/enwiki/wiki/Machine_vision" title="Machine vision">machine vision</a>,<sup id="cite_ref-2" class="reference"><a href="#cite_note-2">[2]</a></sup> data collection, <a href="/enwiki/wiki/Telemetry" title="Telemetry">telemetry</a>, vector processing and <a href="/enwiki/wiki/Ambient_intelligence" title="Ambient intelligence">ambient intelligence</a>. Often embedded SoCs target the <a href="/enwiki/wiki/Internet_of_things" title="Internet of things">internet of things</a>, <a href="/enwiki/wiki/Internet_of_things" title="Internet of things">industrial internet of things</a> and <a href="/enwiki/wiki/Edge_computing" title="Edge computing">edge computing</a> markets.
</p>
<h3><span class="mw-headline" id="Mobile_computing">Mobile computing</span></h3>
<p><a href="/enwiki/wiki/Mobile_computing" title="Mobile computing">Mobile computing</a> based SoCs always bundle processors, memories, on-chip <a href="/enwiki/wiki/Cache_(computing)" title="Cache (computing)">caches</a>, <a href="/enwiki/wiki/Wireless_networking" class="mw-redirect" title="Wireless networking">wireless networking</a> capabilities and often <a href="/enwiki/wiki/Digital_camera" title="Digital camera">digital camera</a> hardware and firmware. With increasing memory sizes, high end SoCs will often have no memory and flash storage and instead, the memory and <a href="/enwiki/wiki/Flash_memory" title="Flash memory">flash memory</a> will be placed right next to, or above (<a href="/enwiki/wiki/Package_on_package" class="mw-redirect" title="Package on package">package on package</a>), the SoC.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3">[3]</a></sup> Some examples of mobile computing SoCs include:
</p>
<ul><li><a href="/enwiki/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung Electronics</a>: <a href="/enwiki/wiki/List_of_Samsung_System_on_Chips" class="mw-redirect" title="List of Samsung System on Chips">list</a>, typically based on <a href="/enwiki/wiki/ARM_architecture" title="ARM architecture">ARM</a>
<ul><li><a href="/enwiki/wiki/Exynos" title="Exynos">Exynos</a>, used mainly by Samsung's <a href="/enwiki/wiki/Samsung_Galaxy" title="Samsung Galaxy">Galaxy</a> series of smartphones</li></ul></li>
<li><a href="/enwiki/wiki/Qualcomm" title="Qualcomm">Qualcomm</a>:
<ul><li><a href="/enwiki/wiki/Qualcomm_Snapdragon" title="Qualcomm Snapdragon">Snapdragon</a> (<a href="/enwiki/wiki/List_of_Qualcomm_Snapdragon_systems-on-chip" class="mw-redirect" title="List of Qualcomm Snapdragon systems-on-chip">list</a>), used in many <a href="/enwiki/wiki/LG_Corporation" title="LG Corporation">LG</a>, <a href="/enwiki/wiki/Xiaomi" title="Xiaomi">Xiaomi</a>, <a href="/enwiki/wiki/Google_Pixel" title="Google Pixel">Google Pixel</a>, <a href="/enwiki/wiki/HTC" title="HTC">HTC</a> and Samsung Galaxy smartphones. In 2018, Snapdragon SoCs are being used as the backbone of <a href="/enwiki/wiki/Laptop" title="Laptop">laptop computers</a> running <a href="/enwiki/wiki/Windows_10" title="Windows 10">Windows 10</a>, marketed as "Always Connected PCs".<sup id="cite_ref-:3_4-0" class="reference"><a href="#cite_note-:3-4">[4]</a></sup><sup id="cite_ref-:4_5-0" class="reference"><a href="#cite_note-:4-5">[5]</a></sup></li></ul></li></ul>
<h3><span class="mw-headline" id="Personal_computers">Personal computers</span></h3>
<p>In 1992, <a href="/enwiki/wiki/Acorn_Computers" title="Acorn Computers">Acorn Computers</a> produced the <a href="/enwiki/wiki/Acorn_Archimedes#New_range_and_a_laptop" title="Acorn Archimedes">A3010, A3020 and A4000 range of personal computers</a> with the ARM250 SoC. It combined the original Acorn ARM2 processor with a memory controller (MEMC), video controller (VIDC), and I/O controller (IOC). In previous Acorn <a href="/enwiki/wiki/ARM_architecture" title="ARM architecture">ARM</a>-powered computers, these were four discrete chips. The ARM7500 chip was their second-generation SoC, based on the ARM700, VIDC20 and IOMD controllers, and was widely licensed in embedded devices such as set-top-boxes, as well as later Acorn personal computers.
</p><p>SoCs are being applied to mainstream <a href="/enwiki/wiki/Personal_computer" title="Personal computer">personal computers</a> as of 2018.<sup id="cite_ref-:3_4-1" class="reference"><a href="#cite_note-:3-4">[4]</a></sup> They are particularly applied to <a href="/enwiki/wiki/Laptop" title="Laptop">laptops</a> and <a href="/enwiki/wiki/Tablet_computer" title="Tablet computer">tablet PCs</a>. Tablet and laptop manufacturers have learned lessons from embedded systems and smartphone markets about reduced power consumption, better performance and reliability from tighter <a href="/enwiki/wiki/System_integration" title="System integration">integration</a> of hardware and <a href="/enwiki/wiki/Firmware" title="Firmware">firmware</a> <a href="/enwiki/wiki/Module_system" class="mw-redirect" title="Module system">modules</a>, and <a href="/enwiki/wiki/LTE_(telecommunication)" title="LTE (telecommunication)">LTE</a> and other <a href="/enwiki/wiki/Wireless_network" title="Wireless network">wireless network</a> communications integrated on chip (integrated <a href="/enwiki/wiki/Network_interface_controller" title="Network interface controller">network interface controllers</a>).<sup id="cite_ref-6" class="reference"><a href="#cite_note-6">[6]</a></sup>
</p><p><a href="/enwiki/wiki/ARM_architecture" title="ARM architecture">ARM</a>-based:
</p>
<ul><li><a href="/enwiki/wiki/Qualcomm_Snapdragon" title="Qualcomm Snapdragon">Qualcomm Snapdragon</a><sup id="cite_ref-:4_5-1" class="reference"><a href="#cite_note-:4-5">[5]</a></sup></li>
<li>ARM250</li>
<li>ARM7500(FE)</li>
<li><a href="/enwiki/wiki/Apple_M1" title="Apple M1">Apple M1</a></li></ul>
<p><a href="/enwiki/wiki/X86" title="X86">x86</a>-based:
</p>
<ul><li><a href="/enwiki/wiki/Intel_Core" title="Intel Core">Intel Core</a> <a href="/enwiki/wiki/CULV" class="mw-redirect" title="CULV">CULV</a></li></ul>
<h2><span class="mw-headline" id="Structure">Structure</span></h2>
<p>An SoC consists of hardware <a href="/enwiki/wiki/Functional_unit" class="mw-redirect" title="Functional unit">functional units</a>, including <a href="/enwiki/wiki/Microprocessor" title="Microprocessor">microprocessors</a> that run <a href="/enwiki/wiki/Computer_program" title="Computer program">software code</a>, as well as a <a href="/enwiki/wiki/Communications_subsystem" class="mw-redirect" title="Communications subsystem">communications subsystem</a> to connect, control, direct and interface between these functional modules.
</p>
<h3><span class="mw-headline" id="Functional_components">Functional components</span></h3>
<h4><span class="mw-headline" id="Processor_cores">Processor cores</span></h4>
<p>An SoC must have at least one <a href="/enwiki/wiki/Processor_core" class="mw-redirect" title="Processor core">processor core</a>, but typically an SoC has more than one core. Processor cores can be a <a href="/enwiki/wiki/Microcontroller" title="Microcontroller">microcontroller</a>, <a href="/enwiki/wiki/Microprocessor" title="Microprocessor">microprocessor</a> (μP),<sup id="cite_ref-Furber_ARM_7-0" class="reference"><a href="#cite_note-Furber_ARM-7">[7]</a></sup> <a href="/enwiki/wiki/Digital_signal_processor" title="Digital signal processor">digital signal processor</a> (DSP) or <a href="/enwiki/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">application-specific instruction set processor</a> (ASIP) core.<sup id="cite_ref-:1_8-0" class="reference"><a href="#cite_note-:1-8">[8]</a></sup> ASIPs have <a href="/enwiki/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction sets</a> that are customized for an <a href="/enwiki/wiki/Application_domain" title="Application domain">application domain</a> and designed to be more efficient than general-purpose instructions for a specific type of workload. <a href="/enwiki/wiki/Multi-processor_system-on-chip" class="mw-redirect" title="Multi-processor system-on-chip">Multiprocessor SoCs</a> have more than one processor core by definition.
</p><p>Whether single-core, <a href="/enwiki/wiki/Multi-core_processor" title="Multi-core processor">multi-core</a> or <a href="/enwiki/wiki/Manycore" class="mw-redirect" title="Manycore">manycore</a>, SoC processor cores typically use <a href="/enwiki/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a> instruction set architectures. RISC architectures are advantageous over <a href="/enwiki/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a> processors for SoCs because they require less digital logic, and therefore less power and area on <a href="/enwiki/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">board</a>, and in the <a href="/enwiki/wiki/Embedded_system" title="Embedded system">embedded</a> and <a href="/enwiki/wiki/Mobile_computing" title="Mobile computing">mobile computing</a> markets, area and power are often highly constrained. In particular, SoC processor cores often use the <a href="/enwiki/wiki/ARM_architecture" title="ARM architecture">ARM architecture</a> because it is a <a href="/enwiki/wiki/Soft_microprocessor" title="Soft microprocessor">soft processor</a> specified as an <a href="/enwiki/wiki/IP_core" class="mw-redirect" title="IP core">IP core</a> and is more power efficient than <a href="/enwiki/wiki/X86" title="X86">x86</a>.<sup id="cite_ref-Furber_ARM_7-1" class="reference"><a href="#cite_note-Furber_ARM-7">[7]</a></sup>
</p>
<h4><span class="mw-headline" id="Memory">Memory</span></h4>
<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1033289096"/><div role="note" class="hatnote navigation-not-searchable">Further information: <a href="/enwiki/wiki/Computer_memory" title="Computer memory">Computer memory</a></div>
<p>SoCs must have <a href="/enwiki/wiki/Semiconductor_memory" title="Semiconductor memory">semiconductor memory</a> blocks to perform their computation, as do <a href="/enwiki/wiki/Microcontroller" title="Microcontroller">microcontrollers</a> and other <a href="/enwiki/wiki/Embedded_system" title="Embedded system">embedded systems</a>. Depending on the application, SoC memory may form a <a href="/enwiki/wiki/Memory_hierarchy" title="Memory hierarchy">memory hierarchy</a> and <a href="/enwiki/wiki/Cache_hierarchy" title="Cache hierarchy">cache hierarchy</a>. In the mobile computing market, this is common, but in many <a href="/enwiki/wiki/Low-power_electronics" title="Low-power electronics">low-power</a> embedded microcontrollers, this is not necessary. Memory technologies for SoCs include <a href="/enwiki/wiki/Read-only_memory" title="Read-only memory">read-only memory</a> (ROM), <a href="/enwiki/wiki/Random-access_memory" title="Random-access memory">random-access memory</a> (RAM), Electrically Erasable Programmable ROM (<a href="/enwiki/wiki/EEPROM" title="EEPROM">EEPROM</a>) and <a href="/enwiki/wiki/Flash_memory" title="Flash memory">flash memory</a>.<sup id="cite_ref-Furber_ARM_7-2" class="reference"><a href="#cite_note-Furber_ARM-7">[7]</a></sup> As in other computer systems, RAM can be subdivided into relatively faster but more expensive <a href="/enwiki/wiki/Static_random-access_memory" title="Static random-access memory">static RAM</a> (SRAM) and the slower but cheaper <a href="/enwiki/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">dynamic RAM</a> (DRAM). When an SoC has a <a href="/enwiki/wiki/Cache_(computing)" title="Cache (computing)">cache</a> hierarchy, SRAM will usually be used to implement <a href="/enwiki/wiki/Processor_register" title="Processor register">processor registers</a> and cores' <a href="/enwiki/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1 caches</a> whereas DRAM will be used for lower levels of the cache hierarchy including <a href="/enwiki/wiki/Main_memory" class="mw-redirect" title="Main memory">main memory</a>. "Main memory" may be specific to a single processor (which can be <a href="/enwiki/wiki/Multi-core_processor" title="Multi-core processor">multi-core</a>) when the SoC <a href="/enwiki/wiki/Multi-processor_system-on-chip" class="mw-redirect" title="Multi-processor system-on-chip">has multiple processors</a>, in which case it is <a href="/enwiki/wiki/Distributed_memory" title="Distributed memory">distributed memory</a> and must be sent via <a href="#Intermodule_communication">§ Intermodule communication</a> on-chip to be accessed by a different processor.<sup id="cite_ref-:1_8-1" class="reference"><a href="#cite_note-:1-8">[8]</a></sup> For further discussion of multi-processing memory issues, see <a href="/enwiki/wiki/Cache_coherence" title="Cache coherence">cache coherence</a> and <a href="/enwiki/wiki/Memory_latency" title="Memory latency">memory latency</a>.
</p>
<h4><span class="mw-headline" id="Interfaces">Interfaces</span></h4>
<p>SoCs include external <a href="/enwiki/wiki/Electrical_connector" title="Electrical connector">interfaces</a>, typically for <a href="/enwiki/wiki/Communication_protocol" title="Communication protocol">communication protocols</a>. These are often based upon industry standards such as <a href="/enwiki/wiki/USB" title="USB">USB</a>, <a href="/enwiki/wiki/FireWire" class="mw-redirect" title="FireWire">FireWire</a>, <a href="/enwiki/wiki/Ethernet" title="Ethernet">Ethernet</a>, <a href="/enwiki/wiki/Universal_synchronous_and_asynchronous_receiver-transmitter" title="Universal synchronous and asynchronous receiver-transmitter">USART</a>, <a href="/enwiki/wiki/Serial_Peripheral_Interface" title="Serial Peripheral Interface">SPI</a>, <a href="/enwiki/wiki/HDMI" title="HDMI">HDMI</a>, <a href="/enwiki/wiki/I%C2%B2C" title="I²C">I²C</a>, etc. These interfaces will differ according to the intended application. <a href="/enwiki/wiki/Wireless_network" title="Wireless network">Wireless networking</a> protocols such as <a href="/enwiki/wiki/Wi-Fi" title="Wi-Fi">Wi-Fi</a>, <a href="/enwiki/wiki/Bluetooth" title="Bluetooth">Bluetooth</a>, <a href="/enwiki/wiki/6LoWPAN" title="6LoWPAN">6LoWPAN</a> and <a href="/enwiki/wiki/Near-field_communication" title="Near-field communication">near-field communication</a> may also be supported.
</p><p>When needed, SoCs include <a href="/enwiki/wiki/Analog_signal" title="Analog signal">analog</a> interfaces including <a href="/enwiki/wiki/Analog-to-digital_converter" title="Analog-to-digital converter">analog-to-digital</a> and <a href="/enwiki/wiki/Digital-to-analog_converter" title="Digital-to-analog converter">digital-to-analog converters</a>, often for <a href="/enwiki/wiki/Signal_processing" title="Signal processing">signal processing</a>. These may be able to interface with different types of <a href="/enwiki/wiki/Sensor" title="Sensor">sensors</a> or <a href="/enwiki/wiki/Actuator" title="Actuator">actuators</a>, including <a href="/enwiki/wiki/Smart_transducer" title="Smart transducer">smart transducers</a>. They may interface with application-specific <a href="/enwiki/wiki/Modularity" title="Modularity">modules</a> or shields.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9">[nb 1]</a></sup> Or they may be internal to the SoC, such as if an analog sensor is built in to the SoC and its readings must be converted to digital signals for mathematical processing.
</p>
<h4><span class="mw-headline" id="Digital_signal_processors">Digital signal processors</span></h4>
<p><a href="/enwiki/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP) cores are often included on SoCs. They perform <a href="/enwiki/wiki/Signal_processing" title="Signal processing">signal processing</a> operations in SoCs for <a href="/enwiki/wiki/Sensor" title="Sensor">sensors</a>, <a href="/enwiki/wiki/Actuator" title="Actuator">actuators</a>, <a href="/enwiki/wiki/Data_collection" title="Data collection">data collection</a>, <a href="/enwiki/wiki/Data_analysis" title="Data analysis">data analysis</a> and multimedia processing. DSP cores typically feature <a href="/enwiki/wiki/Very_long_instruction_word" title="Very long instruction word">very long instruction word</a> (VLIW) and <a href="/enwiki/wiki/SIMD" title="SIMD">single instruction, multiple data</a> (SIMD) <a href="/enwiki/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architectures</a>, and are therefore highly amenable to exploiting <a href="/enwiki/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">instruction-level parallelism</a> through <a href="/enwiki/wiki/Parallel_processing_(DSP_implementation)" title="Parallel processing (DSP implementation)">parallel processing</a> and <a href="/enwiki/wiki/Superscalar_execution" class="mw-redirect" title="Superscalar execution">superscalar execution</a>.<sup id="cite_ref-:1_8-2" class="reference"><a href="#cite_note-:1-8">[8]</a></sup><sup class="reference" style="white-space:nowrap;">:<span>4</span></sup> DSP cores most often feature application-specific instructions, and as such are typically <a href="/enwiki/wiki/Application-specific_instruction-set_processor" class="mw-redirect" title="Application-specific instruction-set processor">application-specific instruction-set processors</a> (ASIP). Such application-specific instructions correspond to dedicated hardware <a href="/enwiki/wiki/Functional_unit" class="mw-redirect" title="Functional unit">functional units</a> that compute those instructions.
</p><p>Typical DSP instructions include <a href="/enwiki/wiki/Multiply%E2%80%93accumulate_operation" title="Multiply–accumulate operation">multiply-accumulate</a>, <a href="/enwiki/wiki/Fast_Fourier_transform" title="Fast Fourier transform">Fast Fourier transform</a>, <a href="/enwiki/wiki/Fused_multiply-accumulate" class="mw-redirect" title="Fused multiply-accumulate">fused multiply-add</a>, and <a href="/enwiki/wiki/Convolution" title="Convolution">convolutions</a>.
</p>
<h4><span class="mw-headline" id="Other">Other</span></h4>
<p>As with other computer systems, SoCs require <a href="/enwiki/wiki/Clock_generator" title="Clock generator">timing sources</a> to generate <a href="/enwiki/wiki/Clock_signal" title="Clock signal">clock signals</a>, control execution of SoC functions and provide time context to <a href="/enwiki/wiki/Signal_processing" title="Signal processing">signal processing</a> applications of the SoC, if needed. Popular time sources are <a href="/enwiki/wiki/Crystal_oscillators" class="mw-redirect" title="Crystal oscillators">crystal oscillators</a> and <a href="/enwiki/wiki/Phase-locked_loop" title="Phase-locked loop">phase-locked loops</a>.
</p><p>SoC <a href="/enwiki/wiki/Peripheral" title="Peripheral">peripherals</a> including <a href="/enwiki/wiki/Counter_(digital)" title="Counter (digital)">counter</a>-timers, real-time <a href="/enwiki/wiki/Timer" title="Timer">timers</a> and <a href="/enwiki/wiki/Power-on_reset" title="Power-on reset">power-on reset</a> generators. SoCs also include <a href="/enwiki/wiki/Voltage_regulator" title="Voltage regulator">voltage regulators</a> and <a href="/enwiki/wiki/Power_management" title="Power management">power management</a> circuits.
</p>
<h3><span class="mw-headline" id="Intermodule_communication">Intermodule communication</span></h3>
<p>SoCs comprise many <a href="/enwiki/wiki/Execution_unit" title="Execution unit">execution units</a>. These units must often send <a href="/enwiki/wiki/Data" title="Data">data</a> and <a href="/enwiki/wiki/Instruction_(computing)" class="mw-redirect" title="Instruction (computing)">instructions</a> back and forth. Because of this, all but the most trivial SoCs require <a href="/enwiki/wiki/Communications_system" title="Communications system">communications subsystems</a>. Originally, as with other <a href="/enwiki/wiki/Microcomputer" title="Microcomputer">microcomputer</a> technologies, <a href="/enwiki/wiki/Bus_(computing)" title="Bus (computing)">data bus</a> architectures were used, but recently designs based on sparse intercommunication networks known as <a href="/enwiki/wiki/Network_on_a_chip" title="Network on a chip">networks-on-chip</a> (NoC) have risen to prominence and are forecast to overtake bus architectures for SoC design in the near future.<sup id="cite_ref-:0_10-0" class="reference"><a href="#cite_note-:0-10">[9]</a></sup>
</p>
<h4><span class="mw-headline" id="Bus-based_communication">Bus-based communication</span></h4>
<p>Historically, a shared global <a href="/enwiki/wiki/Bus_(computing)" title="Bus (computing)">computer bus</a> typically connected the different components, also called "blocks" of the SoC.<sup id="cite_ref-:0_10-1" class="reference"><a href="#cite_note-:0-10">[9]</a></sup> A very common bus for SoC communications is ARM's royalty-free Advanced Microcontroller Bus Architecture (<a href="/enwiki/wiki/Advanced_Microcontroller_Bus_Architecture" title="Advanced Microcontroller Bus Architecture">AMBA</a>) standard.
</p><p><a href="/enwiki/wiki/Direct_memory_access" title="Direct memory access">Direct memory access</a> controllers route data directly between external interfaces and SoC memory, bypassing the CPU or <a href="/enwiki/wiki/Control_unit" title="Control unit">control unit</a>, thereby increasing the data <a href="/enwiki/wiki/Throughput" title="Throughput">throughput</a> of the SoC. This is similar to some <a href="/enwiki/wiki/Device_driver" title="Device driver">device drivers</a> of peripherals on component-based <a href="/enwiki/wiki/Multi-chip_module" title="Multi-chip module">multi-chip module</a> PC architectures.
</p><p>Computer buses are limited in <a href="/enwiki/wiki/Scalability" title="Scalability">scalability</a>, supporting only up to tens of cores (<a href="/enwiki/wiki/Multicore" class="mw-redirect" title="Multicore">multicore</a>) on a single chip.<sup id="cite_ref-:0_10-2" class="reference"><a href="#cite_note-:0-10">[9]</a></sup><sup class="reference" style="white-space:nowrap;">:<span>xiii</span></sup> Wire delay is not scalable due to continued <a href="/enwiki/wiki/Miniaturization" title="Miniaturization">miniaturization</a>, <a href="/enwiki/wiki/Computer_performance" title="Computer performance">system performance</a> does not scale with the number of cores attached, the SoC's <a href="/enwiki/wiki/Operating_frequency" class="mw-redirect" title="Operating frequency">operating frequency</a> must decrease with each additional core attached for power to be sustainable, and long wires consume large amounts of electrical power. These challenges are prohibitive to supporting <a href="/enwiki/wiki/Manycore" class="mw-redirect" title="Manycore">manycore</a> systems on chip.<sup id="cite_ref-:0_10-3" class="reference"><a href="#cite_note-:0-10">[9]</a></sup><sup class="reference" style="white-space:nowrap;">:<span>xiii</span></sup>
</p>
<h4><span class="mw-headline" id="Network_on_a_chip">Network on a chip</span></h4>
<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1033289096"/><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/enwiki/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a></div>
<p>In the late <a href="/enwiki/wiki/2010s" title="2010s">2010s</a>, a trend of SoCs implementing <a href="/enwiki/wiki/Communications_subsystem" class="mw-redirect" title="Communications subsystem">communications subsystems</a> in terms of a network-like topology instead of <a href="/enwiki/wiki/Bus_(computing)" title="Bus (computing)">bus-based</a> protocols has emerged. A trend towards <a href="/enwiki/wiki/Multi-processor_system-on-chip" class="mw-redirect" title="Multi-processor system-on-chip">more processor cores on SoCs</a> has caused on-chip communication efficiency to become one of the key factors in determining the overall system performance and cost.<sup id="cite_ref-:0_10-4" class="reference"><a href="#cite_note-:0-10">[9]</a></sup><sup class="reference" style="white-space:nowrap;">:<span>xiii</span></sup> This has led to the emergence of interconnection networks with <a href="/enwiki/wiki/Router_(computing)" title="Router (computing)">router</a>-based <a href="/enwiki/wiki/Packet_switching" title="Packet switching">packet switching</a> known as "<a href="/enwiki/wiki/Network_on_a_chip" title="Network on a chip">networks on chip</a>" (NoCs) to overcome the <a href="/enwiki/wiki/Bottleneck_(engineering)" title="Bottleneck (engineering)">bottlenecks</a> of bus-based networks.<sup id="cite_ref-:0_10-5" class="reference"><a href="#cite_note-:0-10">[9]</a></sup><sup class="reference" style="white-space:nowrap;">:<span>xiii</span></sup>
</p><p>Networks-on-chip have advantages including destination- and application-specific <a href="/enwiki/wiki/Routing" title="Routing">routing</a>, greater power efficiency and reduced possibility of <a href="/enwiki/wiki/Bus_contention" title="Bus contention">bus contention</a>. Network-on-chip architectures take inspiration from <a href="/enwiki/wiki/Communication_protocols" class="mw-redirect" title="Communication protocols">communication protocols</a> like <a href="/enwiki/wiki/Transmission_Control_Protocol" title="Transmission Control Protocol">TCP</a> and the <a href="/enwiki/wiki/Internet_protocol_suite" title="Internet protocol suite">Internet protocol suite</a> for on-chip communication,<sup id="cite_ref-:0_10-6" class="reference"><a href="#cite_note-:0-10">[9]</a></sup> although they typically have fewer <a href="/enwiki/wiki/Network_layer" title="Network layer">network layers</a>. Optimal network-on-chip <a href="/enwiki/wiki/Network_architecture" title="Network architecture">network architectures</a> are an ongoing area of much research interest. NoC architectures range from traditional distributed computing <a href="/enwiki/wiki/Network_topology" title="Network topology">network topologies</a> such as <a href="/enwiki/wiki/Torus_interconnect" title="Torus interconnect">torus</a>, <a href="/enwiki/wiki/Hypercube_internetwork_topology" title="Hypercube internetwork topology">hypercube</a>, <a href="/enwiki/wiki/Mesh_networking" title="Mesh networking">meshes</a> and <a href="/enwiki/wiki/Tree_network" title="Tree network">tree networks</a> to <a href="/enwiki/wiki/Genetic_algorithm_scheduling" title="Genetic algorithm scheduling">genetic algorithm scheduling</a> to <a href="/enwiki/wiki/Randomized_algorithm" title="Randomized algorithm">randomized algorithms</a> such as <a href="/enwiki/wiki/Branching_random_walk" title="Branching random walk">random walks with branching</a> and randomized <a href="/enwiki/wiki/Time_to_live" title="Time to live">time to live</a> (TTL).
</p><p>Many SoC researchers consider NoC architectures to be the future of SoC design because they have been shown to efficiently meet power and throughput needs of SoC designs. Current NoC architectures are two-dimensional. 2D IC design has limited <a href="/enwiki/wiki/Floorplan_(microelectronics)" title="Floorplan (microelectronics)">floorplanning</a> choices as the number of cores in SoCs increase, so as <a href="/enwiki/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">three-dimensional integrated circuits</a> (3DICs) emerge, SoC designers are looking towards building three-dimensional on-chip networks known as 3DNoCs.<sup id="cite_ref-:0_10-7" class="reference"><a href="#cite_note-:0-10">[9]</a></sup>
</p>
<h2><span class="mw-headline" id="Design_flow">Design flow</span></h2>
<table class="box-More_citations_needed_section plainlinks metadata ambox ambox-content ambox-Refimprove" role="presentation"><tbody><tr><td class="mbox-image"><div style="width:52px"><a href="/enwiki/wiki/File:Question_book-new.svg" class="image"><img alt="" src="/upwiki/wikipedia/en/thumb/9/99/Question_book-new.svg/50px-Question_book-new.svg.png" decoding="async" width="50" height="39" srcset="/upwiki/wikipedia/en/thumb/9/99/Question_book-new.svg/75px-Question_book-new.svg.png 1.5x, /upwiki/wikipedia/en/thumb/9/99/Question_book-new.svg/100px-Question_book-new.svg.png 2x" data-file-width="512" data-file-height="399" /></a></div></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs additional citations for <a href="/enwiki/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">verification</a></b>.<span class="hide-when-compact"> Please help <a class="external text" href="https://en.wikipedia.org/enwiki/w/index.php?title=System_on_a_chip&action=edit">improve this article</a> by <a href="/enwiki/wiki/Help:Referencing_for_beginners" title="Help:Referencing for beginners">adding citations to reliable sources</a>. Unsourced material may be challenged and removed.</span> <span class="date-container"><i>(<span class="date">March 2017</span>)</i></span><span class="hide-when-compact"><i> (<a href="/enwiki/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this template message</a>)</i></span></div></td></tr></tbody></table>
<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1033289096"/><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/enwiki/wiki/Design_flow_(EDA)" title="Design flow (EDA)">Electronics design flow</a>, <a href="/enwiki/wiki/Physical_design_(electronics)" title="Physical design (electronics)">Physical design (electronics)</a>, and <a href="/enwiki/wiki/Platform-based_design" title="Platform-based design">Platform-based design</a></div><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1033289096"/><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/enwiki/wiki/Systems_design" title="Systems design">Systems design</a> and <a href="/enwiki/wiki/Software_design" title="Software design">Software design process</a></div><div class="thumb tright"><div class="thumbinner" style="width:277px;"><a href="/enwiki/wiki/File:SoCDesignFlow.svg" class="image"><img alt="" src="/upwiki/wikipedia/commons/thumb/5/58/SoCDesignFlow.svg/275px-SoCDesignFlow.svg.png" decoding="async" width="275" height="340" class="thumbimage" srcset="/upwiki/wikipedia/commons/thumb/5/58/SoCDesignFlow.svg/413px-SoCDesignFlow.svg.png 1.5x, /upwiki/wikipedia/commons/thumb/5/58/SoCDesignFlow.svg/550px-SoCDesignFlow.svg.png 2x" data-file-width="560" data-file-height="693" /></a> <div class="thumbcaption"><div class="magnify"><a href="/enwiki/wiki/File:SoCDesignFlow.svg" class="internal" title="Enlarge"></a></div>SoC design flow</div></div></div>
<p>A system on a chip consists of both the <a href="/enwiki/wiki/Electronic_hardware" title="Electronic hardware">hardware</a>, described in <a href="#Structure">§ Structure</a>, and the <a href="/enwiki/wiki/Software" title="Software">software</a> controlling the microcontroller, microprocessor or digital signal processor cores, peripherals and interfaces. The <a href="/enwiki/wiki/Design_flow_(EDA)" title="Design flow (EDA)">design flow</a> for an SoC aims to develop this hardware and software at the same time, also known as architectural co-design. The design flow must also take into account optimizations (<a href="#Optimization_goals">§ Optimization goals</a>) and constraints.
</p><p>Most SoCs are developed from pre-qualified hardware component <a href="/enwiki/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">IP core specifications</a> for the hardware elements and <a href="/enwiki/wiki/Execution_unit" title="Execution unit">execution units</a>, collectively "blocks", described above, together with software <a href="/enwiki/wiki/Device_driver" title="Device driver">device drivers</a> that may control their operation. Of particular importance are the <a href="/enwiki/wiki/Protocol_stack" title="Protocol stack">protocol stacks</a> that drive industry-standard interfaces like <a href="/enwiki/wiki/Universal_Serial_Bus" class="mw-redirect" title="Universal Serial Bus">USB</a>. The hardware blocks are put together using <a href="/enwiki/wiki/Computer-aided_design" title="Computer-aided design">computer-aided design</a> tools, specifically <a href="/enwiki/wiki/Electronic_design_automation" title="Electronic design automation">electronic design automation</a> tools; the <a href="/enwiki/wiki/Modular_programming" title="Modular programming">software modules</a> are integrated using a software <a href="/enwiki/wiki/Integrated_development_environment" title="Integrated development environment">integrated development environment</a>.
</p><p>SoCs components are also often designed in <a href="/enwiki/wiki/High-level_programming_language" title="High-level programming language">high-level programming languages</a> such as <a href="/enwiki/wiki/C%2B%2B" title="C++">C++</a>, <a href="/enwiki/wiki/MATLAB" title="MATLAB">MATLAB</a> or <a href="/enwiki/wiki/SystemC" title="SystemC">SystemC</a> and converted to <a href="/enwiki/wiki/Register-transfer_level" title="Register-transfer level">RTL</a> designs through <a href="/enwiki/wiki/High-level_synthesis" title="High-level synthesis">high-level synthesis</a> (HLS) tools such as <a href="/enwiki/wiki/C_to_HDL" title="C to HDL">C to HDL</a> or <a href="/enwiki/wiki/Flow_to_HDL" title="Flow to HDL">flow to HDL</a>.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11">[10]</a></sup> HLS products called "algorithmic synthesis" allow designers to use C++ to model and synthesize system, circuit, software and verification levels all in one high level language commonly known to <a href="/enwiki/wiki/Computer_engineers" class="mw-redirect" title="Computer engineers">computer engineers</a> in a manner independent of time scales, which are typically specified in HDL.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12">[11]</a></sup> Other components can remain software and be compiled and embedded onto <a href="/enwiki/wiki/Soft_microprocessor" title="Soft microprocessor">soft-core processors</a> included in the SoC as modules in HDL as <a href="/enwiki/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">IP cores</a>.
</p><p>Once the <a href="/enwiki/wiki/Computer_architecture" title="Computer architecture">architecture</a> of the SoC has been defined, any new hardware elements are written in an abstract <a href="/enwiki/wiki/Hardware_description_language" title="Hardware description language">hardware description language</a> termed <a href="/enwiki/wiki/Register-transfer_level" title="Register-transfer level">register transfer level</a> (RTL) which defines the circuit behavior, or synthesized into RTL from a high level language through high-level synthesis. These elements are connected together in a hardware description language to create the full SoC design. The logic specified to connect these components and convert between possibly different interfaces provided by different vendors is called <a href="/enwiki/wiki/Glue_logic" title="Glue logic">glue logic</a>.
</p>
<h3><span class="mw-headline" id="Design_verification">Design verification</span></h3>
<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1033289096"/><div role="note" class="hatnote navigation-not-searchable">Further information: <a href="/enwiki/wiki/Functional_verification" title="Functional verification">Functional verification</a> and <a href="/enwiki/wiki/Signoff_(electronic_design_automation)" title="Signoff (electronic design automation)">Signoff (electronic design automation)</a></div>
<p>Chips are verified for validation correctness before being sent to a <a href="/enwiki/wiki/Semiconductor_fabrication_plant" title="Semiconductor fabrication plant">semiconductor foundry</a>. This process is called <a href="/enwiki/wiki/Functional_verification" title="Functional verification">functional verification</a> and it accounts for a significant portion of the time and energy expended in the <a href="/enwiki/wiki/Integrated_circuit_development" class="mw-redirect" title="Integrated circuit development">chip design life cycle</a>, often quoted as 70%.<sup id="cite_ref-70%_verification?_13-0" class="reference"><a href="#cite_note-70%_verification?-13">[12]</a></sup><sup id="cite_ref-verification_vs._validation_14-0" class="reference"><a href="#cite_note-verification_vs._validation-14">[13]</a></sup> With the growing complexity of chips, <a href="/enwiki/wiki/Hardware_verification_language" title="Hardware verification language">hardware verification languages</a> like <a href="/enwiki/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a>, <a href="/enwiki/wiki/SystemC" title="SystemC">SystemC</a>, <a href="/enwiki/wiki/E_(verification_language)" title="E (verification language)">e</a>, and <a href="/enwiki/wiki/OpenVera" title="OpenVera">OpenVera</a> are being used. <a href="/enwiki/wiki/Software_bug" title="Software bug">Bugs</a> found in the verification stage are reported to the designer.
</p><p>Traditionally, engineers have employed simulation acceleration, <a href="/enwiki/wiki/Emulator" title="Emulator">emulation</a> or prototyping on <a href="/enwiki/wiki/Reconfigurable_computing" title="Reconfigurable computing">reprogrammable hardware</a> to verify and debug hardware and software for SoC designs prior to the finalization of the design, known as <a href="/enwiki/wiki/Tape-out" title="Tape-out">tape-out</a>. <a href="/enwiki/wiki/Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate arrays</a> (FPGAs) are favored for prototyping SoCs because <a href="/enwiki/wiki/FPGA_prototyping" title="FPGA prototyping">FPGA prototypes</a> are reprogrammable, allow <a href="/enwiki/wiki/Debugging" title="Debugging">debugging</a> and are more flexible than <a href="/enwiki/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">application-specific integrated circuits</a> (ASICs).<sup id="cite_ref-nm_prototyping_15-0" class="reference"><a href="#cite_note-nm_prototyping-15">[14]</a></sup><sup id="cite_ref-Reason_to_debug_in_FPGA_16-0" class="reference"><a href="#cite_note-Reason_to_debug_in_FPGA-16">[15]</a></sup>
</p><p>With high capacity and fast compilation time, simulation acceleration and emulation are powerful technologies that provide wide visibility into systems. Both technologies, however, operate slowly, on the order of MHz, which may be significantly slower – up to 100 times slower – than the SoC's operating frequency. Acceleration and emulation boxes are also very large and expensive at over US$1 million.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/enwiki/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (May 2018)">citation needed</span></a></i>]</sup>
</p><p>FPGA prototypes, in contrast, use FPGAs directly to enable engineers to validate and test at, or close to, a system's full operating frequency with real-world stimuli. Tools such as Certus<sup id="cite_ref-17" class="reference"><a href="#cite_note-17">[16]</a></sup> are used to insert probes in the FPGA RTL that make signals available for observation. This is used to debug hardware, firmware and software interactions across multiple FPGAs with capabilities similar to a logic analyzer.
</p><p>In parallel, the hardware elements are grouped and passed through a process of <a href="/enwiki/wiki/Logic_synthesis" title="Logic synthesis">logic synthesis</a>, during which performance constraints, such as operational frequency and expected signal delays, are applied. This generates an output known as a <a href="/enwiki/wiki/Netlist" title="Netlist">netlist</a> describing the design as a physical circuit and its interconnections. These netlists are combined with the <a href="/enwiki/wiki/Glue_logic" title="Glue logic">glue logic</a> connecting the components to produce the schematic description of the SoC as a circuit which can be <a href="/enwiki/wiki/Printed_circuit_board" title="Printed circuit board">printed</a> onto a chip. This process is known as <a href="/enwiki/wiki/Place_and_route" title="Place and route">place and route</a> and precedes <a href="/enwiki/wiki/Tape-out" title="Tape-out">tape-out</a> in the event that the SoCs are produced as <a href="/enwiki/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">application-specific integrated circuits</a> (ASIC).
</p>
<h2><span class="mw-headline" id="Optimization_goals">Optimization goals</span></h2>
<p>SoCs must optimize <a href="/enwiki/wiki/Power_consumption" class="mw-redirect" title="Power consumption">power use</a>, area on <a href="/enwiki/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">die</a>, communication, positioning for <a href="/enwiki/wiki/Locality_of_reference" title="Locality of reference">locality</a> between modular units and other factors. Optimization is necessarily a design goal of SoCs. If optimization was not necessary, the engineers would use a <a href="/enwiki/wiki/Multi-chip_module" title="Multi-chip module">multi-chip module</a> architecture without accounting for the area utilization, power consumption or performance of the system to the same extent.
</p><p>Common optimization targets for SoC designs follow, with explanations of each. In general, optimizing any of these quantities may be a hard <a href="/enwiki/wiki/Combinatorial_optimization" title="Combinatorial optimization">combinatorial optimization</a> problem, and can indeed be <a href="/enwiki/wiki/NP-hardness" title="NP-hardness">NP-hard</a> fairly easily. Therefore, sophisticated <a href="/enwiki/wiki/Optimization_algorithm" class="mw-redirect" title="Optimization algorithm">optimization algorithms</a> are often required and it may be practical to use <a href="/enwiki/wiki/Approximation_algorithm" title="Approximation algorithm">approximation algorithms</a> or <a href="/enwiki/wiki/Heuristic_(computer_science)" title="Heuristic (computer science)">heuristics</a> in some cases. Additionally, most SoC designs contain <a href="/enwiki/wiki/Multivariate_optimization" class="mw-redirect" title="Multivariate optimization">multiple variables to optimize simultaneously</a>, so <a href="/enwiki/wiki/Pareto_efficiency" title="Pareto efficiency">Pareto efficient</a> solutions are sought after in SoC design. Oftentimes the goals of optimizing some of these quantities are directly at odds, further adding complexity to design optimization of SoCs and introducing <a href="/enwiki/wiki/Trade-off#Engineering" title="Trade-off">trade-offs</a> in system design.
</p><p>For broader coverage of trade-offs and <a href="/enwiki/wiki/Requirements_analysis" title="Requirements analysis">requirements analysis</a>, see <a href="/enwiki/wiki/Requirements_engineering" title="Requirements engineering">requirements engineering</a>.
</p>
<h3><span class="mw-headline" id="Targets">Targets</span></h3>
<h4><span class="mw-headline" id="Power_consumption">Power consumption</span></h4>
<p>SoCs are optimized to minimize the <a href="/enwiki/wiki/Electric_power#Definition" title="Electric power">electrical power</a> used to perform the SoC's functions. Most SoCs must use low power. SoC systems often require long <a href="/enwiki/wiki/Battery_life" class="mw-redirect" title="Battery life">battery life</a> (such as <a href="/enwiki/wiki/Smartphone" title="Smartphone">smartphones</a>), can potentially spending months or years without a power source needing to maintain autonomous function, and often are limited in power use by a high number of <a href="/enwiki/wiki/Embedded_system" title="Embedded system">embedded</a> SoCs being <a href="/enwiki/wiki/Distributed_computing" title="Distributed computing">networked together</a> in an area. Additionally, energy costs can be high and conserving energy will reduce the <a href="/enwiki/wiki/Total_cost_of_ownership" title="Total cost of ownership">total cost of ownership</a> of the SoC. Finally, <a href="/enwiki/wiki/Waste_heat" title="Waste heat">waste heat</a> from high energy consumption can damage other circuit components if too much heat is dissipated, giving another pragmatic reason to conserve energy. The amount of <a href="/enwiki/wiki/Energy" title="Energy">energy</a> used in a circuit is the <a href="/enwiki/wiki/Integral" title="Integral">integral</a> of <a href="/enwiki/wiki/Power_(physics)" title="Power (physics)">power</a> consumed with respect to time, and the <a href="/enwiki/wiki/Mean_value_theorem" title="Mean value theorem">average rate</a> of power consumption is the product of <a href="/enwiki/wiki/Electric_current" title="Electric current">current</a> by <a href="/enwiki/wiki/Voltage" title="Voltage">voltage</a>. Equivalently, by <a href="/enwiki/wiki/Ohm%27s_law" title="Ohm's law">Ohm's law</a>, power is current squared times resistance or voltage squared divided by <a href="/enwiki/wiki/Resistance_(physics)" class="mw-redirect" title="Resistance (physics)">resistance</a>:
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<annotation encoding="application/x-tex">{\displaystyle P=IV={\frac {V^{2}}{R}}={I^{2}}{R}}</annotation>
</semantics>
</math></div><img src="https://wikimedia.org/enwiki/api/rest_v1/media/math/render/svg/b7ea74b4b52b63f4bf75bcf2eaeecd3c8333bb32" class="mwe-math-fallback-image-display" aria-hidden="true" style="vertical-align: -2.005ex; width:21.842ex; height:5.843ex;" alt="{\displaystyle P=IV={\frac {V^{2}}{R}}={I^{2}}{R}}"/></div>SoCs are frequently embedded in <a href="/enwiki/wiki/Mobile_device" title="Mobile device">portable devices</a> such as <a href="/enwiki/wiki/Smartphones" class="mw-redirect" title="Smartphones">smartphones</a>, <a href="/enwiki/wiki/GPS_navigation_device" class="mw-redirect" title="GPS navigation device">GPS navigation devices</a>, digital <a href="/enwiki/wiki/Digital_watch" class="mw-redirect" title="Digital watch">watches</a> (including <a href="/enwiki/wiki/Smartwatch" title="Smartwatch">smartwatches</a>) and <a href="/enwiki/wiki/Netbook" title="Netbook">netbooks</a>. Customers want long battery lives for <a href="/enwiki/wiki/Mobile_computing" title="Mobile computing">mobile computing</a> devices, another reason that power consumption must be minimized in SoCs. <a href="/enwiki/wiki/Multimedia_application" class="mw-redirect" title="Multimedia application">Multimedia applications</a> are often executed on these devices, including <a href="/enwiki/wiki/Video_game" title="Video game">video games</a>, <a href="/enwiki/wiki/Video_streaming" class="mw-redirect" title="Video streaming">video streaming</a>, <a href="/enwiki/wiki/Image_processing" class="mw-redirect" title="Image processing">image processing</a>; all of which have grown in <a href="/enwiki/wiki/Computational_complexity" title="Computational complexity">computational complexity</a> in recent years with user demands and expectations for higher-<a href="/enwiki/wiki/Video_quality" title="Video quality">quality</a> multimedia. Computation is more demanding as expectations move towards <a href="/enwiki/wiki/3D_video" class="mw-redirect" title="3D video">3D video</a> at <a href="/enwiki/wiki/High_resolution" class="mw-redirect" title="High resolution">high resolution</a> with <a href="/enwiki/wiki/List_of_video_compression_formats" class="mw-redirect" title="List of video compression formats">multiple standards</a>, so SoCs performing multimedia tasks must be computationally capable platform while being low power to run off a standard mobile battery.<sup id="cite_ref-:1_8-3" class="reference"><a href="#cite_note-:1-8">[8]</a></sup><sup class="reference" style="white-space:nowrap;">:<span>3</span></sup>
</p>
<h4><span class="mw-headline" id="Performance_per_watt">Performance per watt</span></h4>
<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1033289096"/><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/enwiki/wiki/Green_computing" title="Green computing">Green computing</a></div>
<p>SoCs are optimized to maximize <a href="/enwiki/wiki/Power_efficiency" class="mw-redirect" title="Power efficiency">power efficiency</a> in performance per watt: maximize the performance of the SoC given a budget of power usage. Many applications such as <a href="/enwiki/wiki/Edge_computing" title="Edge computing">edge computing</a>, <a href="/enwiki/wiki/Distributed_processing" class="mw-redirect" title="Distributed processing">distributed processing</a> and <a href="/enwiki/wiki/Ambient_intelligence" title="Ambient intelligence">ambient intelligence</a> require a certain level of <a href="/enwiki/wiki/Computer_performance" title="Computer performance">computational performance</a>, but power is limited in most SoC environments. The <a href="/enwiki/wiki/ARM_architecture" title="ARM architecture">ARM architecture</a> has greater performance per watt than <a href="/enwiki/wiki/X86" title="X86">x86</a> in embedded systems, so it is preferred over x86 for most SoC applications requiring an <a href="/enwiki/wiki/Soft_microprocessor" title="Soft microprocessor">embedded processor</a>.
</p>
<h4><span class="mw-headline" id="Waste_heat">Waste heat</span></h4>
<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1033289096"/><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/enwiki/wiki/Heat_generation_in_integrated_circuits" title="Heat generation in integrated circuits">Heat generation in integrated circuits</a></div><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1033289096"/><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/enwiki/wiki/Thermal_management_(electronics)" title="Thermal management (electronics)">Thermal management in electronics</a> and <a href="/enwiki/wiki/Thermal_design_power" title="Thermal design power">Thermal design power</a></div>
<p>SoC designs are optimized to minimize <a href="/enwiki/wiki/Waste_heat" title="Waste heat">waste heat</a> <a href="/enwiki/wiki/Dissipation" title="Dissipation">output</a> on the chip. As with other <a href="/enwiki/wiki/Integrated_circuit" title="Integrated circuit">integrated circuits</a>, heat generated due to high <a href="/enwiki/wiki/Power_density" title="Power density">power density</a> are the <a href="/enwiki/wiki/Bottleneck_(engineering)" title="Bottleneck (engineering)">bottleneck</a> to further <a href="/enwiki/wiki/Miniaturization" title="Miniaturization">miniaturization</a> of components.<sup id="cite_ref-:2_18-0" class="reference"><a href="#cite_note-:2-18">[17]</a></sup><sup class="reference" style="white-space:nowrap;">:<span>1</span></sup> The power densities of high speed integrated circuits, particularly microprocessors and including SoCs, have become highly uneven. Too much waste heat can damage circuits and erode <a href="/enwiki/wiki/Reliability_(semiconductor)" title="Reliability (semiconductor)">reliability</a> of the circuit over time. High temperatures and thermal stress negatively impact reliability, <a href="/enwiki/wiki/Stress_migration" title="Stress migration">stress migration</a>, decreased <a href="/enwiki/wiki/Mean_time_between_failures" title="Mean time between failures">mean time between failures</a>, <a href="/enwiki/wiki/Electromigration" title="Electromigration">electromigration</a>, <a href="/enwiki/wiki/Wire_bonding" title="Wire bonding">wire bonding</a>, <a href="/enwiki/wiki/Metastability_(electronics)" title="Metastability (electronics)">metastability</a> and other performance degradation of the SoC over time.<sup id="cite_ref-:2_18-1" class="reference"><a href="#cite_note-:2-18">[17]</a></sup><sup class="reference" style="white-space:nowrap;">:<span>2–9</span></sup>
</p><p>In particular, most SoCs are in a small physical area or volume and therefore the effects of waste heat are compounded because there is little room for it to diffuse out of the system. Because of high <a href="/enwiki/wiki/Transistor_count" title="Transistor count">transistor counts</a> on modern devices due to <a href="/enwiki/wiki/Moore%27s_law" title="Moore's law">Moore's law</a>, oftentimes a layout of sufficient throughput and high <a href="/enwiki/wiki/Transistors_density" class="mw-redirect" title="Transistors density">transistor density</a> is physically realizable from <a href="/enwiki/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">fabrication processes</a> but would result in unacceptably high amounts of heat in the circuit's volume.<sup id="cite_ref-:2_18-2" class="reference"><a href="#cite_note-:2-18">[17]</a></sup><sup class="reference" style="white-space:nowrap;">:<span>1</span></sup>
</p><p>These thermal effects force SoC and other chip designers to apply conservative <a href="/enwiki/wiki/Design_margin" class="mw-redirect" title="Design margin">design margins</a>, creating less performant devices to mitigate the risk of <a href="/enwiki/wiki/Catastrophic_failure" title="Catastrophic failure">catastrophic failure</a>. Due to increased <a href="/enwiki/wiki/Transistors_density" class="mw-redirect" title="Transistors density">transistor densities</a> as length scales get smaller, each <a href="/enwiki/wiki/Semiconductor_node" class="mw-redirect" title="Semiconductor node">process generation</a> produces more heat output than the last. Compounding this problem, SoC architectures are usually heterogeneous, creating spatially inhomogeneous <a href="/enwiki/wiki/Heat_flux" title="Heat flux">heat fluxes</a>, which cannot be effectively mitigated by uniform <a href="/enwiki/wiki/Passive_cooling" title="Passive cooling">passive cooling</a>.<sup id="cite_ref-:2_18-3" class="reference"><a href="#cite_note-:2-18">[17]</a></sup><sup class="reference" style="white-space:nowrap;">:<span>1</span></sup>
</p>
<h4><span class="mw-headline" id="Throughput">Throughput</span></h4>
<table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><a href="/enwiki/wiki/File:Wiki_letter_w_cropped.svg" class="image"><img alt="[icon]" src="/upwiki/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" srcset="/upwiki/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/30px-Wiki_letter_w_cropped.svg.png 1.5x, /upwiki/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/enwiki/w/index.php?title=System_on_a_chip&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">October 2018</span>)</i></span></div></td></tr></tbody></table>
<p>SoCs are optimized to maximize computational and communications <a href="/enwiki/wiki/Throughput" title="Throughput">throughput</a>.
</p>
<h4><span class="mw-headline" id="Latency">Latency</span></h4>
<table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><a href="/enwiki/wiki/File:Wiki_letter_w_cropped.svg" class="image"><img alt="[icon]" src="/upwiki/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" srcset="/upwiki/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/30px-Wiki_letter_w_cropped.svg.png 1.5x, /upwiki/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/enwiki/w/index.php?title=System_on_a_chip&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">October 2018</span>)</i></span></div></td></tr></tbody></table>
<p>SoCs are optimized to minimize <a href="/enwiki/wiki/Latency_(engineering)" title="Latency (engineering)">latency</a> for some or all of their functions. This can be accomplished by <a href="/enwiki/wiki/Integrated_circuit_layout" title="Integrated circuit layout">laying out</a> elements with proper proximity and <a href="/enwiki/wiki/Locality_of_reference" title="Locality of reference">locality</a> to each-other to minimize the interconnection delays and maximize the speed at which data is communicated between modules, <a href="/enwiki/wiki/Execution_unit" title="Execution unit">functional units</a> and memories. In general, optimizing to minimize latency is an <a href="/enwiki/wiki/NP-completeness" title="NP-completeness">NP-complete</a> problem equivalent to the <a href="/enwiki/wiki/Boolean_satisfiability_problem" title="Boolean satisfiability problem">boolean satisfiability problem</a>.
</p><p>For <a href="/enwiki/wiki/Task_(computing)" title="Task (computing)">tasks</a> running on processor cores, latency and throughput can be improved with <a href="/enwiki/wiki/Scheduling_(computing)" title="Scheduling (computing)">task scheduling</a>. Some tasks run in application-specific hardware units, however, and even task scheduling may not be sufficient to optimize all software-based tasks to meet timing and throughput constraints.
</p>
<h3><span class="mw-headline" id="Methodologies">Methodologies</span></h3>
<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1033289096"/><div role="note" class="hatnote navigation-not-searchable">Further information: <a href="/enwiki/wiki/Multi-objective_optimization" title="Multi-objective optimization">Multi-objective optimization</a>, <a href="/enwiki/wiki/Multiple-criteria_decision_analysis" title="Multiple-criteria decision analysis">Multiple-criteria decision analysis</a>, and <a href="/enwiki/wiki/Architecture_tradeoff_analysis_method" title="Architecture tradeoff analysis method">Architecture tradeoff analysis</a></div>
<table class="box-Expand_section plainlinks metadata ambox ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><div style="width:52px"><a href="/enwiki/wiki/File:Wiki_letter_w_cropped.svg" class="image"><img alt="[icon]" src="/upwiki/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/44px-Wiki_letter_w_cropped.svg.png" decoding="async" width="44" height="31" srcset="/upwiki/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/66px-Wiki_letter_w_cropped.svg.png 1.5x, /upwiki/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/88px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></div></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/enwiki/w/index.php?title=System_on_a_chip&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">October 2018</span>)</i></span></div></td></tr></tbody></table>
<p>Systems on chip are modeled with standard hardware <a href="/enwiki/wiki/Verification_and_validation" title="Verification and validation">verification and validation</a> techniques, but additional techniques are used to model and optimize SoC design alternatives to make the system optimal with respect to <a href="/enwiki/wiki/Multiple-criteria_decision_analysis" title="Multiple-criteria decision analysis">multiple-criteria decision analysis</a> on the above optimization targets.
</p>
<h4><span class="mw-headline" id="Task_scheduling">Task scheduling</span></h4>
<p><a href="/enwiki/wiki/Scheduling_(computing)" title="Scheduling (computing)">Task scheduling</a> is an important activity in any computer system with multiple <a href="/enwiki/wiki/Process_(computing)" title="Process (computing)">processes</a> or <a href="/enwiki/wiki/Thread_(computing)" title="Thread (computing)">threads</a> sharing a single processor core. It is important to reduce <a href="#Latency">§ Latency</a> and increase <a href="#Throughput">§ Throughput</a> for <a href="/enwiki/wiki/Embedded_software" title="Embedded software">embedded software</a> running on an SoC's <a href="#Processor_cores">§ Processor cores</a>. Not every important computing activity in a SoC is performed in software running on on-chip processors, but scheduling can drastically improve performance of software-based tasks and other tasks involving <a href="/enwiki/wiki/Shared_resource" title="Shared resource">shared resources</a>.
</p><p>SoCs often schedule tasks according to <a href="/enwiki/wiki/Network_scheduling" class="mw-redirect" title="Network scheduling">network scheduling</a> and <a href="/enwiki/wiki/Stochastic_scheduling" title="Stochastic scheduling">randomized scheduling</a> algorithms.
</p>
<h4><span class="mw-headline" id="Pipelining">Pipelining</span></h4>
<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1033289096"/><div role="note" class="hatnote navigation-not-searchable">For broader coverage of this topic, see <a href="/enwiki/wiki/Pipeline_(computing)" title="Pipeline (computing)">Pipeline (computing)</a>.</div>
<p>Hardware and software tasks are often pipelined in <a href="/enwiki/wiki/Processor_design" title="Processor design">processor design</a>. Pipelining is an important principle for <a href="/enwiki/wiki/Speedup" title="Speedup">speedup</a> in <a href="/enwiki/wiki/Computer_architecture" title="Computer architecture">computer architecture</a>. They are frequently used in <a href="/enwiki/wiki/GPU" class="mw-redirect" title="GPU">GPUs</a> (<a href="/enwiki/wiki/Graphics_pipeline" title="Graphics pipeline">graphics pipeline</a>) and RISC processors (evolutions of the <a href="/enwiki/wiki/Classic_RISC_pipeline" title="Classic RISC pipeline">classic RISC pipeline</a>), but are also applied to application-specific tasks such as <a href="/enwiki/wiki/Digital_signal_processing" title="Digital signal processing">digital signal processing</a> and multimedia manipulations in the context of SoCs.<sup id="cite_ref-:1_8-4" class="reference"><a href="#cite_note-:1-8">[8]</a></sup>
</p>
<h4><span class="mw-headline" id="Probabilistic_modeling">Probabilistic modeling</span></h4>
<p>SoCs are often analyzed though <a href="/enwiki/wiki/Probabilistic_model" class="mw-redirect" title="Probabilistic model">probabilistic models</a>, <a href="/enwiki/wiki/Queueing_theory#Queueing_networks" title="Queueing theory">Queueing theory § Queueing networks</a> and <a href="/enwiki/wiki/Markov_chain" title="Markov chain">Markov chains</a>. For instance, <a href="/enwiki/wiki/Little%27s_law" title="Little's law">Little's law</a> allows SoC states and NoC buffers to be modeled as arrival processes and analyzed through <a href="/enwiki/wiki/Poisson_random_variable" class="mw-redirect" title="Poisson random variable">Poisson random variables</a> and <a href="/enwiki/wiki/Poisson_process" class="mw-redirect" title="Poisson process">Poisson processes</a>.
</p>
<h4><span class="mw-headline" id="Markov_chains">Markov chains</span></h4>
<p>SoCs are often modeled with <a href="/enwiki/wiki/Markov_chain" title="Markov chain">Markov chains</a>, both <a href="/enwiki/wiki/Markov_chain#Discrete-time_Markov_chain" title="Markov chain">discrete time</a> and <a href="/enwiki/wiki/Markov_chain#Continuous-time_Markov_chain" title="Markov chain">continuous time</a> variants. Markov chain modeling allows <a href="/enwiki/wiki/Asymptotic_analysis" title="Asymptotic analysis">asymptotic analysis</a> of the SoC's <a href="/enwiki/wiki/Markov_chain#Steady-state_analysis_and_limiting_distributions" title="Markov chain">steady state distribution</a> of power, heat, latency and other factors to allow design decisions to be optimized for the common case.
</p>
<h2><span class="mw-headline" id="Fabrication">Fabrication</span></h2>
<table class="box-More_citations_needed_section plainlinks metadata ambox ambox-content ambox-Refimprove" role="presentation"><tbody><tr><td class="mbox-image"><div style="width:52px"><a href="/enwiki/wiki/File:Question_book-new.svg" class="image"><img alt="" src="/upwiki/wikipedia/en/thumb/9/99/Question_book-new.svg/50px-Question_book-new.svg.png" decoding="async" width="50" height="39" srcset="/upwiki/wikipedia/en/thumb/9/99/Question_book-new.svg/75px-Question_book-new.svg.png 1.5x, /upwiki/wikipedia/en/thumb/9/99/Question_book-new.svg/100px-Question_book-new.svg.png 2x" data-file-width="512" data-file-height="399" /></a></div></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs additional citations for <a href="/enwiki/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">verification</a></b>.<span class="hide-when-compact"> Please help <a class="external text" href="https://en.wikipedia.org/enwiki/w/index.php?title=System_on_a_chip&action=edit">improve this article</a> by <a href="/enwiki/wiki/Help:Referencing_for_beginners" title="Help:Referencing for beginners">adding citations to reliable sources</a>. Unsourced material may be challenged and removed.</span> <span class="date-container"><i>(<span class="date">March 2017</span>)</i></span><span class="hide-when-compact"><i> (<a href="/enwiki/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this template message</a>)</i></span></div></td></tr></tbody></table><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1033289096"/><div role="note" class="hatnote navigation-not-searchable">Further information: <a href="/enwiki/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></div>
<p>SoC chips are typically <a href="/enwiki/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">fabricated</a> using <a href="/enwiki/wiki/Metal%E2%80%93oxide%E2%80%93semiconductor" class="mw-redirect" title="Metal–oxide–semiconductor">metal–oxide–semiconductor</a> (MOS) technology.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19">[18]</a></sup> The netlists described above are used as the basis for the physical design (<a href="/enwiki/wiki/Place_and_route" title="Place and route">place and route</a>) flow to convert the designers' intent into the design of the SoC. Throughout this conversion process, the design is analyzed with static timing modeling, simulation and other tools to ensure that it meets the specified operational parameters such as frequency, power consumption and dissipation, functional integrity (as described in the register transfer level code) and electrical integrity.
</p><p>When all known bugs have been rectified and these have been re-verified and all physical design checks are done, the physical design files describing each layer of the chip are sent to the foundry's mask shop where a full set of glass lithographic masks will be etched. These are sent to a wafer fabrication plant to create the SoC dice before packaging and testing.
</p><p>SoCs can be fabricated by several technologies, including:
</p>
<ul><li><a href="/enwiki/wiki/Full_custom" title="Full custom">Full custom</a> ASIC</li>
<li><a href="/enwiki/wiki/Standard_cell" title="Standard cell">Standard cell</a> ASIC</li>
<li><a href="/enwiki/wiki/Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li></ul>
<p>ASICs consume less power and are faster than FPGAs but cannot be reprogrammed and are expensive to manufacture. FPGA designs are more suitable for lower volume designs, but after enough units of production ASICs reduce the total cost of ownership.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20">[19]</a></sup>
</p><p>SoC designs consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. With fewer packages in the system, assembly costs are reduced as well.
</p><p>However, like most <a href="/enwiki/wiki/Very-large-scale_integration" class="mw-redirect" title="Very-large-scale integration">very-large-scale integration</a> (VLSI) designs, the total cost<sup class="noprint Inline-Template" style="margin-left:0.1em; white-space:nowrap;">[<i><a href="/enwiki/wiki/Wikipedia:Please_clarify" title="Wikipedia:Please clarify"><span title="what kind of cost? (May 2018)">clarification needed</span></a></i>]</sup> is higher for one large chip than for the same functionality distributed over several smaller chips, because of <a href="/enwiki/wiki/Semiconductor_device_fabrication#Device_test" title="Semiconductor device fabrication">lower yields</a><sup class="noprint Inline-Template" style="margin-left:0.1em; white-space:nowrap;">[<i><a href="/enwiki/wiki/Wikipedia:Please_clarify" title="Wikipedia:Please clarify"><span title="confusing to non-experts (May 2018)">clarification needed</span></a></i>]</sup> and higher <a href="/enwiki/wiki/Non-recurring_engineering" title="Non-recurring engineering">non-recurring engineering</a> costs.
</p><p>When it is not feasible to construct an SoC for a particular application, an alternative is a <a href="/enwiki/wiki/System_in_package" class="mw-redirect" title="System in package">system in package</a> (SiP) comprising a number of chips in a single <a href="/enwiki/wiki/Chip_carrier" title="Chip carrier">package</a>. When produced in large volumes, SoC is more cost-effective than SiP because its packaging is simpler.<sup id="cite_ref-21" class="reference"><a href="#cite_note-21">[20]</a></sup> Another reason SiP may be preferred is <a href="/enwiki/wiki/Waste_heat" title="Waste heat">waste heat</a> may be too high in a SoC for a given purpose because functional components are too close together, and in an SiP heat will dissipate better from different functional modules since they are physically further apart.
</p>
<h2><span class="mw-headline" id="Benchmarks">Benchmarks</span></h2>
<table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><a href="/enwiki/wiki/File:Wiki_letter_w_cropped.svg" class="image"><img alt="[icon]" src="/upwiki/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" srcset="/upwiki/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/30px-Wiki_letter_w_cropped.svg.png 1.5x, /upwiki/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/enwiki/w/index.php?title=System_on_a_chip&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">October 2018</span>)</i></span></div></td></tr></tbody></table>
<p>SoC <a href="/enwiki/wiki/Research_and_development" title="Research and development">research and development</a> often compares many options. Benchmarks, such as COSMIC,<sup id="cite_ref-22" class="reference"><a href="#cite_note-22">[21]</a></sup> are developed to help such evaluations.
</p>
<h2><span class="mw-headline" id="See_also">See also</span></h2>
<ul><li><a href="/enwiki/wiki/List_of_system-on-a-chip_suppliers" class="mw-redirect" title="List of system-on-a-chip suppliers">List of system-on-a-chip suppliers</a></li>
<li><a href="/enwiki/wiki/Post-silicon_validation" title="Post-silicon validation">Post-silicon validation</a></li>
<li><a href="/enwiki/wiki/ARM_architecture" title="ARM architecture">ARM architecture</a></li>
<li><a href="/enwiki/wiki/Single-board_computer" title="Single-board computer">Single-board computer</a></li>
<li><a href="/enwiki/wiki/System_in_package" class="mw-redirect" title="System in package">System in package</a></li>
<li><a href="/enwiki/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a></li>
<li><a href="/enwiki/wiki/Programmable_system-on-chip" class="mw-redirect" title="Programmable system-on-chip">Programmable SoC</a></li>
<li><a href="/enwiki/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific instruction set processor</a> (ASIP)</li>
<li><a href="/enwiki/wiki/Platform-based_design" title="Platform-based design">Platform-based design</a></li>
<li><a href="/enwiki/wiki/Lab_on_a_chip" class="mw-redirect" title="Lab on a chip">Lab on a chip</a></li>
<li><a href="/enwiki/wiki/Organ_on_a_chip" class="mw-redirect" title="Organ on a chip">Organ on a chip</a> in biomedical technology</li>
<li><a href="/enwiki/wiki/Multi-chip_module" title="Multi-chip module">Multi-chip module</a></li>
<li><a href="/enwiki/wiki/List_of_Qualcomm_Snapdragon_processors" title="List of Qualcomm Snapdragon processors">List of Qualcomm Snapdragon processors</a> - <a href="/enwiki/wiki/Qualcomm" title="Qualcomm">Qualcomm</a></li>
<li><a href="/enwiki/wiki/Exynos" title="Exynos">Exynos</a> - <a href="/enwiki/wiki/Samsung" title="Samsung">Samsung</a></li></ul>
<h2><span class="mw-headline" id="Notes">Notes</span></h2>
<style data-mw-deduplicate="TemplateStyles:r1011085734">.mw-parser-output .reflist{font-size:90%;margin-bottom:0.5em;list-style-type:decimal}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist">
<div class="mw-references-wrap"><ol class="references">
<li id="cite_note-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-9">^</a></b></span> <span class="reference-text">In <a href="/enwiki/wiki/Embedded_system" title="Embedded system">embedded systems</a>, "shields" are analogous to <a href="/enwiki/wiki/Expansion_card" title="Expansion card">expansion cards</a> for <a href="/enwiki/wiki/Personal_computer" title="Personal computer">PCs</a>. They often fit over a <a href="/enwiki/wiki/Microcontroller" title="Microcontroller">microcontroller</a> such as an <a href="/enwiki/wiki/Arduino" title="Arduino">Arduino</a> or <a href="/enwiki/wiki/Single-board_computer" title="Single-board computer">single-board computer</a> such as the <a href="/enwiki/wiki/Raspberry_Pi" title="Raspberry Pi">Raspberry Pi</a> and function as <a href="/enwiki/wiki/Peripheral" title="Peripheral">peripherals</a> for the device.</span>
</li>
</ol></div></div>
<h2><span class="mw-headline" id="References">References</span></h2>
<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1011085734"/><div class="reflist">
<div class="mw-references-wrap mw-references-columns"><ol class="references">
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<li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.imveurope.com/news/qualcomm-launches-socs-embedded-vision">"Qualcomm launches SoCs for embedded vision | Imaging and Machine Vision Europe"</a>. <i>www.imveurope.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2018-10-13</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.imveurope.com&rft.atitle=Qualcomm+launches+SoCs+for+embedded+vision+%7C+Imaging+and+Machine+Vision+Europe&rft_id=https%3A%2F%2Fwww.imveurope.com%2Fnews%2Fqualcomm-launches-socs-embedded-vision&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
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<li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.ifixit.com/Teardown/Samsung+Galaxy+S10+and+S10e+Teardown/120331">"Samsung Galaxy S10 and S10e Teardown"</a>. <i>iFixit</i>. March 6, 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=iFixit&rft.atitle=Samsung+Galaxy+S10+and+S10e+Teardown&rft.date=2019-03-06&rft_id=https%3A%2F%2Fwww.ifixit.com%2FTeardown%2FSamsung%2BGalaxy%2BS10%2Band%2BS10e%2BTeardown%2F120331&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
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<li id="cite_note-:3-4"><span class="mw-cite-backlink">^ <a href="#cite_ref-:3_4-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:3_4-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://www.windowscentral.com/arm-going-after-intel-new-chip-roadmap-through-2020">"ARM is going after Intel with new chip roadmap through 2020"</a>. <i>Windows Central</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2018-10-06</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Windows+Central&rft.atitle=ARM+is+going+after+Intel+with+new+chip+roadmap+through+2020&rft_id=https%3A%2F%2Fwww.windowscentral.com%2Farm-going-after-intel-new-chip-roadmap-through-2020&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
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<li id="cite_note-:4-5"><span class="mw-cite-backlink">^ <a href="#cite_ref-:4_5-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:4_5-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.microsoft.com/en-us/windows/always-connected-laptop-pcs">"Always Connected PCs, Extended Battery Life 4G LTE Laptops | Windows"</a>. <i>www.microsoft.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2018-10-06</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.microsoft.com&rft.atitle=Always+Connected+PCs%2C+Extended+Battery+Life+4G+LTE+Laptops+%7C+Windows&rft_id=https%3A%2F%2Fwww.microsoft.com%2Fen-us%2Fwindows%2Falways-connected-laptop-pcs&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
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<li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://www.qualcomm.com/products/modems">"Gigabit Class LTE, 4G LTE and 5G Cellular Modems | Qualcomm"</a>. <i>Qualcomm</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2018-10-13</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Qualcomm&rft.atitle=Gigabit+Class+LTE%2C+4G+LTE+and+5G+Cellular+Modems+%7C+Qualcomm&rft_id=https%3A%2F%2Fwww.qualcomm.com%2Fproducts%2Fmodems&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
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<li id="cite_note-Furber_ARM-7"><span class="mw-cite-backlink">^ <a href="#cite_ref-Furber_ARM_7-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Furber_ARM_7-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Furber_ARM_7-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite id="CITEREFFurber2000" class="citation book cs1">Furber, Stephen B. (2000). <i>ARM system-on-chip architecture</i>. Harlow, England: Addison-Wesley. <a href="/enwiki/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/enwiki/wiki/Special:BookSources/0201675196" title="Special:BookSources/0201675196"><bdi>0201675196</bdi></a>. <a href="/enwiki/wiki/OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="/enwiki//www.worldcat.org/oclc/44267964">44267964</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=ARM+system-on-chip+architecture&rft.place=Harlow%2C+England&rft.pub=Addison-Wesley&rft.date=2000&rft_id=info%3Aoclcnum%2F44267964&rft.isbn=0201675196&rft.aulast=Furber&rft.aufirst=Stephen+B.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
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<li id="cite_note-:1-8"><span class="mw-cite-backlink">^ <a href="#cite_ref-:1_8-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:1_8-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-:1_8-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-:1_8-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-:1_8-4"><sup><i><b>e</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite class="citation book cs1">Haris Javaid, Sri Parameswaran (2014). <i>Pipelined Multiprocessor System-on-Chip for Multimedia</i>. <a href="/enwiki/wiki/Springer-Verlag" class="mw-redirect" title="Springer-Verlag">Springer</a>. <a href="/enwiki/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/enwiki/wiki/Special:BookSources/9783319011134" title="Special:BookSources/9783319011134"><bdi>9783319011134</bdi></a>. <a href="/enwiki/wiki/OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="/enwiki//www.worldcat.org/oclc/869378184">869378184</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Pipelined+Multiprocessor+System-on-Chip+for+Multimedia&rft.pub=Springer&rft.date=2014&rft_id=info%3Aoclcnum%2F869378184&rft.isbn=9783319011134&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span><span class="cs1-maint citation-comment">CS1 maint: uses authors parameter (<a href="/enwiki/wiki/Category:CS1_maint:_uses_authors_parameter" title="Category:CS1 maint: uses authors parameter">link</a>)</span></span>
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<li id="cite_note-:0-10"><span class="mw-cite-backlink">^ <a href="#cite_ref-:0_10-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:0_10-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-:0_10-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-:0_10-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-:0_10-4"><sup><i><b>e</b></i></sup></a> <a href="#cite_ref-:0_10-5"><sup><i><b>f</b></i></sup></a> <a href="#cite_ref-:0_10-6"><sup><i><b>g</b></i></sup></a> <a href="#cite_ref-:0_10-7"><sup><i><b>h</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite id="CITEREFKunduChattopadhyay2014" class="citation book cs1">Kundu, Santanu; Chattopadhyay, Santanu (2014). <i>Network-on-chip: the Next Generation of System-on-Chip Integration</i> (1st ed.). Boca Raton, FL: CRC Press. <a href="/enwiki/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/enwiki/wiki/Special:BookSources/9781466565272" title="Special:BookSources/9781466565272"><bdi>9781466565272</bdi></a>. <a href="/enwiki/wiki/OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="/enwiki//www.worldcat.org/oclc/895661009">895661009</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Network-on-chip%3A+the+Next+Generation+of+System-on-Chip+Integration&rft.place=Boca+Raton%2C+FL&rft.edition=1st&rft.pub=CRC+Press&rft.date=2014&rft_id=info%3Aoclcnum%2F895661009&rft.isbn=9781466565272&rft.aulast=Kundu&rft.aufirst=Santanu&rft.au=Chattopadhyay%2C+Santanu&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
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<li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite class="citation news cs1"><a rel="nofollow" class="external text" href="http://www.eejournal.com/archives/articles/20110825-mathworks/">"Best Practices for FPGA Prototyping of MATLAB and Simulink Algorithms"</a>. <i>EEJournal</i>. 2011-08-25<span class="reference-accessdate">. Retrieved <span class="nowrap">2018-10-08</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=EEJournal&rft.atitle=Best+Practices+for+FPGA+Prototyping+of+MATLAB+and+Simulink+Algorithms&rft.date=2011-08-25&rft_id=http%3A%2F%2Fwww.eejournal.com%2Farchives%2Farticles%2F20110825-mathworks%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
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<li id="cite_note-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-12">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite id="CITEREFBowyer2005" class="citation web cs1">Bowyer, Bryan (2005-02-05). <a rel="nofollow" class="external text" href="https://www.eetimes.com/document.asp?doc_id=1271261">"The 'why' and 'what' of algorithmic synthesis"</a>. <i><a href="/enwiki/wiki/EE_Times" title="EE Times">EE Times</a></i><span class="reference-accessdate">. Retrieved <span class="nowrap">2018-10-08</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=EE+Times&rft.atitle=The+%27why%27+and+%27what%27+of+algorithmic+synthesis&rft.date=2005-02-05&rft.aulast=Bowyer&rft.aufirst=Bryan&rft_id=https%3A%2F%2Fwww.eetimes.com%2Fdocument.asp%3Fdoc_id%3D1271261&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
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<li id="cite_note-70%_verification?-13"><span class="mw-cite-backlink"><b><a href="#cite_ref-70%_verification?_13-0">^</a></b></span> <span class="reference-text"><a href="/enwiki/wiki/EE_Times" title="EE Times">EE Times</a>. "<a rel="nofollow" class="external text" href="http://www.eetimes.com/author.asp?section_id=36&doc_id=1264922">Is verification really 70 percent?</a>." June 14, 2004. Retrieved July 28, 2015.</span>
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<li id="cite_note-verification_vs._validation-14"><span class="mw-cite-backlink"><b><a href="#cite_ref-verification_vs._validation_14-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.softwaretestingclass.com/difference-between-verification-and-validation/">"Difference between Verification and Validation"</a>. <i>Software Testing Class</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2018-04-30</span></span>. <q>In interviews most of the interviewers are asking questions on “What is Difference between Verification and Validation?” Many people use verification and validation interchangeably but both have different meanings.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Software+Testing+Class&rft.atitle=Difference+between+Verification+and+Validation&rft_id=http%3A%2F%2Fwww.softwaretestingclass.com%2Fdifference-between-verification-and-validation%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
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<li id="cite_note-nm_prototyping-15"><span class="mw-cite-backlink"><b><a href="#cite_ref-nm_prototyping_15-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite id="CITEREFRittman2006" class="citation web cs1">Rittman, Danny (2006-01-05). <a rel="nofollow" class="external text" href="http://www.tayden.com/publications/Nanometer%20Prototyping.pdf">"Nanometer prototyping"</a> <span class="cs1-format">(PDF)</span>. <i>Tayden Design</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2018-10-07</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tayden+Design&rft.atitle=Nanometer+prototyping&rft.date=2006-01-05&rft.aulast=Rittman&rft.aufirst=Danny&rft_id=http%3A%2F%2Fwww.tayden.com%2Fpublications%2FNanometer%2520Prototyping.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
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<li id="cite_note-Reason_to_debug_in_FPGA-16"><span class="mw-cite-backlink"><b><a href="#cite_ref-Reason_to_debug_in_FPGA_16-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.design-reuse.com/articles/13550/fpga-prototyping-to-structured-asic-production-to-reduce-cost-risk-ttm.html">"FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk & TTM"</a>. <i>Design And Reuse</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2018-10-07</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Design+And+Reuse&rft.atitle=FPGA+Prototyping+to+Structured+ASIC+Production+to+Reduce+Cost%2C+Risk+%26+TTM&rft_id=http%3A%2F%2Fwww.design-reuse.com%2Farticles%2F13550%2Ffpga-prototyping-to-structured-asic-production-to-reduce-cost-risk-ttm.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
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<li id="cite_note-17"><span class="mw-cite-backlink"><b><a href="#cite_ref-17">^</a></b></span> <span class="reference-text">Brian Bailey, EE Times. "<a rel="nofollow" class="external text" href="http://www.eetimes.com/document.asp?doc_id=1317504">Tektronix hopes to shake up ASIC prototyping</a>." October 30, 2012. Retrieved July 28, 2015.</span>
</li>
<li id="cite_note-:2-18"><span class="mw-cite-backlink">^ <a href="#cite_ref-:2_18-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:2_18-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-:2_18-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-:2_18-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite id="CITEREFOgrenci-Memik2015" class="citation book cs1">Ogrenci-Memik, Seda (2015). <i>Heat Management in Integrated circuits: On-chip and system-level monitoring and cooling</i>. London, United Kingdom: The Institution of Engineering and Technology. <a href="/enwiki/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/enwiki/wiki/Special:BookSources/9781849199353" title="Special:BookSources/9781849199353"><bdi>9781849199353</bdi></a>. <a href="/enwiki/wiki/OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="/enwiki//www.worldcat.org/oclc/934678500">934678500</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Heat+Management+in+Integrated+circuits%3A+On-chip+and+system-level+monitoring+and+cooling&rft.place=London%2C+United+Kingdom&rft.pub=The+Institution+of+Engineering+and+Technology&rft.date=2015&rft_id=info%3Aoclcnum%2F934678500&rft.isbn=9781849199353&rft.aulast=Ogrenci-Memik&rft.aufirst=Seda&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
</li>
<li id="cite_note-19"><span class="mw-cite-backlink"><b><a href="#cite_ref-19">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite id="CITEREFLin2007" class="citation book cs1">Lin, Youn-Long Steve (2007). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=7OV9lEn9LiQC&pg=PA176"><i>Essential Issues in SOC Design: Designing Complex Systems-on-Chip</i></a>. <a href="/enwiki/wiki/Springer_Science_%26_Business_Media" class="mw-redirect" title="Springer Science & Business Media">Springer Science & Business Media</a>. p. 176. <a href="/enwiki/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/enwiki/wiki/Special:BookSources/9781402053528" title="Special:BookSources/9781402053528"><bdi>9781402053528</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Essential+Issues+in+SOC+Design%3A+Designing+Complex+Systems-on-Chip&rft.pages=176&rft.pub=Springer+Science+%26+Business+Media&rft.date=2007&rft.isbn=9781402053528&rft.aulast=Lin&rft.aufirst=Youn-Long+Steve&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3D7OV9lEn9LiQC%26pg%3DPA176&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
</li>
<li id="cite_note-20"><span class="mw-cite-backlink"><b><a href="#cite_ref-20">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://numato.com/blog/differences-between-fpga-and-asics/">"FPGA vs ASIC: Differences between them and which one to use? – Numato Lab Help Center"</a>. <i>numato.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2018-10-17</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=numato.com&rft.atitle=FPGA+vs+ASIC%3A+Differences+between+them+and+which+one+to+use%3F+%E2%80%93+Numato+Lab+Help+Center&rft_id=https%3A%2F%2Fnumato.com%2Fblog%2Fdifferences-between-fpga-and-asics%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
</li>
<li id="cite_note-21"><span class="mw-cite-backlink"><b><a href="#cite_ref-21">^</a></b></span> <span class="reference-text"><a href="/enwiki/wiki/EE_Times" title="EE Times">EE Times</a>. "<a rel="nofollow" class="external text" href="http://www.eetimes.com/document.asp?doc_id=1153043">The Great Debate: SOC vs. SIP</a>." March 21, 2005. Retrieved July 28, 2015.</span>
</li>
<li id="cite_note-22"><span class="mw-cite-backlink"><b><a href="#cite_ref-22">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.ece.ust.hk/~eexu/COSMIC.html">"COSMIC"</a>. <i>www.ece.ust.hk</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2018-10-08</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.ece.ust.hk&rft.atitle=COSMIC&rft_id=http%3A%2F%2Fwww.ece.ust.hk%2F~eexu%2FCOSMIC.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></span>
</li>
</ol></div></div>
<h2><span class="mw-headline" id="Further_reading">Further reading</span></h2>
<ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite id="CITEREFBadawyJullien2003" class="citation book cs1">Badawy, Wael; Jullien, Graham A., eds. (2003). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=Ha76NqrqPVIC"><i>System-on-Chip for Real-Time Applications</i></a>. Kluwer international series in engineering and computer science, SECS 711. Boston: <a href="/enwiki/wiki/Wolters_Kluwer" title="Wolters Kluwer">Kluwer Academic Publishers</a>. <a href="/enwiki/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/enwiki/wiki/Special:BookSources/9781402072543" title="Special:BookSources/9781402072543"><bdi>9781402072543</bdi></a>. <a href="/enwiki/wiki/OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="/enwiki//www.worldcat.org/oclc/50478525">50478525</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=System-on-Chip+for+Real-Time+Applications&rft.place=Boston&rft.series=Kluwer+international+series+in+engineering+and+computer+science%2C+SECS+711&rft.pub=Kluwer+Academic+Publishers&rft.date=2003&rft_id=info%3Aoclcnum%2F50478525&rft.isbn=9781402072543&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DHa76NqrqPVIC&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span> 465 pages.</li>
<li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite id="CITEREFFurber,_Stephen_B.2000" class="citation book cs1">Furber, Stephen B. (2000). <a href="/enwiki/wiki/ARM_system-on-chip_architecture" class="mw-redirect" title="ARM system-on-chip architecture"><i>ARM system-on-chip architecture</i></a>. Boston: Addison-Wesley. <a href="/enwiki/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/enwiki/wiki/Special:BookSources/0-201-67519-6" title="Special:BookSources/0-201-67519-6"><bdi>0-201-67519-6</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=ARM+system-on-chip+architecture&rft.place=Boston&rft.pub=Addison-Wesley&rft.date=2000&rft.isbn=0-201-67519-6&rft.au=Furber%2C+Stephen+B.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></li>
<li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r999302996"/><cite id="CITEREFKunduChattopadhyay2014" class="citation book cs1">Kundu, Santanu; Chattopadhyay, Santanu (2014). <i>Network-on-chip: the Next Generation of System-on-Chip Integration</i> (1st ed.). Boca Raton, FL: CRC Press. <a href="/enwiki/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/enwiki/wiki/Special:BookSources/9781466565272" title="Special:BookSources/9781466565272"><bdi>9781466565272</bdi></a>. <a href="/enwiki/wiki/OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="/enwiki//www.worldcat.org/oclc/895661009">895661009</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Network-on-chip%3A+the+Next+Generation+of+System-on-Chip+Integration&rft.place=Boca+Raton%2C+FL&rft.edition=1st&rft.pub=CRC+Press&rft.date=2014&rft_id=info%3Aoclcnum%2F895661009&rft.isbn=9781466565272&rft.aulast=Kundu&rft.aufirst=Santanu&rft.au=Chattopadhyay%2C+Santanu&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASystem+on+a+chip" class="Z3988"></span></li></ul>
<h2><span class="mw-headline" id="External_links">External links</span></h2>
<ul><li><a rel="nofollow" class="external text" href="http://www.ieee-socc.org/">SOCC</a> Annual <a href="/enwiki/wiki/Institute_of_Electrical_and_Electronics_Engineers" title="Institute of Electrical and Electronics Engineers">IEEE</a> International SoC Conference</li>
<li><a rel="nofollow" class="external text" href="http://www.edautils.com/Baya.html">Baya</a> free SoC platform assembly and IP integration tool</li>
<li><a rel="nofollow" class="external text" href="http://www.eng.auburn.edu/~nelson/courses/elec5260_6260/Systems%20on%20Chip%20(SoC).pdf">Systems on Chip for Embedded Applications</a>, <a href="/enwiki/wiki/Auburn_University" title="Auburn University">Auburn University</a> seminar in <a href="/enwiki/wiki/Very-large-scale_integration" class="mw-redirect" title="Very-large-scale integration">VLSI</a></li>
<li><a rel="nofollow" class="external text" href="http://www.fpga-cores.com/instant-soc/">Instant SoC</a> SoC for FPGAs defined by C++</li></ul>
<div role="navigation" class="navbox" aria-labelledby="System_on_a_chip_(SoC)" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><style data-mw-deduplicate="TemplateStyles:r992953826">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}.mw-parser-output .infobox .navbar{font-size:100%}.mw-parser-output .navbox .navbar{display:block;font-size:100%}.mw-parser-output .navbox-title .navbar{float:left;text-align:left;margin-right:0.5em}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/enwiki/wiki/Template:System_on_a_chip" title="Template:System on a chip"><abbr title="View this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">v</abbr></a></li><li class="nv-talk"><a href="/enwiki/wiki/Template_talk:System_on_a_chip" title="Template talk:System on a chip"><abbr title="Discuss this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">t</abbr></a></li><li class="nv-edit"><a class="external text" href="https://en.wikipedia.org/enwiki/w/index.php?title=Template:System_on_a_chip&action=edit"><abbr title="Edit this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">e</abbr></a></li></ul></div><div id="System_on_a_chip_(SoC)" style="font-size:114%;margin:0 4em"><a class="mw-selflink selflink">System on a chip</a> (SoC)</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Microprocessor" title="Microprocessor">Microprocessor</a>
<ul><li><a href="/enwiki/wiki/Central_processing_unit" title="Central processing unit">cores</a></li>
<li><a href="/enwiki/wiki/Chipset" title="Chipset">controllers</a></li></ul></li>
<li><a href="/enwiki/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li>
<li><a href="/enwiki/wiki/Image_processor" title="Image processor">Image processor</a></li>
<li><a href="/enwiki/wiki/Media_processor" title="Media processor">Media processor</a></li>
<li><a href="/enwiki/wiki/AI_accelerator" title="AI accelerator">AI accelerator</a></li>
<li><a href="/enwiki/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list navbox-even hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li>
<li><a href="/enwiki/wiki/Multiprocessor_system_on_a_chip" title="Multiprocessor system on a chip">Multiprocessor SoC</a> (MPSoC)</li>
<li><a href="/enwiki/wiki/Programmable_system_on_a_chip" class="mw-redirect" title="Programmable system on a chip">Programmable SoC</a> (PSoC)</li>
<li><a href="/enwiki/wiki/Microcontroller" title="Microcontroller">Microcontroller</a> (MCU)</li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Alternatives</th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li>
<li><a href="/enwiki/wiki/System_in_a_package" title="System in a package">System in a package</a> (SiP)</li>
<li><a href="/enwiki/wiki/Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list navbox-even hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Processor_(computing)" title="Processor (computing)">Processor</a>
<ul><li><a href="/enwiki/wiki/Microprocessor_chronology" title="Microprocessor chronology">chronology</a></li>
<li><a href="/enwiki/wiki/Processor_design" title="Processor design">design</a></li></ul></li>
<li><a href="/enwiki/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li>
<li><a href="/enwiki/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li>
<li><a href="/enwiki/wiki/Embedded_system" title="Embedded system">Embedded systems</a></li>
<li><a href="/enwiki/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li>
<li><a href="/enwiki/wiki/List_of_system_on_a_chip_suppliers" title="List of system on a chip suppliers">List of SoC suppliers</a></li>
<li><a href="/enwiki/wiki/Mobile_computing" title="Mobile computing">Mobile computing</a></li>
<li><a href="/enwiki/wiki/Unified_memory" class="mw-redirect" title="Unified memory">Unified memory</a></li></ul>
</div></td></tr></tbody></table></div><div role="navigation" class="navbox" aria-labelledby="Processor_technologies" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r992953826"/><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/enwiki/wiki/Template:Processor_technologies" title="Template:Processor technologies"><abbr title="View this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">v</abbr></a></li><li class="nv-talk"><a href="/enwiki/wiki/Template_talk:Processor_technologies" title="Template talk:Processor technologies"><abbr title="Discuss this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">t</abbr></a></li><li class="nv-edit"><a class="external text" href="https://en.wikipedia.org/enwiki/w/index.php?title=Template:Processor_technologies&action=edit"><abbr title="Edit this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">e</abbr></a></li></ul></div><div id="Processor_technologies" style="font-size:114%;margin:0 4em"><a href="/enwiki/wiki/Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Abstract_machine" title="Abstract machine">Abstract machine</a></li>
<li><a href="/enwiki/wiki/Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li>
<li><a href="/enwiki/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a>
<ul><li><a href="/enwiki/wiki/Finite_state_machine_with_datapath" class="mw-redirect" title="Finite state machine with datapath">with datapath</a></li>
<li><a href="/enwiki/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li>
<li><a href="/enwiki/wiki/Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li>
<li><a href="/enwiki/wiki/Queue_automaton" title="Queue automaton">Queue automaton</a></li>
<li><a href="/enwiki/wiki/Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li>
<li><a href="/enwiki/wiki/Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li>
<li><a href="/enwiki/wiki/Turing_machine" title="Turing machine">Turing machine</a>
<ul><li><a href="/enwiki/wiki/Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li>
<li><a href="/enwiki/wiki/Universal_Turing_machine" title="Universal Turing machine">Universal</a></li>
<li><a href="/enwiki/wiki/Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li>
<li><a href="/enwiki/wiki/Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li>
<li><a href="/enwiki/wiki/Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li>
<li><a href="/enwiki/wiki/Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li>
<li><a href="/enwiki/wiki/Hypercomputation" title="Hypercomputation">Hypercomputation</a></li>
<li><a href="/enwiki/wiki/Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li>
<li><a href="/enwiki/wiki/History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li>
<li><a href="/enwiki/wiki/Stack_machine" title="Stack machine">Stack machine</a></li>
<li><a href="/enwiki/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a>
<ul><li><a href="/enwiki/wiki/Finite_state_machine_with_datapath" class="mw-redirect" title="Finite state machine with datapath">with datapath</a></li>
<li><a href="/enwiki/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li>
<li><a href="/enwiki/wiki/Queue_automaton" title="Queue automaton">Queue automaton</a></li></ul></li>
<li><a href="/enwiki/wiki/Register_machine" title="Register machine">Register machines</a>
<ul><li><a href="/enwiki/wiki/Counter_machine" title="Counter machine">Counter</a></li>
<li><a href="/enwiki/wiki/Pointer_machine" title="Pointer machine">Pointer</a></li>
<li><a href="/enwiki/wiki/Random-access_machine" title="Random-access machine">Random-access</a></li>
<li><a href="/enwiki/wiki/Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list navbox-even hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></li>
<li><a href="/enwiki/wiki/Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li>
<li><a href="/enwiki/wiki/Harvard_architecture" title="Harvard architecture">Harvard</a>
<ul><li><a href="/enwiki/wiki/Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li>
<li><a href="/enwiki/wiki/Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li>
<li><a href="/enwiki/wiki/Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li>
<li><a href="/enwiki/wiki/Cellular_architecture" title="Cellular architecture">Cellular</a></li>
<li><a href="/enwiki/wiki/Endianness" title="Endianness">Endianness</a></li>
<li><a href="/enwiki/wiki/Computer_data_storage" title="Computer data storage">Memory access</a>
<ul><li><a href="/enwiki/wiki/Non-uniform_memory_access" title="Non-uniform memory access">NUMA</a></li>
<li><a href="/enwiki/wiki/Heterogenous_Unified_Memory_Access" class="mw-redirect" title="Heterogenous Unified Memory Access">HUMA</a></li>
<li><a href="/enwiki/wiki/Load/store_architecture" class="mw-redirect" title="Load/store architecture">Load/store</a></li>
<li><a href="/enwiki/wiki/Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li>
<li><a href="/enwiki/wiki/Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li>
<li><a href="/enwiki/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a>
<ul><li><a href="/enwiki/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></li>
<li><a href="/enwiki/wiki/Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li>
<li><a href="/enwiki/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li>
<li><a href="/enwiki/wiki/Fabric_computing" title="Fabric computing">Fabric</a></li>
<li><a href="/enwiki/wiki/Multiprocessing" title="Multiprocessing">Multiprocessing</a></li>
<li><a href="/enwiki/wiki/Cognitive_computing" title="Cognitive computing">Cognitive</a></li>
<li><a href="/enwiki/wiki/Neuromorphic_engineering" title="Neuromorphic engineering">Neuromorphic</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set<br />architectures</a></th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li>
<li><a href="/enwiki/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></li>
<li><a href="/enwiki/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></li>
<li><a href="/enwiki/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li>
<li><a href="/enwiki/wiki/Explicit_data_graph_execution" title="Explicit data graph execution">EDGE</a>
<ul><li><a href="/enwiki/wiki/TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li>
<li><a href="/enwiki/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a>
<ul><li><a href="/enwiki/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></li></ul></li>
<li><a href="/enwiki/wiki/Minimal_instruction_set_computer" title="Minimal instruction set computer">MISC</a></li>
<li><a href="/enwiki/wiki/One_instruction_set_computer" class="mw-redirect" title="One instruction set computer">OISC</a></li>
<li><a href="/enwiki/wiki/No_instruction_set_computing" title="No instruction set computing">NISC</a></li>
<li><a href="/enwiki/wiki/Zero_instruction_set_computer" class="mw-redirect" title="Zero instruction set computer">ZISC</a></li>
<li><a href="/enwiki/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li>
<li><a href="/enwiki/wiki/Quantum_computing" title="Quantum computing">Quantum computing</a></li>
<li><a href="/enwiki/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a>
<ul><li><a href="/enwiki/wiki/Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction<br />sets</th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li>
<li><a href="/enwiki/wiki/VAX" title="VAX">VAX</a></li>
<li><a href="/enwiki/wiki/PDP-11_architecture" title="PDP-11 architecture">PDP-11</a></li>
<li><a href="/enwiki/wiki/X86" title="X86">x86</a></li>
<li><a href="/enwiki/wiki/ARM_architecture" title="ARM architecture">ARM</a></li>
<li><a href="/enwiki/wiki/Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li>
<li><a href="/enwiki/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></li>
<li><a href="/enwiki/wiki/MIPS-X" title="MIPS-X">MIPS-X</a></li>
<li>Power
<ul><li><a href="/enwiki/wiki/IBM_POWER_instruction_set_architecture" title="IBM POWER instruction set architecture">POWER</a></li>
<li><a href="/enwiki/wiki/PowerPC" title="PowerPC">PowerPC</a></li>
<li><a href="/enwiki/wiki/Power_ISA" title="Power ISA">Power ISA</a></li></ul></li>
<li><a href="/enwiki/wiki/Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li>
<li><a href="/enwiki/wiki/SPARC" title="SPARC">SPARC</a></li>
<li><a href="/enwiki/wiki/SuperH" title="SuperH">SuperH</a></li>
<li><a href="/enwiki/wiki/DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li>
<li><a href="/enwiki/wiki/ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li>
<li><a href="/enwiki/wiki/M32R" title="M32R">M32R</a></li>
<li><a href="/enwiki/wiki/Unicore" title="Unicore">Unicore</a></li>
<li><a href="/enwiki/wiki/IA-64" title="IA-64">Itanium</a></li>
<li><a href="/enwiki/wiki/OpenRISC" title="OpenRISC">OpenRISC</a></li>
<li><a href="/enwiki/wiki/RISC-V" title="RISC-V">RISC-V</a></li>
<li><a href="/enwiki/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>
<li><a href="/enwiki/wiki/Little_man_computer" title="Little man computer">LMC</a></li>
<li>System/3x0
<ul><li><a href="/enwiki/wiki/IBM_System/360_architecture" title="IBM System/360 architecture">S/360</a></li>
<li><a href="/enwiki/wiki/IBM_System/370" title="IBM System/370">S/370</a></li>
<li><a href="/enwiki/wiki/IBM_System/390" title="IBM System/390">S/390</a></li>
<li><a href="/enwiki/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li>
<li><a href="/enwiki/w/index.php?title=Tilera_ISA&action=edit&redlink=1" class="new" title="Tilera ISA (page does not exist)">Tilera ISA</a></li>
<li><a href="/enwiki/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li>
<li><a href="/enwiki/wiki/Adapteva#Products" title="Adapteva">Epiphany architecture</a></li>
<li><a href="/enwiki/wiki/List_of_instruction_sets" class="mw-redirect" title="List of instruction sets">Others</a></li></ul>
</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li>
<li><a href="/enwiki/wiki/Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li>
<li><a href="/enwiki/wiki/Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Data_dependency" title="Data dependency">Data dependency</a></li>
<li><a href="/enwiki/wiki/Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li>
<li><a href="/enwiki/wiki/Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li>
<li><a href="/enwiki/wiki/False_sharing" title="False sharing">False sharing</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Scoreboarding" title="Scoreboarding">Scoreboarding</a></li>
<li><a href="/enwiki/wiki/Tomasulo_algorithm" title="Tomasulo algorithm">Tomasulo algorithm</a>
<ul><li><a href="/enwiki/wiki/Reservation_station" title="Reservation station">Reservation station</a></li>
<li><a href="/enwiki/wiki/Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li>
<li><a href="/enwiki/wiki/Register_renaming" title="Register renaming">Register renaming</a></li>
<li><a href="/enwiki/wiki/Wide-issue" title="Wide-issue">Wide-issue</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Branch_predictor" title="Branch predictor">Branch prediction</a></li>
<li><a href="/enwiki/wiki/Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul>
</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Bit-level_parallelism" title="Bit-level parallelism">Bit</a>
<ul><li><a href="/enwiki/wiki/Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li>
<li><a href="/enwiki/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word</a></li></ul></li>
<li><a href="/enwiki/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li>
<li><a href="/enwiki/wiki/Instruction_pipelining" title="Instruction pipelining">Pipelining</a>
<ul><li><a href="/enwiki/wiki/Scalar_processor" title="Scalar processor">Scalar</a></li>
<li><a href="/enwiki/wiki/Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li>
<li><a href="/enwiki/wiki/Task_parallelism" title="Task parallelism">Task</a>
<ul><li><a href="/enwiki/wiki/Thread_(computing)" title="Thread (computing)">Thread</a></li>
<li><a href="/enwiki/wiki/Process_(computing)" title="Process (computing)">Process</a></li></ul></li>
<li><a href="/enwiki/wiki/Data_parallelism" title="Data parallelism">Data</a>
<ul><li><a href="/enwiki/wiki/Vector_processor" title="Vector processor">Vector</a></li></ul></li>
<li><a href="/enwiki/wiki/Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li>
<li><a href="/enwiki/wiki/Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Temporal_multithreading" title="Temporal multithreading">Temporal</a></li>
<li><a href="/enwiki/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a>
<ul><li><a href="/enwiki/wiki/Hyper-threading" title="Hyper-threading">Hyperthreading</a></li></ul></li>
<li><a href="/enwiki/wiki/Speculative_multithreading" title="Speculative multithreading">Speculative</a></li>
<li><a href="/enwiki/wiki/Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li>
<li><a href="/enwiki/wiki/Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Flynn%27s_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/SISD" title="SISD">SISD</a></li>
<li><a href="/enwiki/wiki/SIMD" title="SIMD">SIMD</a>
<ul><li><a href="/enwiki/wiki/Single_instruction,_multiple_threads" title="Single instruction, multiple threads">Array Processing (SIMT)</a></li>
<li><a href="/enwiki/wiki/Flynn%27s_taxonomy#Pipelined_Processor" title="Flynn's taxonomy">Pipelined Processing</a></li>
<li><a href="/enwiki/wiki/Flynn%27s_taxonomy#Associative_Processor" title="Flynn's taxonomy">Associative Processing</a></li>
<li><a href="/enwiki/wiki/SWAR" title="SWAR">SWAR</a></li></ul></li>
<li><a href="/enwiki/wiki/MISD" title="MISD">MISD</a></li>
<li><a href="/enwiki/wiki/MIMD" title="MIMD">MIMD</a>
<ul><li><a href="/enwiki/wiki/SPMD" title="SPMD">SPMD</a></li></ul></li></ul>
</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Computer_performance" title="Computer performance">Processor<br />performance</a></th><td class="navbox-list navbox-even hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Transistor_count" title="Transistor count">Transistor count</a></li>
<li><a href="/enwiki/wiki/Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC)
<ul><li><a href="/enwiki/wiki/Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li>
<li><a href="/enwiki/wiki/Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li>
<li><a href="/enwiki/wiki/FLOPS" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li>
<li><a href="/enwiki/wiki/Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li>
<li><a href="/enwiki/wiki/SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li>
<li><a href="/enwiki/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li>
<li><a href="/enwiki/wiki/Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li>
<li><a href="/enwiki/wiki/Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li>
<li><a href="/enwiki/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)
<ul><li><a href="/enwiki/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li>
<li><a href="/enwiki/wiki/Vector_processor" title="Vector processor">Vector</a></li>
<li><a href="/enwiki/wiki/Barrel_processor" title="Barrel processor">Barrel</a></li>
<li><a href="/enwiki/wiki/Stream_processing" title="Stream processing">Stream</a></li>
<li><a href="/enwiki/wiki/Tile_processor" title="Tile processor">Tile processor</a></li>
<li><a href="/enwiki/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li>
<li><a href="/enwiki/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li>
<li><a href="/enwiki/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li>
<li><a href="/enwiki/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li>
<li><a href="/enwiki/wiki/Field-programmable_object_array" title="Field-programmable object array">FPOA</a></li>
<li><a href="/enwiki/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li>
<li><a href="/enwiki/wiki/Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li>
<li><a href="/enwiki/wiki/System_in_package" class="mw-redirect" title="System in package">System in package</a> (SiP)</li>
<li><a href="/enwiki/wiki/Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul>
</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Embedded_processor" class="mw-redirect" title="Embedded processor">Embedded processor</a></li>
<li><a href="/enwiki/wiki/Microprocessor" title="Microprocessor">Microprocessor</a></li>
<li><a href="/enwiki/wiki/Microcontroller" title="Microcontroller">Microcontroller</a></li>
<li><a href="/enwiki/wiki/Mobile_processor" title="Mobile processor">Mobile</a></li>
<li><a href="/enwiki/wiki/Notebook_processor" title="Notebook processor">Notebook</a></li>
<li><a href="/enwiki/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li>
<li><a href="/enwiki/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">ASIP</a></li>
<li><a href="/enwiki/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems<br />on chip</th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a class="mw-selflink selflink">System on a chip</a> (SoC)</li>
<li><a href="/enwiki/wiki/Multiprocessor_system_on_a_chip" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li>
<li><a href="/enwiki/wiki/Cypress_PSoC" title="Cypress PSoC">Programmable</a> (PSoC)</li>
<li><a href="/enwiki/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware<br />accelerators</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li>
<li><a href="/enwiki/wiki/AI_accelerator" title="AI accelerator">AI accelerator</a></li>
<li><a href="/enwiki/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li>
<li><a href="/enwiki/wiki/Image_processor" title="Image processor">Image processor</a></li>
<li><a href="/enwiki/wiki/Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li>
<li><a href="/enwiki/wiki/Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li>
<li><a href="/enwiki/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li>
<li><a href="/enwiki/wiki/Tensor_processing_unit" class="mw-redirect" title="Tensor processing unit">Tensor processing unit</a> (TPU)</li>
<li><a href="/enwiki/wiki/Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li>
<li><a href="/enwiki/wiki/Network_processor" title="Network processor">Network processor</a></li>
<li><a href="/enwiki/wiki/Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul>
</div></td></tr></tbody></table><div>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/1-bit_computing" title="1-bit computing">1-bit</a></li>
<li><a href="/enwiki/wiki/4-bit_computing" title="4-bit computing">4-bit</a></li>
<li><a href="/enwiki/wiki/8-bit_computing" title="8-bit computing">8-bit</a></li>
<li><a href="/enwiki/wiki/12-bit_computing" title="12-bit computing">12-bit</a></li>
<li><a href="/enwiki/wiki/Apollo_Guidance_Computer" title="Apollo Guidance Computer">15-bit</a></li>
<li><a href="/enwiki/wiki/16-bit_computing" title="16-bit computing">16-bit</a></li>
<li><a href="/enwiki/wiki/24-bit_computing" title="24-bit computing">24-bit</a></li>
<li><a href="/enwiki/wiki/32-bit_computing" title="32-bit computing">32-bit</a></li>
<li><a href="/enwiki/wiki/48-bit_computing" title="48-bit computing">48-bit</a></li>
<li><a href="/enwiki/wiki/64-bit_computing" title="64-bit computing">64-bit</a></li>
<li><a href="/enwiki/wiki/128-bit_computing" title="128-bit computing">128-bit</a></li>
<li><a href="/enwiki/wiki/256-bit_computing" title="256-bit computing">256-bit</a></li>
<li><a href="/enwiki/wiki/512-bit_computing" title="512-bit computing">512-bit</a></li>
<li><a href="/enwiki/wiki/Bit_slicing" title="Bit slicing">bit slicing</a></li>
<li><a href="/enwiki/wiki/Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a>
<ul><li><a href="/enwiki/wiki/Word_(computer_architecture)#Variable_word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list navbox-even hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Single-core" title="Single-core">Single-core</a></li>
<li><a href="/enwiki/wiki/Multi-core_processor" title="Multi-core processor">Multi-core</a></li>
<li><a href="/enwiki/wiki/Manycore_processor" title="Manycore processor">Manycore</a></li>
<li><a href="/enwiki/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Processor_core" class="mw-redirect" title="Processor core">Core</a></li>
<li><a href="/enwiki/wiki/Cache_(computing)" title="Cache (computing)">Cache</a>
<ul><li><a href="/enwiki/wiki/CPU_cache" title="CPU cache">CPU cache</a></li>
<li><a href="/enwiki/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li>
<li><a href="/enwiki/wiki/Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li>
<li><a href="/enwiki/wiki/Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li>
<li><a href="/enwiki/wiki/Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li>
<li><a href="/enwiki/wiki/Cache_coherence" title="Cache coherence">coherence</a></li></ul></li>
<li><a href="/enwiki/wiki/Bus_(computing)" title="Bus (computing)">Bus</a></li>
<li><a href="/enwiki/wiki/Clock_rate" title="Clock rate">Clock rate</a></li>
<li><a href="/enwiki/wiki/Clock_signal" title="Clock signal">Clock signal</a></li>
<li><a href="/enwiki/wiki/FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFO</a></li></ul>
</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Execution_unit" title="Execution unit">Functional units</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li>
<li><a href="/enwiki/wiki/Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li>
<li><a href="/enwiki/wiki/Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li>
<li><a href="/enwiki/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU)
<ul><li><a href="/enwiki/wiki/Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li>
<li><a href="/enwiki/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li>
<li><a href="/enwiki/wiki/Branch_predictor" title="Branch predictor">Branch predictor</a></li>
<li><a href="/enwiki/wiki/Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li>
<li><a href="/enwiki/wiki/Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC)
<ul><li><a href="/enwiki/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li>
<li><a href="/enwiki/wiki/Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Digital_logic" class="mw-redirect" title="Digital logic">Logic</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Combinational_logic" title="Combinational logic">Combinational</a></li>
<li><a href="/enwiki/wiki/Sequential_logic" title="Sequential logic">Sequential</a></li>
<li><a href="/enwiki/wiki/Glue_logic" title="Glue logic">Glue</a></li>
<li><a href="/enwiki/wiki/Logic_gate" title="Logic gate">Logic gate</a>
<ul><li><a href="/enwiki/wiki/Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li>
<li><a href="/enwiki/wiki/Gate_array" title="Gate array">Array</a></li></ul></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Processor_register" title="Processor register">Processor register</a></li>
<li><a href="/enwiki/wiki/Status_register" title="Status register">Status register</a></li>
<li><a href="/enwiki/wiki/Stack_register" title="Stack register">Stack register</a></li>
<li><a href="/enwiki/wiki/Register_file" title="Register file">Register file</a></li>
<li><a href="/enwiki/wiki/Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li>
<li><a href="/enwiki/wiki/Memory_address_register" title="Memory address register">Memory address register</a></li>
<li><a href="/enwiki/wiki/Program_counter" title="Program counter">Program counter</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li>
<li><a href="/enwiki/wiki/Instruction_unit" title="Instruction unit">Instruction unit</a></li>
<li><a href="/enwiki/wiki/Data_buffer" title="Data buffer">Data buffer</a></li>
<li><a href="/enwiki/wiki/Write_buffer" title="Write buffer">Write buffer</a></li>
<li><a href="/enwiki/wiki/Microcode" title="Microcode">Microcode</a> <a href="/enwiki/wiki/ROM_image" title="ROM image">ROM</a></li>
<li><a href="/enwiki/wiki/Microcode#Horizontal_microcode" title="Microcode">Horizontal microcode</a></li>
<li><a href="/enwiki/wiki/Counter_(digital)" title="Counter (digital)">Counter</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Datapath" title="Datapath">Datapath</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Multiplexer" title="Multiplexer">Multiplexer</a></li>
<li><a href="/enwiki/wiki/Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li>
<li><a href="/enwiki/wiki/Adder_(electronics)" title="Adder (electronics)">Adder</a></li>
<li><a href="/enwiki/wiki/Binary_multiplier" title="Binary multiplier">Multiplier</a>
<ul><li><a href="/enwiki/wiki/CPU_multiplier" title="CPU multiplier">CPU</a></li></ul></li>
<li><a href="/enwiki/wiki/Binary_decoder" title="Binary decoder">Binary decoder</a>
<ul><li><a href="/enwiki/wiki/Address_decoder" title="Address decoder">Address decoder</a></li>
<li><a href="/enwiki/wiki/Sum_addressed_decoder" class="mw-redirect" title="Sum addressed decoder">Sum addressed decoder</a></li></ul></li>
<li><a href="/enwiki/wiki/Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a>
<ul><li><a href="/enwiki/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D</a></li>
<li><a href="/enwiki/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li>
<li><a href="/enwiki/wiki/Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li>
<li><a href="/enwiki/wiki/Boolean_circuit" title="Boolean circuit">Boolean</a></li>
<li><a href="/enwiki/wiki/Digital_circuit" class="mw-redirect" title="Digital circuit">Digital</a></li>
<li><a href="/enwiki/wiki/Analog_circuit" class="mw-redirect" title="Analog circuit">Analog</a></li>
<li><a href="/enwiki/wiki/Quantum_circuit" title="Quantum circuit">Quantum</a></li>
<li><a href="/enwiki/wiki/Switch#Electronic_switches" title="Switch">Switch</a></li></ul>
</div></td></tr></tbody></table><div>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Power_management" title="Power management">Power<br />management</a></th><td class="navbox-list navbox-even hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Power_Management_Unit" title="Power Management Unit">PMU</a></li>
<li><a href="/enwiki/wiki/Advanced_Power_Management" title="Advanced Power Management">APM</a></li>
<li><a href="/enwiki/wiki/Advanced_Configuration_and_Power_Interface" title="Advanced Configuration and Power Interface">ACPI</a></li>
<li><a href="/enwiki/wiki/Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li>
<li><a href="/enwiki/wiki/Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li>
<li><a href="/enwiki/wiki/Clock_gating" title="Clock gating">Clock gating</a></li>
<li><a href="/enwiki/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li>
<li><a href="/enwiki/w/index.php?title=Race_to_sleep&action=edit&redlink=1" class="new" title="Race to sleep (page does not exist)">Race to sleep</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li>
<li><a href="/enwiki/wiki/Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li>
<li><a href="/enwiki/wiki/Processor_design" title="Processor design">Processor design</a></li>
<li><a href="/enwiki/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></li>
<li><a href="/enwiki/wiki/Hardware_security_module" title="Hardware security module">Hardware security module</a></li>
<li><a href="/enwiki/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li>
<li><a href="/enwiki/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li>
<li><a href="/enwiki/wiki/Pin_grid_array" title="Pin grid array">Pin grid array</a></li>
<li><a href="/enwiki/wiki/Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul>
</div></td></tr></tbody></table></div>
<div role="navigation" class="navbox" aria-labelledby="Single-board_computer_and_single-board_microcontroller" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r992953826"/><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/enwiki/wiki/Template:Single-board_computer" title="Template:Single-board computer"><abbr title="View this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">v</abbr></a></li><li class="nv-talk"><a href="/enwiki/wiki/Template_talk:Single-board_computer" title="Template talk:Single-board computer"><abbr title="Discuss this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">t</abbr></a></li><li class="nv-edit"><a class="external text" href="https://en.wikipedia.org/enwiki/w/index.php?title=Template:Single-board_computer&action=edit"><abbr title="Edit this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">e</abbr></a></li></ul></div><div id="Single-board_computer_and_single-board_microcontroller" style="font-size:114%;margin:0 4em"><a href="/enwiki/wiki/Single-board_computer" title="Single-board computer">Single-board computer</a> and <a href="/enwiki/wiki/Single-board_microcontroller" title="Single-board microcontroller">single-board microcontroller</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Devices</th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Arduino" title="Arduino">Arduino</a></li>
<li><a href="/enwiki/wiki/Arndale_Board" title="Arndale Board">Arndale Board</a></li>
<li><a href="/enwiki/wiki/Asus_Tinker_Board" title="Asus Tinker Board">Asus Tinker Board</a></li>
<li><a href="/enwiki/wiki/Banana_Pi" title="Banana Pi">Banana Pi</a></li>
<li><a href="/enwiki/wiki/BeagleBoard" title="BeagleBoard">BeagleBoard</a></li>
<li><a href="/enwiki/wiki/Cotton_Candy_(single-board_computer)" title="Cotton Candy (single-board computer)">Cotton Candy</a></li>
<li><a href="/enwiki/wiki/CHIP_(computer)" title="CHIP (computer)">CHIP</a></li>
<li><a href="/enwiki/wiki/Cubieboard" title="Cubieboard">Cubieboard</a></li>
<li><a href="/enwiki/wiki/Intel_Edison" title="Intel Edison">Edison</a></li>
<li><a href="/enwiki/wiki/Intel_Galileo" title="Intel Galileo">Galileo</a></li>
<li><a href="/enwiki/wiki/Gumstix" title="Gumstix">Gumstix</a></li>
<li><a href="/enwiki/wiki/Hawkboard" title="Hawkboard">Hawkboard</a></li>
<li><a href="/enwiki/wiki/IGEPv2" title="IGEPv2">IGEPv2</a></li>
<li><a href="/enwiki/wiki/Drive_PX-series" class="mw-redirect" title="Drive PX-series">Nvidia Drive</a></li>
<li><a href="/enwiki/wiki/Nvidia_Jetson" title="Nvidia Jetson">Nvidia Jetson</a></li>
<li><a href="/enwiki/wiki/ODROID" title="ODROID">ODROID</a></li>
<li><a href="/enwiki/wiki/OLinuXino" title="OLinuXino">OLinuXino</a></li>
<li><a href="/enwiki/wiki/PandaBoard" title="PandaBoard">PandaBoard</a></li>
<li><a href="/enwiki/wiki/Pine64" title="Pine64">Pine64</a></li>
<li><a href="/enwiki/wiki/Adapteva#Parallella_project" title="Adapteva">Parallella</a></li>
<li><a href="/enwiki/wiki/Rascal_(single-board_computer)" title="Rascal (single-board computer)">Rascal</a></li>
<li><a href="/enwiki/wiki/Raspberry_Pi" title="Raspberry Pi">Raspberry Pi</a></li>
<li><a href="/enwiki/wiki/Snowball_(single-board_computer)" title="Snowball (single-board computer)">Snowball</a></li>
<li><a href="/enwiki/w/index.php?title=UDOO&action=edit&redlink=1" class="new" title="UDOO (page does not exist)">UDOO</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a class="mw-selflink selflink">SoCs</a></th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/ARM_architecture" title="ARM architecture">ARM</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Actions_Semiconductor" title="Actions Semiconductor">Actions</a></li>
<li><a href="/enwiki/wiki/Allwinner_Technology#SoC_.28System_on_Chip.29" title="Allwinner Technology">Allwinner</a></li>
<li><a href="/enwiki/wiki/Apple_silicon#A_series" title="Apple silicon">Ax</a></li>
<li><a href="/enwiki/wiki/Apple_M1" title="Apple M1">Apple M1</a></li>
<li><a href="/enwiki/wiki/Exynos_(system_on_chip)" class="mw-redirect" title="Exynos (system on chip)">Exynos</a></li>
<li><a href="/enwiki/wiki/I.MX" title="I.MX">i.MX</a></li>
<li><a href="/enwiki/wiki/HiSilicon#K3V3" title="HiSilicon">HiSiliconK3V3</a></li>
<li><a href="/enwiki/wiki/MediaTek" title="MediaTek">MediaTek</a></li>
<li><a href="/enwiki/wiki/Nomadik" title="Nomadik">Nomadik</a></li>
<li><a href="/enwiki/wiki/NovaThor" title="NovaThor">NovaThor</a></li>
<li><a href="/enwiki/wiki/OMAP" title="OMAP">OMAP</a></li>
<li><a href="/enwiki/wiki/Rockchip" title="Rockchip">Rockchip</a></li>
<li><a href="/enwiki/wiki/Qualcomm_Snapdragon" title="Qualcomm Snapdragon">Qualcomm Snapdragon</a></li>
<li><a href="/enwiki/wiki/Tegra" title="Tegra">Tegra</a></li>
<li><a href="/enwiki/wiki/WonderMedia#Products" title="WonderMedia">WonderMedia</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Ingenic#XBurst1-based_SoCs" class="mw-redirect" title="Ingenic">Jz</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/X86" title="X86">x86</a>/<a href="/enwiki/wiki/X86-64" title="X86-64">x86-64</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Atom_(system_on_chip)" class="mw-redirect" title="Atom (system on chip)">Atom</a></li>
<li><a href="/enwiki/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar</a>-based</li>
<li><a href="/enwiki/wiki/Puma_(microarchitecture)" title="Puma (microarchitecture)">Puma</a>-based</li>
<li><a href="/enwiki/wiki/Intel_Quark" title="Intel Quark">Quark</a></li></ul>
</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Apache_Hadoop" title="Apache Hadoop">Apache Hadoop</a></li>
<li><a href="/enwiki/wiki/Linaro" title="Linaro">Linaro</a></li></ul>
</div></td></tr></tbody></table></div>
<div role="navigation" class="navbox" aria-labelledby="Programmable_logic" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r992953826"/><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/enwiki/wiki/Template:Programmable_Logic" title="Template:Programmable Logic"><abbr title="View this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">v</abbr></a></li><li class="nv-talk"><a href="/enwiki/wiki/Template_talk:Programmable_Logic" title="Template talk:Programmable Logic"><abbr title="Discuss this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">t</abbr></a></li><li class="nv-edit"><a class="external text" href="https://en.wikipedia.org/enwiki/w/index.php?title=Template:Programmable_Logic&action=edit"><abbr title="Edit this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">e</abbr></a></li></ul></div><div id="Programmable_logic" style="font-size:114%;margin:0 4em"><a href="/enwiki/wiki/Programmable_logic_device" title="Programmable logic device">Programmable logic</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Concepts</th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li>
<li><a class="mw-selflink selflink">SoC</a></li>
<li><a href="/enwiki/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a>
<ul><li><a href="/enwiki/wiki/Logic_block" title="Logic block">Logic block</a></li></ul></li>
<li><a href="/enwiki/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li>
<li><a href="/enwiki/wiki/Erasable_programmable_logic_device" class="mw-redirect" title="Erasable programmable logic device">EPLD</a></li>
<li><a href="/enwiki/wiki/Programmable_logic_array" title="Programmable logic array">PLA</a></li>
<li><a href="/enwiki/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li>
<li><a href="/enwiki/wiki/Generic_array_logic" title="Generic array logic">GAL</a></li>
<li><a href="/enwiki/wiki/Programmable_system-on-chip" class="mw-redirect" title="Programmable system-on-chip">PSoC</a></li>
<li><a href="/enwiki/wiki/Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a>
<ul><li><a href="/enwiki/wiki/Xputer" title="Xputer">Xputer</a></li></ul></li>
<li><a href="/enwiki/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li>
<li><a href="/enwiki/wiki/Circuit_underutilization" title="Circuit underutilization">Circuit underutilization</a></li>
<li><a href="/enwiki/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li>
<li><a href="/enwiki/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Hardware_description_language" title="Hardware description language">Languages</a></th><td class="navbox-list navbox-even hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Verilog" title="Verilog">Verilog</a>
<ul><li><a href="/enwiki/wiki/Verilog-A" title="Verilog-A">A</a></li>
<li><a href="/enwiki/wiki/Verilog-AMS" title="Verilog-AMS">AMS</a></li></ul></li>
<li><a href="/enwiki/wiki/VHDL" title="VHDL">VHDL</a>
<ul><li><a href="/enwiki/wiki/VHDL-AMS" title="VHDL-AMS">AMS</a></li>
<li><a href="/enwiki/wiki/VHDL-VITAL" title="VHDL-VITAL">VITAL</a></li></ul></li>
<li><a href="/enwiki/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a>
<ul><li><a href="/enwiki/wiki/SystemVerilog_DPI" title="SystemVerilog DPI">DPI</a></li></ul></li>
<li><a href="/enwiki/wiki/SystemC" title="SystemC">SystemC</a></li>
<li><a href="/enwiki/wiki/Altera_Hardware_Description_Language" title="Altera Hardware Description Language">AHDL</a></li>
<li><a href="/enwiki/wiki/Handel-C" title="Handel-C">Handel-C</a></li>
<li><a href="/enwiki/wiki/Lola_(computing)" title="Lola (computing)">Lola</a></li>
<li><a href="/enwiki/wiki/Property_Specification_Language" title="Property Specification Language">PSL</a></li>
<li><a href="/enwiki/wiki/Unified_Power_Format" title="Unified Power Format">UPF</a></li>
<li><a href="/enwiki/wiki/PALASM" title="PALASM">PALASM</a></li>
<li><a href="/enwiki/wiki/Advanced_Boolean_Expression_Language" title="Advanced Boolean Expression Language">ABEL</a></li>
<li><a href="/enwiki/wiki/Programmable_Array_Logic#CUPL" title="Programmable Array Logic">CUPL</a></li>
<li><a href="/enwiki/wiki/OpenVera" title="OpenVera">OpenVera</a></li>
<li><a href="/enwiki/wiki/C_to_HDL" title="C to HDL">C to HDL</a></li>
<li><a href="/enwiki/wiki/Flow_to_HDL" title="Flow to HDL">Flow to HDL</a></li>
<li><a href="/enwiki/wiki/MyHDL" title="MyHDL">MyHDL</a></li>
<li><a href="/enwiki/wiki/JHDL" title="JHDL">JHDL</a></li>
<li><a href="/enwiki/wiki/ELLA_(programming_language)" title="ELLA (programming language)">ELLA</a></li>
<li><a href="/enwiki/wiki/Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Companies</th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Accellera" title="Accellera">Accellera</a></li>
<li><a href="/enwiki/wiki/Achronix" title="Achronix">Achronix</a></li>
<li><a href="/enwiki/wiki/Advanced_Micro_Devices" title="Advanced Micro Devices">AMD</a></li>
<li><a href="/enwiki/wiki/Aldec" title="Aldec">Aldec</a></li>
<li><a href="/enwiki/wiki/Arm_Ltd." title="Arm Ltd.">Arm Ltd.</a></li>
<li><a href="/enwiki/wiki/Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a></li>
<li><a href="/enwiki/wiki/Infineon_Technologies" title="Infineon Technologies">Infineon</a></li>
<li><a href="/enwiki/wiki/Intel" title="Intel">Intel</a></li>
<li><a href="/enwiki/wiki/Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a></li>
<li><a href="/enwiki/wiki/Microchip_Technology" title="Microchip Technology">Microchip Technology</a></li>
<li><a href="/enwiki/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a></li>
<li><a href="/enwiki/wiki/Siemens" title="Siemens">Siemens</a>
<ul><li><a href="/enwiki/wiki/Mentor_Graphics" title="Mentor Graphics">Mentor Graphics</a></li></ul></li>
<li><a href="/enwiki/wiki/Synopsys" title="Synopsys">Synopsys</a></li>
<li><a href="/enwiki/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a></li>
<li><a href="/enwiki/wiki/Xilinx" title="Xilinx">Xilinx</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/ICE_(FPGA)" title="ICE (FPGA)">iCE</a></li>
<li><a href="/enwiki/wiki/Stratix" title="Stratix">Stratix</a></li>
<li><a href="/enwiki/wiki/Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Intel_Quartus_Prime" title="Intel Quartus Prime">Intel Quartus Prime</a></li>
<li><a href="/enwiki/wiki/Xilinx_ISE" title="Xilinx ISE">Xilinx ISE</a></li>
<li><a href="/enwiki/wiki/Xilinx_Vivado" title="Xilinx Vivado">Xilinx Vivado</a></li>
<li><a href="/enwiki/wiki/ModelSim" title="ModelSim">ModelSim</a></li>
<li><a href="/enwiki/wiki/Verilog-to-Routing" title="Verilog-to-Routing">VTR</a></li>
<li><a href="/enwiki/wiki/List_of_HDL_simulators" title="List of HDL simulators">Simulators</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Intellectual_property" title="Intellectual property">Intellectual<br />property</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Proprietary_hardware" title="Proprietary hardware">Proprietary</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li>
<li><a href="/enwiki/wiki/ARM_Cortex-M" title="ARM Cortex-M">ARM Cortex-M</a></li>
<li><a href="/enwiki/wiki/LEON" title="LEON">LEON</a></li>
<li><a href="/enwiki/wiki/LatticeMico8" title="LatticeMico8">LatticeMico8</a></li>
<li><a href="/enwiki/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>
<li><a href="/enwiki/wiki/PicoBlaze" title="PicoBlaze">PicoBlaze</a></li>
<li><a href="/enwiki/wiki/Nios_embedded_processor" title="Nios embedded processor">Nios</a></li>
<li><a href="/enwiki/wiki/Nios_II" title="Nios II">Nios II</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Open-source_hardware" title="Open-source hardware">Open-source</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Java_Optimized_Processor" title="Java Optimized Processor">JOP</a></li>
<li><a href="/enwiki/wiki/LatticeMico32" title="LatticeMico32">LatticeMico32</a></li>
<li><a href="/enwiki/wiki/OpenCores" title="OpenCores">OpenCores</a></li>
<li><a href="/enwiki/wiki/OpenRISC" title="OpenRISC">OpenRISC</a>
<ul><li><a href="/enwiki/wiki/OpenRISC_1200" title="OpenRISC 1200">1200</a></li></ul></li>
<li><a href="/enwiki/wiki/Power_ISA" title="Power ISA">Power ISA</a>
<ul><li><a href="/enwiki/wiki/Libre-SOC" title="Libre-SOC">Libre-SOC</a></li>
<li><a href="/enwiki/wiki/OpenPower_Microwatt" class="mw-redirect" title="OpenPower Microwatt">Microwatt</a></li></ul></li>
<li><a href="/enwiki/wiki/RISC-V" title="RISC-V">RISC-V</a></li>
<li><a href="/enwiki/wiki/Zet_(hardware)" title="Zet (hardware)">Zet</a></li></ul>
</div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table></div>
<div role="navigation" class="navbox" aria-labelledby="Computer_science" style="padding:3px"><table class="nowraplinks hlist mw-collapsible mw-collapsed navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="3"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r992953826"/><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/enwiki/wiki/Template:Computer_science" title="Template:Computer science"><abbr title="View this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">v</abbr></a></li><li class="nv-talk"><a href="/enwiki/wiki/Template_talk:Computer_science" title="Template talk:Computer science"><abbr title="Discuss this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">t</abbr></a></li><li class="nv-edit"><a class="external text" href="https://en.wikipedia.org/enwiki/w/index.php?title=Template:Computer_science&action=edit"><abbr title="Edit this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">e</abbr></a></li></ul></div><div id="Computer_science" style="font-size:114%;margin:0 4em"><a href="/enwiki/wiki/Computer_science" title="Computer science">Computer science</a></div></th></tr><tr><td class="navbox-abovebelow" colspan="3"><div id="Note:_This_template_roughly_follows_the_2012_ACM_Computing_Classification_System.">Note: This template roughly follows the 2012 <a href="/enwiki/wiki/ACM_Computing_Classification_System" title="ACM Computing Classification System">ACM Computing Classification System</a>.</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Computer_hardware" title="Computer hardware">Hardware</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li>
<li><a href="/enwiki/wiki/Peripheral" title="Peripheral">Peripheral</a></li>
<li><a href="/enwiki/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a></li>
<li><a href="/enwiki/wiki/Very_Large_Scale_Integration" title="Very Large Scale Integration">Very Large Scale Integration</a></li>
<li><a class="mw-selflink selflink">Systems on Chip (SoCs)</a></li>
<li><a href="/enwiki/wiki/Green_computing" title="Green computing">Energy consumption (Green computing)</a></li>
<li><a href="/enwiki/wiki/Electronic_design_automation" title="Electronic design automation">Electronic design automation</a></li>
<li><a href="/enwiki/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul>
</div></td><td class="noviewer navbox-image" rowspan="17" style="width:1px;padding:0px 0px 0px 2px"><div><a href="/enwiki/wiki/File:Computer_Retro.svg" class="image"><img alt="Computer Retro.svg" src="/upwiki/wikipedia/commons/thumb/5/51/Computer_Retro.svg/50px-Computer_Retro.svg.png" decoding="async" width="50" height="50" srcset="/upwiki/wikipedia/commons/thumb/5/51/Computer_Retro.svg/75px-Computer_Retro.svg.png 1.5x, /upwiki/wikipedia/commons/thumb/5/51/Computer_Retro.svg/100px-Computer_Retro.svg.png 2x" data-file-width="512" data-file-height="512" /></a></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Computer systems organization</th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Computer_architecture" title="Computer architecture">Computer architecture</a></li>
<li><a href="/enwiki/wiki/Embedded_system" title="Embedded system">Embedded system</a></li>
<li><a href="/enwiki/wiki/Real-time_computing" title="Real-time computing">Real-time computing</a></li>
<li><a href="/enwiki/wiki/Dependability" title="Dependability">Dependability</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Computer_network" title="Computer network">Networks</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Network_architecture" title="Network architecture">Network architecture</a></li>
<li><a href="/enwiki/wiki/Network_protocol" class="mw-redirect" title="Network protocol">Network protocol</a></li>
<li><a href="/enwiki/wiki/Networking_hardware" title="Networking hardware">Network components</a></li>
<li><a href="/enwiki/wiki/Network_scheduler" title="Network scheduler">Network scheduler</a></li>
<li><a href="/enwiki/wiki/Network_performance" title="Network performance">Network performance evaluation</a></li>
<li><a href="/enwiki/wiki/Network_service" title="Network service">Network service</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software organization</th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Interpreter_(computing)" title="Interpreter (computing)">Interpreter</a></li>
<li><a href="/enwiki/wiki/Middleware" title="Middleware">Middleware</a></li>
<li><a href="/enwiki/wiki/Virtual_machine" title="Virtual machine">Virtual machine</a></li>
<li><a href="/enwiki/wiki/Operating_system" title="Operating system">Operating system</a></li>
<li><a href="/enwiki/wiki/Software_quality" title="Software quality">Software quality</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Programming_language_theory" title="Programming language theory">Software notations</a> and <a href="/enwiki/wiki/Programming_tool" title="Programming tool">tools</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Programming_paradigm" title="Programming paradigm">Programming paradigm</a></li>
<li><a href="/enwiki/wiki/Programming_language" title="Programming language">Programming language</a></li>
<li><a href="/enwiki/wiki/Compiler_construction" class="mw-redirect" title="Compiler construction">Compiler</a></li>
<li><a href="/enwiki/wiki/Domain-specific_language" title="Domain-specific language">Domain-specific language</a></li>
<li><a href="/enwiki/wiki/Modeling_language" title="Modeling language">Modeling language</a></li>
<li><a href="/enwiki/wiki/Software_framework" title="Software framework">Software framework</a></li>
<li><a href="/enwiki/wiki/Integrated_development_environment" title="Integrated development environment">Integrated development environment</a></li>
<li><a href="/enwiki/wiki/Software_configuration_management" title="Software configuration management">Software configuration management</a></li>
<li><a href="/enwiki/wiki/Library_(computing)" title="Library (computing)">Software library</a></li>
<li><a href="/enwiki/wiki/Software_repository" title="Software repository">Software repository</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Software_development" title="Software development">Software development</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Control_variable_(programming)" title="Control variable (programming)">Control variable</a></li>
<li><a href="/enwiki/wiki/Software_development_process" title="Software development process">Software development process</a></li>
<li><a href="/enwiki/wiki/Requirements_analysis" title="Requirements analysis">Requirements analysis</a></li>
<li><a href="/enwiki/wiki/Software_design" title="Software design">Software design</a></li>
<li><a href="/enwiki/wiki/Software_construction" title="Software construction">Software construction</a></li>
<li><a href="/enwiki/wiki/Software_deployment" title="Software deployment">Software deployment</a></li>
<li><a href="/enwiki/wiki/Software_maintenance" title="Software maintenance">Software maintenance</a></li>
<li><a href="/enwiki/wiki/Programming_team" title="Programming team">Programming team</a></li>
<li><a href="/enwiki/wiki/Open-source_software" title="Open-source software">Open-source model</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Theory_of_computation" title="Theory of computation">Theory of computation</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Model_of_computation" title="Model of computation">Model of computation</a></li>
<li><a href="/enwiki/wiki/Formal_language" title="Formal language">Formal language</a></li>
<li><a href="/enwiki/wiki/Automata_theory" title="Automata theory">Automata theory</a></li>
<li><a href="/enwiki/wiki/Computability_theory" title="Computability theory">Computability theory</a></li>
<li><a href="/enwiki/wiki/Computational_complexity_theory" title="Computational complexity theory">Computational complexity theory</a></li>
<li><a href="/enwiki/wiki/Logic_in_computer_science" title="Logic in computer science">Logic</a></li>
<li><a href="/enwiki/wiki/Semantics_(computer_science)" title="Semantics (computer science)">Semantics</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Algorithm" title="Algorithm">Algorithms</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Algorithm_design" class="mw-redirect" title="Algorithm design">Algorithm design</a></li>
<li><a href="/enwiki/wiki/Analysis_of_algorithms" title="Analysis of algorithms">Analysis of algorithms</a></li>
<li><a href="/enwiki/wiki/Algorithmic_efficiency" title="Algorithmic efficiency">Algorithmic efficiency</a></li>
<li><a href="/enwiki/wiki/Randomized_algorithm" title="Randomized algorithm">Randomized algorithm</a></li>
<li><a href="/enwiki/wiki/Computational_geometry" title="Computational geometry">Computational geometry</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Mathematics of computing</th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Discrete_mathematics" title="Discrete mathematics">Discrete mathematics</a></li>
<li><a href="/enwiki/wiki/Probability" title="Probability">Probability</a></li>
<li><a href="/enwiki/wiki/Statistics" title="Statistics">Statistics</a></li>
<li><a href="/enwiki/wiki/Mathematical_software" title="Mathematical software">Mathematical software</a></li>
<li><a href="/enwiki/wiki/Information_theory" title="Information theory">Information theory</a></li>
<li><a href="/enwiki/wiki/Mathematical_analysis" title="Mathematical analysis">Mathematical analysis</a></li>
<li><a href="/enwiki/wiki/Numerical_analysis" title="Numerical analysis">Numerical analysis</a></li>
<li><a href="/enwiki/wiki/Theoretical_computer_science" title="Theoretical computer science">Theoretical computer science</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Information_system" title="Information system">Information systems</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Database" title="Database">Database management system</a></li>
<li><a href="/enwiki/wiki/Computer_data_storage" title="Computer data storage">Information storage systems</a></li>
<li><a href="/enwiki/wiki/Enterprise_information_system" title="Enterprise information system">Enterprise information system</a></li>
<li><a href="/enwiki/wiki/Social_software" title="Social software">Social information systems</a></li>
<li><a href="/enwiki/wiki/Geographic_information_system" title="Geographic information system">Geographic information system</a></li>
<li><a href="/enwiki/wiki/Decision_support_system" title="Decision support system">Decision support system</a></li>
<li><a href="/enwiki/wiki/Process_control" title="Process control">Process control system</a></li>
<li><a href="/enwiki/wiki/Multimedia_database" title="Multimedia database">Multimedia information system</a></li>
<li><a href="/enwiki/wiki/Data_mining" title="Data mining">Data mining</a></li>
<li><a href="/enwiki/wiki/Digital_library" title="Digital library">Digital library</a></li>
<li><a href="/enwiki/wiki/Computing_platform" title="Computing platform">Computing platform</a></li>
<li><a href="/enwiki/wiki/Digital_marketing" title="Digital marketing">Digital marketing</a></li>
<li><a href="/enwiki/wiki/World_Wide_Web" title="World Wide Web">World Wide Web</a></li>
<li><a href="/enwiki/wiki/Information_retrieval" title="Information retrieval">Information retrieval</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Computer_security" title="Computer security">Security</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Cryptography" title="Cryptography">Cryptography</a></li>
<li><a href="/enwiki/wiki/Formal_methods" title="Formal methods">Formal methods</a></li>
<li><a href="/enwiki/wiki/Security_service_(telecommunication)" title="Security service (telecommunication)">Security services</a></li>
<li><a href="/enwiki/wiki/Intrusion_detection_system" title="Intrusion detection system">Intrusion detection system</a></li>
<li><a href="/enwiki/wiki/Computer_security_compromised_by_hardware_failure" title="Computer security compromised by hardware failure">Hardware security</a></li>
<li><a href="/enwiki/wiki/Network_security" title="Network security">Network security</a></li>
<li><a href="/enwiki/wiki/Information_security" title="Information security">Information security</a></li>
<li><a href="/enwiki/wiki/Application_security" title="Application security">Application security</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Human%E2%80%93computer_interaction" title="Human–computer interaction">Human–computer interaction</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Interaction_design" title="Interaction design">Interaction design</a></li>
<li><a href="/enwiki/wiki/Social_computing" title="Social computing">Social computing</a></li>
<li><a href="/enwiki/wiki/Ubiquitous_computing" title="Ubiquitous computing">Ubiquitous computing</a></li>
<li><a href="/enwiki/wiki/Visualization_(graphics)" title="Visualization (graphics)">Visualization</a></li>
<li><a href="/enwiki/wiki/Computer_accessibility" title="Computer accessibility">Accessibility</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Concurrency_(computer_science)" title="Concurrency (computer science)">Concurrency</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Concurrent_computing" title="Concurrent computing">Concurrent computing</a></li>
<li><a href="/enwiki/wiki/Parallel_computing" title="Parallel computing">Parallel computing</a></li>
<li><a href="/enwiki/wiki/Distributed_computing" title="Distributed computing">Distributed computing</a></li>
<li><a href="/enwiki/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></li>
<li><a href="/enwiki/wiki/Multiprocessing" title="Multiprocessing">Multiprocessing</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Artificial_intelligence" title="Artificial intelligence">Artificial intelligence</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Natural_language_processing" title="Natural language processing">Natural language processing</a></li>
<li><a href="/enwiki/wiki/Knowledge_representation_and_reasoning" title="Knowledge representation and reasoning">Knowledge representation and reasoning</a></li>
<li><a href="/enwiki/wiki/Computer_vision" title="Computer vision">Computer vision</a></li>
<li><a href="/enwiki/wiki/Automated_planning_and_scheduling" title="Automated planning and scheduling">Automated planning and scheduling</a></li>
<li><a href="/enwiki/wiki/Mathematical_optimization" title="Mathematical optimization">Search methodology</a></li>
<li><a href="/enwiki/wiki/Control_theory" title="Control theory">Control method</a></li>
<li><a href="/enwiki/wiki/Philosophy_of_artificial_intelligence" title="Philosophy of artificial intelligence">Philosophy of artificial intelligence</a></li>
<li><a href="/enwiki/wiki/Distributed_artificial_intelligence" title="Distributed artificial intelligence">Distributed artificial intelligence</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Machine_learning" title="Machine learning">Machine learning</a></th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Supervised_learning" title="Supervised learning">Supervised learning</a></li>
<li><a href="/enwiki/wiki/Unsupervised_learning" title="Unsupervised learning">Unsupervised learning</a></li>
<li><a href="/enwiki/wiki/Reinforcement_learning" title="Reinforcement learning">Reinforcement learning</a></li>
<li><a href="/enwiki/wiki/Multi-task_learning" title="Multi-task learning">Multi-task learning</a></li>
<li><a href="/enwiki/wiki/Cross-validation_(statistics)" title="Cross-validation (statistics)">Cross-validation</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Computer_graphics" title="Computer graphics">Graphics</a></th><td class="navbox-list navbox-even" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Computer_animation" title="Computer animation">Animation</a></li>
<li><a href="/enwiki/wiki/Rendering_(computer_graphics)" title="Rendering (computer graphics)">Rendering</a></li>
<li><a href="/enwiki/wiki/Photo_manipulation" class="mw-redirect" title="Photo manipulation">Image manipulation</a></li>
<li><a href="/enwiki/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a></li>
<li><a href="/enwiki/wiki/Mixed_reality" title="Mixed reality">Mixed reality</a></li>
<li><a href="/enwiki/wiki/Virtual_reality" title="Virtual reality">Virtual reality</a></li>
<li><a href="/enwiki/wiki/Image_compression" title="Image compression">Image compression</a></li>
<li><a href="/enwiki/wiki/Solid_modeling" title="Solid modeling">Solid modeling</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Applied computing</th><td class="navbox-list navbox-odd" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/E-commerce" title="E-commerce">E-commerce</a></li>
<li><a href="/enwiki/wiki/Enterprise_software" title="Enterprise software">Enterprise software</a></li>
<li><a href="/enwiki/wiki/Computational_mathematics" title="Computational mathematics">Computational mathematics</a></li>
<li><a href="/enwiki/wiki/Computational_physics" title="Computational physics">Computational physics</a></li>
<li><a href="/enwiki/wiki/Computational_chemistry" title="Computational chemistry">Computational chemistry</a></li>
<li><a href="/enwiki/wiki/Computational_biology" title="Computational biology">Computational biology</a></li>
<li><a href="/enwiki/wiki/Computational_social_science" title="Computational social science">Computational social science</a></li>
<li><a href="/enwiki/wiki/Computational_engineering" title="Computational engineering">Computational engineering</a></li>
<li><a href="/enwiki/wiki/Health_informatics" title="Health informatics">Computational healthcare</a></li>
<li><a href="/enwiki/wiki/Digital_art" title="Digital art">Digital art</a></li>
<li><a href="/enwiki/wiki/Electronic_publishing" title="Electronic publishing">Electronic publishing</a></li>
<li><a href="/enwiki/wiki/Cyberwarfare" title="Cyberwarfare">Cyberwarfare</a></li>
<li><a href="/enwiki/wiki/Electronic_voting" title="Electronic voting">Electronic voting</a></li>
<li><a href="/enwiki/wiki/Video_game" title="Video game">Video games</a></li>
<li><a href="/enwiki/wiki/Word_processor" title="Word processor">Word processing</a></li>
<li><a href="/enwiki/wiki/Operations_research" title="Operations research">Operations research</a></li>
<li><a href="/enwiki/wiki/Educational_technology" title="Educational technology">Educational technology</a></li>
<li><a href="/enwiki/wiki/Document_management_system" title="Document management system">Document management</a></li></ul>
</div></td></tr><tr><td class="navbox-abovebelow" colspan="3"><div>
<ul><li><a href="/enwiki/wiki/File:Symbol_category_class.svg" class="image" title="Category"><img alt="Category" src="/upwiki/wikipedia/en/thumb/9/96/Symbol_category_class.svg/16px-Symbol_category_class.svg.png" decoding="async" width="16" height="16" srcset="/upwiki/wikipedia/en/thumb/9/96/Symbol_category_class.svg/23px-Symbol_category_class.svg.png 1.5x, /upwiki/wikipedia/en/thumb/9/96/Symbol_category_class.svg/31px-Symbol_category_class.svg.png 2x" data-file-width="180" data-file-height="185" /></a> <b><a href="/enwiki/wiki/Category:Computer_science" title="Category:Computer science">Category</a></b></li>
<li><a href="/enwiki/wiki/File:Global_thinking.svg" class="image" title="Outline"><img alt="Outline" src="/upwiki/wikipedia/commons/thumb/4/41/Global_thinking.svg/10px-Global_thinking.svg.png" decoding="async" width="10" height="16" srcset="/upwiki/wikipedia/commons/thumb/4/41/Global_thinking.svg/15px-Global_thinking.svg.png 1.5x, /upwiki/wikipedia/commons/thumb/4/41/Global_thinking.svg/21px-Global_thinking.svg.png 2x" data-file-width="130" data-file-height="200" /></a> <b><a href="/enwiki/wiki/Outline_of_computer_science" title="Outline of computer science">Outline</a></b></li>
<li><a href="/enwiki/wiki/File:People_icon.svg" class="image" title="WikiProject"><img alt="WikiProject" src="/upwiki/wikipedia/commons/thumb/3/37/People_icon.svg/16px-People_icon.svg.png" decoding="async" width="16" height="16" srcset="/upwiki/wikipedia/commons/thumb/3/37/People_icon.svg/24px-People_icon.svg.png 1.5x, /upwiki/wikipedia/commons/thumb/3/37/People_icon.svg/32px-People_icon.svg.png 2x" data-file-width="100" data-file-height="100" /></a><b><a href="/enwiki/wiki/Wikipedia:WikiProject_Computer_science" title="Wikipedia:WikiProject Computer science">WikiProject</a></b></li>
<li><a href="/enwiki/wiki/File:Commons-logo.svg" class="image" title="Commons page"><img alt="Commons page" src="/upwiki/wikipedia/en/thumb/4/4a/Commons-logo.svg/12px-Commons-logo.svg.png" decoding="async" width="12" height="16" srcset="/upwiki/wikipedia/en/thumb/4/4a/Commons-logo.svg/18px-Commons-logo.svg.png 1.5x, /upwiki/wikipedia/en/thumb/4/4a/Commons-logo.svg/24px-Commons-logo.svg.png 2x" data-file-width="1024" data-file-height="1376" /></a> <b><a href="https://commons.wikimedia.org/wiki/Category:Computer_science" class="extiw" title="commons:Category:Computer science">Commons</a></b></li></ul>
</div></td></tr></tbody></table></div>
<div role="navigation" class="navbox" aria-labelledby="Hardware_acceleration" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r992953826"/><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/enwiki/wiki/Template:Hardware_acceleration" title="Template:Hardware acceleration"><abbr title="View this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">v</abbr></a></li><li class="nv-talk"><a href="/enwiki/wiki/Template_talk:Hardware_acceleration" title="Template talk:Hardware acceleration"><abbr title="Discuss this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">t</abbr></a></li><li class="nv-edit"><a class="external text" href="https://en.wikipedia.org/enwiki/w/index.php?title=Template:Hardware_acceleration&action=edit"><abbr title="Edit this template" style=";;background:none transparent;border:none;box-shadow:none;padding:0;">e</abbr></a></li></ul></div><div id="Hardware_acceleration" style="font-size:114%;margin:0 4em"><a href="/enwiki/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Models_of_computation" class="mw-redirect" title="Models of computation">Theory</a></th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Universal_Turing_machine" title="Universal Turing machine">Universal Turing machine</a></li>
<li><a href="/enwiki/wiki/Parallel_computing" title="Parallel computing">Parallel computing</a></li>
<li><a href="/enwiki/wiki/Distributed_computing" title="Distributed computing">Distributed computing</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Applications</th><td class="navbox-list navbox-even hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a>
<ul><li><a href="/enwiki/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li>
<li><a href="/enwiki/wiki/DirectX_Video_Acceleration" title="DirectX Video Acceleration">DirectX</a></li></ul></li>
<li><a href="/enwiki/wiki/Sound_card" title="Sound card">Audio</a></li>
<li><a href="/enwiki/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processing</a></li>
<li><a href="/enwiki/wiki/Hardware_random_number_generator" title="Hardware random number generator">Hardware random number generation</a></li>
<li><a href="/enwiki/wiki/AI_accelerator" title="AI accelerator">Artificial intelligence</a></li>
<li><a href="/enwiki/wiki/Cryptographic_accelerator" title="Cryptographic accelerator">Cryptography</a>
<ul><li><a href="/enwiki/wiki/TLS_acceleration" title="TLS acceleration">TLS</a></li></ul></li>
<li><a href="/enwiki/wiki/Vision_processing_unit" title="Vision processing unit">Machine vision</a></li>
<li><a href="/enwiki/wiki/Custom_hardware_attack" title="Custom hardware attack">Custom hardware attack</a>
<ul><li><a href="/enwiki/wiki/Scrypt" title="Scrypt">scrypt</a></li></ul></li>
<li><a href="/enwiki/wiki/Network_processor" title="Network processor">Networking</a></li>
<li><a href="/enwiki/wiki/Data_processing_unit" title="Data processing unit">Data</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Implementations</th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a>
<ul><li><a href="/enwiki/wiki/C_to_HDL" title="C to HDL">C to HDL</a></li></ul></li>
<li><a href="/enwiki/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li>
<li><a href="/enwiki/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li>
<li><a href="/enwiki/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li>
<li><a class="mw-selflink selflink">System on a chip</a>
<ul><li><a href="/enwiki/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a></li></ul></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/enwiki/wiki/Computer_architecture" title="Computer architecture">Architectures</a></th><td class="navbox-list navbox-even hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Dataflow_architecture" title="Dataflow architecture">Data flow</a></li>
<li><a href="/enwiki/wiki/Transport_triggered_architecture" title="Transport triggered architecture">Transport triggered</a></li>
<li><a href="/enwiki/wiki/Multicore" class="mw-redirect" title="Multicore">Multicore</a></li>
<li><a href="/enwiki/wiki/Manycore" class="mw-redirect" title="Manycore">Manycore</a></li>
<li><a href="/enwiki/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous</a></li>
<li><a href="/enwiki/wiki/In-memory_processing" title="In-memory processing">In-memory computing</a></li>
<li><a href="/enwiki/wiki/Systolic_array" title="Systolic array">Systolic array</a></li>
<li><a href="/enwiki/wiki/Neuromorphic_engineering" title="Neuromorphic engineering">Neuromorphic</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list navbox-odd hlist" style="text-align:left;border-left-width:2px;border-left-style:solid;width:100%;padding:0px"><div style="padding:0em 0.25em">
<ul><li><a href="/enwiki/wiki/Programmable_logic" class="mw-redirect" title="Programmable logic">Programmable logic</a></li>
<li><a href="/enwiki/wiki/Processor_(computing)" title="Processor (computing)">Processor</a>
<ul><li><a href="/enwiki/wiki/Processor_design" title="Processor design">design</a></li>
<li><a href="/enwiki/wiki/Microprocessor_chronology" title="Microprocessor chronology">chronology</a></li></ul></li>
<li><a href="/enwiki/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></li>
<li><a href="/enwiki/wiki/Virtualization" title="Virtualization">Virtualization</a>
<ul><li><a href="/enwiki/wiki/Hardware_emulation" title="Hardware emulation">Hardware emulation</a></li></ul></li>
<li><a href="/enwiki/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li>
<li><a href="/enwiki/wiki/Embedded_system" title="Embedded system">Embedded systems</a></li></ul>
</div></td></tr></tbody></table></div>
' |
Whether or not the change was made through a Tor exit node (tor_exit_node) | false |
Unix timestamp of change (timestamp) | 1629598090 |
